MEMORY存储芯片TMS320C6455DZTZA中文规格书

SPRS146N − FEBRUARY 2001 − REVISED MAY 2005peripheral register descriptions (continued)

Table 17. HPI Registers

HEX ADDRESS RANGE

−0188 00000188 00040188 0008

0188 000C − 0189 FFFF

018A 0000

018A 0004 − 018B FFFF

†

ACRONYMHPIDHPICHPIA(HPIAW)†HPIA(HPIAR)†

−TRCTL−

HPI data registerHPI control register

REGISTER NAMECOMMENTS

Host read/write access onlyHPIC has both Host/CPUread/write accessHPIA has both Host/CPUread/write access

HPI address register (Write)HPI address register (Read)Reserved

HPI transfer request control registerReserved

Host access to the HPIA register updates both the HPIAW and HPIAR registers. The CPU can access HPIAW and HPIAR independently.

Table 18. GPIO Registers

HEX ADDRESS RANGE

01B0 000001B0 000401B0 000801B0 000C01B0 001001B0 001401B0 001801B0 001C01B0 002001B0 0024

01B0 0028 − 01B0 01FF

01B0 0200

01B0 0204 − 01B3 FFFF

ACRONYMGPENGPDIRGPVAL−GPDHGPHMGPDLGPLMGPGCGPPOL−DEVICE_REV

−

REGISTER NAME

GPIO enable registerGPIO direction registerGPIO value registerReserved

GPIO delta high registerGPIO high mask registerGPIO delta low registerGPIO low mask registerGPIO global control registerGPIO interrupt polarity registerReserved

Silicon Revision Identification Register

(For more details, see the device characteristics listed in Table 1.)Reserved

TMS320C6414, TMS320C6415, TMS320C6416FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS146N − FEBRUARY 2001 − REVISED MAY 2005signal groups description

CLKIN

CLKOUT4/GP1†CLKOUT6/GP2†

CLKMODE1CLKMODE0

PLLV

Clock/PLLReset andInterruptsRESETNMI

GP7/EXT_INT7‡GP6/EXT_INT6‡GP5/EXT_INT5‡GP4/EXT_INT4‡

TMSTDOTDITCKTRSTEMU0EMU1EMU2EMU3EMU4EMU5EMU6EMU7EMU8EMU9EMU10EMU11

ReservedRSVRSVRSVRSVRSVRSV

IEEE Standard1149.1(JTAG)EmulationRSVRSVRSV

•••

PeripheralControl/StatusPCI_EN

MCBSP2_EN

Control/StatusGP15/PRST§GP14/PCLK§GP13/PINTA§GP12/PGNT§GP11/PREQ§GP10/PCBE3§GP9/PIDSEL§CLKS2/GP8†

GPIOGP7/EXT_INT7‡GP6/EXT_INT6‡GP5/EXT_INT5‡GP4/EXT_INT4‡GP3

CLKOUT6/GP2†CLKOUT4/GP1†GP0

General-Purpose Input/Output (GPIO) Port†These pins are muxed with the GPIO port pins and by default these signals function as clocks (CLKOUT4 or CLKOUT6) or McBSP2clock source (CLKS2). To use these muxed pins as GPIO signals, the appropriate GPIO register bits (GPxEN and GPxDIR) must beproperly enabled and configured. For more details, see the Device Configurations section of this data sheet.

‡These pins are GPIO pins that can also function as external interrupt sources (EXT_INT[7:4]). Default after reset is EXT_INTx orGPIO as input-only.

§For the C6415 and C6416 devices, these GPIO pins are muxed with the PCI peripheral pins. By default, these signals are set up tono function with both the GPIO and PCI pin functions disabled. For more details on these muxed pins, see the Device Configurationssection of this data sheet. For the C6414 device, the GPIO peripheral pins are not muxed; the C6414 device does not support thePCI peripheral.

Figure 3. CPU and Peripheral Signals