RDA5802E datasheet_v1_6

RDA5802E

SINGLE-CHIP BROADCAST FM RADIO TUNER Rev.1.6–Jun.2009

1 General Description

The RDA5802E (RDA5802 Enhanced) is a single-chip broadcast FM stereo radio tuner with fully integrated synthesizer, IF selectivity and MPX decoder. The tuner uses the CMOS process, support multi-interface and require the least external component. The package size is 4X4mm and is completely adjustment-free. All these make it very suitable for portable devices. The RDA5802E has a powerful low-IF digital audio processor, this make it have optimum sound quality with varying reception conditions. The RDA5802E can be tuned to the worldwide frequency band.

Figure 1-1. RDA5802E Top View 1.1

Features

Ø High cut l Programmable de-emphasis (50/75 µs) l Receive signal strength indicator (RSSI) l Bass boost l Volume control l IS digital output interface l Line-level analog output voltage l 32.768 KHz 12M,24M,13M,26M,19.2M,38.4MHz Reference clock l 2-wire and 3-wire serial control bus interface l Directly support 32Ω resistance loading l Integrated LDO regulator Ø 1.8 to 5.5 V operation voltage l 4X4mm 24 pin QFN package and SOP 16Pin 1.2 Applications 2

l CMOS single-chip fully-integrated FM tuner l Low power consumption Ø Total current consumption lower than 22mA at 3.0V power supply l Support worldwide frequency band Ø 65 -108 MHz l Digital low-IF tuner Ø Image-reject down-converter Ø High performance A/D converter Ø IF selectivity performed internally l Fully integrated digital frequency synthesizer Ø Fully integrated on-chip RF and IF VCO Ø Fully integrated on-chip loop filter l Autonomous search tuning l Support 32.768KHz crystal oscillator l Digital auto gain control (AGC) l Digital adaptive noise cancellation Ø Mono/stereo switch Ø Soft mute l Cellular handsets l MP3, MP4 players l Portable radios，PDAs, Notebook Copyright © RDA Microelectronics Inc. 2006. All rights are reserved.

The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA.

RDA Microelectronics, Inc. RDA5802E FM Tuner V1.6

2 Table of Contents

1

General Description....................................................................................................................................1 1.1 Features.........................................................................................................................................1 1.2 Applications....................................................................................................................................1 2 Table of Contents........................................................................................................................................2 3 Functional Description...............................................................................................................................3

3.1 FM Receiver.................................................................................................................................3 3.2 Synthesizer....................................................................................................................................3 3.3 Power Supply................................................................................................................................3 3.4 RESET and Control Interface select.............................................................................................4 3.5 Control Interface...........................................................................................................................4 3.6 I2S Audio Data Interface...............................................................................................................4 3.7 GPIO Outputs...............................................................................................................................4 4 Electrical Characteristics...........................................................................................................................5 5 Receiver Characteristics.............................................................................................................................6 6 Serial Interface............................................................................................................................................7

6.1 Three-wire Interface Timing.........................................................................................................7 6.2 I2C Interface Timing.....................................................................................................................8 7 Register Definition......................................................................................................................................9 8 Pins Description........................................................................................................................................13 9 Application Diagram................................................................................................................................16

9.1 Audio Loading Resistance Larger than 32Ω & TCXO Application:..........................................16 9.1.1 Bill of Materials:.........................................................................................................................16 9.2 Audio Loading Resistance Lower than 32Ω & DCXO Application:..........................................17 9.2.1 Bill of Materials:.........................................................................................................................17 9.3 Audio Loading Resistance Lower than 32Ω & SOP16 Application:..........................................18 9.3.1 Bill of Materials:.........................................................................................................................18 10 Package Physical Dimension....................................................................................................................19 11 PCB Land Pattern....................................................................................................................................21 12 Change List................................................................................................................................................24 13 Notes：.......................................................................................................................................................24 14 RDA5802E与RDA5802对比..................................................................................................................25 15 Contact Information.................................................................................................................................26

The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA. Page 2 of 26

RDA Microelectronics, Inc. RDA5802E FM Tuner V1.6

3 Functional Description

Figure 3-1. RDA5802E FM Tuner Block Diagram 3.1 FM Receiver demodulation, stereo MPX decoder and output audio signal. The MPX decoder can autonomous switch from stereo to mono to limit the output noise. The DACs convert digital audio signal to analog and change the volume at same time. The DACs has low-pass feature and -3dB frequency is about 30 KHz. 3.2 Synthesizer The receiver uses a digital low-IF architecture that avoids the difficulties associated with direct conversion while delivering lower solution cost and reduces complexity, and integrates a low noise amplifier (LNA) supporting the FM broadcast band (65 to 108MHz), a quadrature image-reject mixer, a programmable gain control (PGA), a high resolution analog-to-digital converters (ADCs), an audio DSP and a high- fidelity digital-to-analog converters (DACs). The LNA has differential input ports (LNAP and LNAN) and supports any input port by set according registers bits (LNA_PORT_SEL[1:0]). It default input common mode voltage is GND. The limiter prevents overloading and limits the amount of intermodulation products created by strong adjacent channels.

The quadrature mixer down converts the LNA output differential RF signal to low-IF, it also has image-reject function.

The PGA amplifies the mixer output IF signal and then digitized with ADCs.

The DSP core finishes the channel selection, FM

The frequency synthesizer generates the local oscillator signal which divide to quadrature, then be used to downconvert the RF input to a constant low intermediate frequency (IF). The synthesizer reference clock is 32.768 KHz. The synthesizer frequency is defined by bits CHAN[9:0] with the range from 65MHz to 108MHz. 3.3

Power Supply

The RDA5802E integrated one LDO which supplies power to the chip. The external supply voltage range is 1.8-5.5 V.

The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA. Page 3 of 26

RDA Microelectronics, Inc. RDA5802E FM Tuner V1.6 3.4

RESET and Control Interface select

0x02h high byte, then register 0x02h low byte, then register 0x03h high byte, till the last register. RDA5802E always gives out ACK after every byte, and MCU gives out STOP condition when register programming is finished. For read transfer, after command byte from MCU, RDA5802E sends out register 0x0Ah high byte, then register 0x0Ah low byte, then register 0x0Bh high byte, till receives NACK from MCU. MCU gives out ACK for data bytes besides last data byte. MCU gives out NACK for last data byte, and then RDA5802E will return the bus to MCU, and MCU will give out STOP condition.

Details refer to RDA5802E Programming Guide. 3.6

I2S Audio Data Interface

The RDA5802E is RESET itself When VIO is Power up. And also support soft reset by trigger 02H BIT1 from 0 to 1. The control interface is select by MODE Pin. The MODE Pin is low ,I2C Interface is select. The MODE Pin is set to VIO, SPI Interface is select. 3.5

Control Interface

The RDA5802E supports three- wire and I2C control interface. User could select either of them to program the chip.

The three-wire interface is a standard SPI interface. It includes three pins: SEN, SCLK and SDIO. Each register write is 25-bit long, including 4-bit high register address, a r/w bit, 4-bit low register address, and 16-bit data (MSB is the first bit). RDA5802E samples command byte and data at posedge of SCLK. Each register read is also 25-bit long, including 4-bit high register address, a r/w bit, 4-bit low register address, and 16-bit data (MSB is the first bit) from RDA5802E. The turn around cycle between command byte from MCU and data from RDA5802E is a half cycle. RDA5802E samples command byte at posedge of SCLK, and output data also at posedge of SCLK. The IC interface is compliant to IC Bus Specification 2.1. It includes two pins: SCLK and

2

SDIO. A IC interface transfer begins with START condition, a command byte and data bytes, each byte has a followed ACK (or NACK) bit, and ends with STOP condition. The command byte includes a 7-bit chip address (0010000b) and a R/W bit. The ACK (or NACK) is always sent out by receiver. When in write transfer, data bytes is written out from MCU, and when in read transfer, data bytes is read out from RDA5802E. There is no visible

22

register address in IC interface transfers. The IC interface has a fixed start register address (0x02h for write transfer and 0x0Ah for read transfer), and an internal incremental address counter. If register address meets the end of register file, 0x3Ah, register address will wrap back to 0x00h. For write transfer, MCU programs registers from register 2

2

The RDA5802E supports I2S (Inter_IC Sound Bus) audio interface. The interface is fully compliant with I2S bus specification. When setting I2SEN bit high, RDA5802E will output SCK, WS, SD signals from GPIO3, GPIO1, GPIO2 as I2S master and transmitter, the sample rate is 48Kbps，44.1kbps,32kbps….. RDA5802E also support as I2S slaver mode and transmitter, the sample rate is less than 100kbps.

Details refer to RDA5802E Programming Guide. 3.7

GPIO Outputs

The RDA5802E has three GPIOs. The function of GPIOs could programmed with bits GPIO1[1:0], GPIO2[1:0], GPIO3[1:0] and I2SEN.

If I2SEN is set to low, GPIO pins could be programmed to output low or high or high-Z, or be programmed to output interrupt and stereo indicator with bits GPIO1[1:0], GPIO2[1:0], GPIO3[1:0]. GPIO2 could be programmed to output a low interrupt (interrupt will be generated only with interrupt enable bit STCIEN is set to high) when seek/tune process completes. GPIO3 could be programmed to output stereo indicator bit ST. Constant low, high or high-Z functionality is available regardless of the state of VA and VD supplies or the ENABLE bit SCK WS SD

LEFT CHANNEL1 SCK1 SCKRIGHT CHANNELMSBLSBMSBLSBFigure 3-2. I2S Digital Audio Format The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA. Page 4 of 26

RDA Microelectronics, Inc. RDA5802E FM Tuner V1.6

4 Electrical Characteristics

Table 4-1

SYMBOL

DC Electrical Specification (Recommended Operation Conditions):

DESCRIPTION

Analog Supply Voltage Digital Supply Voltage Interface Supply Voltage Ambient Temperature

CMOS Low Level Input Voltage CMOS High Level Input Voltage CMOS Threshold Voltage

MIN 1.8 1.8 1.5 -20 0 0.7*VDD

TYP 3.3 3.3 - 27 0.5*VDD

MAX 5.5 5.5 3.6 +70 0.3*DVDD DVDD

UNIT V V V ℃ V V V

AVDD DVDD VIO Tamb VIL VIH VTH

Table 4-2 SYMBOL DC Electrical Specification (Absolute Maximum Ratings): DESCRIPTION Interface Supply Voltage Ambient Temperature Input Current (1) Input Voltage(1) LNA FM Input Level MIN -0.5 -40 -10 -0.3 TYP MAX +4 +90 +10 VIO+0.3 -20 UNIT V °C mA V dBm VIO Tamb IIN VIN Vlna Notes: 1. For Pin: SCLK, SDIO, SEN, MODE Table 4-3 Power Consumption Specification (VDD = 1.8 to 5.5 V, TA = -25 to 85 ℃, unless otherwise specified) SYMBOL DESCRIPTION Analog Supply Current Digital Supply Current Interface Supply Current Analog Powerdown Current Digital Powerdown Current Interface Powerdown Current CONDITION ENABLE=1 ENABLE=1 SCLK and RCLK inactive ENABLE=0 ENABLE=0 ENABLE=0 TYP 18 3 90 2 2 10 UNIT mA mA µA µA µA µA IA ID IVIO IAPD IDPD IVIO

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RDA Microelectronics, Inc. RDA5802E FM Tuner V1.6

5 Receiver Characteristics

Table 5-1

Receiver Characteristics

(VDD = 2.7 to 5.5 V, TA = -25 to 85 °C, unless otherwise specified) SYMBOL General specifications BAND=00 Fin FM Input Frequency BAND=01 BAND=10 BAND=11 Vrf Rin Cin IP3in αam S200 Sensitivity1,2,3 LNA Input Resistance 7 LNA Input Capacitance 7 Input IP34 AM Suppression1,2 Adjacent Channel Selectivity Left and Right Audio Frequency VAFL; VAFR Output Voltage (Pins LOUT and ROUT) (S+N)/N αSCS THD αAOI RL Maximum Signal Plus Noise to Noise Ratio1,2,3,5 Stereo Channel Separation Audio Total Harmonic Distortion1,3,6 Audio Output L/R Imbalance Audio Output Loading Resistance Single-ended 55 35 32 60 - 0.03 - - - 0.05 0.1 - dB dB % dB Ω Volume [3:0] =1111 200 mV (S+N)/N=26dB AGCD=1 m=0.3 ±200KHz 87 76 76 65 2 80 40 45 1 150 4 - 108 91 108 76 1.5 6 - - - MHz MHz MHz MHz µV EMF Ω pF dBµV dB dB PARAMETER CONDITIONS MIN TYP MAX UNIT Pins LNAN, LNAP, LOUT, ROUT and NC(22,23) Vcom_rfin Pins LNAN and LNAP Input Common Mode Voltage Audio Output Common Mode Voltage8 Pins NC (22, 23) Common Mode Voltage 0 V Vcom 0.95 1. 1.05 V Vcom_nc Floating V ! The NC(22, 23) pins SHOULD BE left floating. Notes:

1. Fin=65 to 108MHz; Fmod=1KHz; de-emphasis=75µs; MONO=1; L=R unless noted otherwise; 2. ∆f=22.5KHz;

3. BAF = 300Hz to 15KHz, RBW <=10Hz;

4. |f2-f1|>1MHz, f0=2xf1-f2, AGC disable, Fin=76 to 108MHz; 5. PRF=60dBUV; 6. ∆f=75KHz.

7. Measured at VEMF = 1 m V, f RF = 65 to 108MHz 8. At LOUT and ROUT pins

The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA. Page 6 of 26

RDA Microelectronics, Inc. RDA5802E FM Tuner V1.6

6 Serial Interface

6.1

Three-wire Interface Timing

Table 6-1 Three-wire Interface Timing Characteristics

(VDD = 2.7 to 5.5 V, TA = -25 to 85 °C, unless otherwise specified)

PARAMETER SCLK Cycle Time SCLK Rise Time SCLK Fall Time SCLK High Time SCLK Low Time SDIO Input, SEN to SCLK↑ Setup SDIO Input, to SCLK↑ Hold SCLK↑ to SDIO Output Valid SEN↑ to SDIO Output High Z Digital Input Pin Capacitance SYMBOL tCLK tR tF tHI tLO ts th tcdv tsdz TEST CONDITION Read Read MIN 35 10 10 10 10 2 2 TYP - - - - MAX 50 50 - - 10 10 5 UNIT ns ns ns ns ns ns ns ns ns pF Figure 6-1. Three-wire Interface Write Timing Diagram Figure 6-2. Three-wire Interface Read Timing Diagram

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RDA Microelectronics, Inc. RDA5802E FM Tuner V1.6 6.2

I2C Interface Timing

Table 6-2

I2C Interface Timing Characteristics

(VDD = 2.7 to 5.5 V, TA = -25 to 85 °C, unless otherwise specified)

PARAMETER SCLK Frequency SCLK High Time SCLK Low Time Setup Time for START Condition Hold Time for START Condition Setup Time for STOP Condition SDIO Input to SCLK↑ Setup SDIO Input to SCLK↓ Hold STOP to START Time SDIO Output Fall Time SDIO Input, SCLK Rise/Fall Time Input Spike Suppression SCLK, SDIO Capacitive Loading Digital Input Pin Capacitance SYMBOL TEST CONDITION MIN 0 0.6 1.3 0.6 0.6 0.6 100 0 1.3 20+0.1Cb 20+0.1Cb - - TYP - - - - - - - - - - - - - MAX 400 - - - - - - 900 - 250 300 50 50 5 UNIT KHz µs µs µs µs µs ns ns µs ns ns ns pF pF fscl thigh tlow tsu:sta thd:sta tsu:sto tsu:dat thd:dat tbuf tf:out tr:in / tf:in tsp Cb Figure 6-3. IC Interface Write Timing Diagram

2

Figure 6-4. IC Interface Read Timing Diagram

2

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RDA Microelectronics, Inc. RDA5802E FM Tuner V1.6

7 Register Definition

REG BITS 00H 02H 15:8 15 14 13 12 10 DHIZ DMUTE MONO BASS CLK_DIRECT_MODE NAME CHIPID[7:0] Chip ID. FUNCTION Audio Output High-Z Disable. 0 = High impedance; 1 = Normal operation Mute Disable. 0 = Mute; 1 = Normal operation Mono Select. 0 = Stereo; 1 = Force mono Bass Boost. 0 = Disabled; 1 = Bass boost enabled Reference clk (32.768K,12M,…) direct input mode. 0=clk_buffer mode; 1=clk directly input mode DEFAULT 0x58 0 0 0 0 0 9 8 SEEKUP SEEK Seek Up. 0 = Seek down; 1 = Seek up Seek. 0 = Disable stop seek; 1 = Enable Seek begins in the direction specified by SEEKUP and ends when a channel is found with RSSI level above SEEKTH[5:0], or the entire band has been searched. The SEEK bit is set low and the STC bit is set high when the seek operation completes. 0 0 7 SKMODE Seek Mode 0 = wrap at the upper or lower band limit and continue seeking 1 = stop seeking at the upper or lower band limit 0 6:4 CLK_MODE[2:0] 000=32.768kHz 001=12Mhz 101=24Mhz 010=13Mhz 110=26Mhz 011=19.2Mhz 111=38.4Mhz 000 1 SOFT_RESET Soft reset. If 0, not reset; If 1, reset. 0 03H 0 15:6 ENABLE CHAN[9:0] Power Up Enable. 0 = Disabled; 1 = Enabled Channel Select. BAND = 0 0 0x00 The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA. Page 9 of 26

RDA Microelectronics, Inc. RDA5802E FM Tuner V1.6

REG BITS NAME Frequency = FUNCTION Channel Spacing (kHz) x CHAN+ 87.0 MHz BAND = 1or 2 Frequency = Channel Spacing (kHz) x CHAN + 76.0 MHz BAND = 3 Frequency = Channel Spacing (kHz) x CHAN + 65.0 MHz CHAN is updated after a seek operation. DEFAULT 4 TUNE Tune 0 = Disable 1 = Enable The tune operation begins when the TUNE bit is set high. The STC bit is set high when the tune operation completes. The tune bit is reset to low automatically when the tune operation completes.. 0 3:2 BAND[1:0] Band Select. 00 = 87–108 MHz (US/Europe) 01 = 76–91 MHz (Japan) 10 = 76–108 MHz (world wide) 11 = 65 –76 MHz （East Europe） 00 1:0 SPACE[1:0] Channel Spacing. 00 = 100 kHz 01 = 200 kHz 10 = 50kHz 00 04H 14 STCIEN Seek/Tune Complete Interrupt Enable. 0 = Disable Interrupt 1 = Enable Interrupt Setting STCIEN = 1 will generate a low pulse on GPIO2 when the interrupt occurs. 0 11 9 8 DE SOFTMUTE_EN AFCD De-emphasis. 0 = 75 µs; 1 = 50 µs If 1, softmute enable AFC disable. If 0, afc work; If 1, afc disabled. 0 1 0 6 I2S_ENABLED I2S bus enable If 0, disabled; If 1, enabled. 0 5:4 GPIO3[1:0] General Purpose I/O 3. 00 = High impedance 01 = Mono/Stereo indicator (ST) 10 = Low 00 The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA. Page 10 of 26

RDA Microelectronics, Inc. RDA5802E FM Tuner V1.6

REG BITS 3:2 NAME 11 = High GPIO2[1:0] FUNCTION General Purpose I/O 2. 00 = High impedance 01 = Interrupt (INT) 10 = Low 11 = High DEFAULT 00 1:0 GPIO1[1:0] General Purpose I/O 1. 00 = High impedance 01 = Reserved 10 = Low 11 = High 00 05H 15 INT _MODE If 0, generate 5ms interrupt; If 1, interrupt last until read reg0CH action occurs. 1 14:8 7:6 SEEKTH[6:0] LNA_PORT_SEL[1:0] Seek Threshold. RSSI scale is logarithmic. 0000000 = min RSSI LNA input port selection bit: 00: no input 01: LNAN 10: LNAP 11: dual port input 0001000 10 5:4 LNA_ICSEL_BIT[1:0] Lna working current bit: 00=1.8mA 01=2.1mA 10=2.5mA 11=3.0mA 10 3:0 VOLUME[3:0] DAC Gain Control Bits (Volume). 0000=min; 1111=max Volume scale is logarithmic 1111 06H 12 I2s_mode_select If 0, master mode; If 1, slave mode. 0 0000 7:4 I2s_ws_cnt[4:0] Only valid in master mode 4'b1000: WS_STEP_48; 4'b0111: WS_STEP=44.1kbps; 4'b0110: WS_STEP=32kbps; 4'b0101: WS_STEP=24kbps; 4'b0100: WS_STEP=22.05kbps; 4'b0011: WS_STEP=16kbps; 4'b0010: WS_STEP=12kbps; 4'b0001: WS_STEP=11.025kbps; 4'b0000: WS_STEP=8kbps; 0AH 14 STC Seek/Tune Complete. 0 = Not complete 1 = Complete The seek/tune complete flag is set when the seek or tune operation completes. 0 13 SF Seek Fail. 0 = Seek successful; 1 = Seek failure The seek fail flag is set when the seek operation 0 The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA. Page 11 of 26

RDA Microelectronics, Inc. RDA5802E FM Tuner V1.6

REG BITS NAME FUNCTION fails to find a channel with an RSSI level greater than SEEKTH[5:0]. DEFAULT 10 ST Stereo Indicator. 0 = Mono; 1 = Stereo Stereo indication is available on GPIO3 by setting GPIO1[1:0] =01. 1 9:0 READCHAN[9:0] Read Channel. BAND = 0 Frequency = Channel Spacing (kHz) x READCHAN[9:0]+ 87.0 MHz BAND = 1 or 2 Frequency = Channel Spacing (kHz) x READCHAN[9:0]+ 76.0 MHz BAND = 3 Frequency = Channel Spacing (kHz) x READCHAN[9:0]+ 65.0 MHz READCHAN[9:0] is updated after a tune or seek operation. 8’h00 0BH 15:9 RSSI[6:0] RSSI. 000000 = min 111111 = max RSSI scale is logarithmic. 0 8 FM TRUE 1 = the current channel is a station 0 = the current channel is not a station 0 0 7 FM_READY 1=ready 0=not ready The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA. Page 12 of 26

RDA Microelectronics, Inc. RDA5802E FM Tuner V1.6

8 Pins Description

GPIO1GPIO2202423222119181716151413GPIO3GNDNCNCGNDLNANRFGNDLNAPGNDGND1234567101112AVDDGNDLOUTROUTGNDDVDDGNDPADRDA5802EMODESCLKSDIOSEN Figure 8-1. RDA5802E Top View Table 8-1 RDA5802E Pins Description PIN DESCRIPTION SYMBOL GND LNAN,LNAP RFGND MODE SEN SCLK SDIO RCLK VIO AVDD ROUT,LOUT DVDD GPIO1,GPIO2,GPIO3 NC 1,5,6,14,17,24 Ground. Connect to ground plane on PCB LNA input port. For single-ended input, LNAN should 2,4 be connected to RFGND 3 LNA ground. Connect to ground plane on PCB Control Interface select The MODE Pin is low ,I2C Interface is select. 7 The MODE Pin is set to VIO, SPI Interface is select. 8 9 10 11 12 18 15,16 13 19,20,21 22,23 Latch enable (active low) input for serial control bus Clock input for serial control bus Data input/output for serial control bus 32.768KHz crystal oscillator and reference clock input Power supply for I/O Power supply for analog section Right/Left audio output Power supply for digital section General purpose input/output No Connect The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA. Page 13 of 26

RCLKVIORDA Microelectronics, Inc. RDA5802E FM Tuner V1.6

Table 8-2 12345678GPIO1GNDGNDFMIN GNDGNDSCLKSDAGPIO2GPIO3GND161514131211109RDA5802ESOP16ROUTLOUTGNDVDDRCLKFigure 8-2. SOP16 Top View RDA5802E SOP16 Pins Description PIN DESCRIPTION SYMBOL GND FM_IN RCLK VDD LOUT,ROUT SCLK SDIO GPIO1,GPIO2,GPIO3

2,3,5,6,11,14 4 9 10 12,13 7 8 1,16,15 Ground. Connect to ground plane on PCB FM single input 32.768KHz reference clock input Power supply Right/Left audio output Clock input for serial control bus Data input/output for serial control bus General purpose input/output The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA. Page 14 of 26

RDA Microelectronics, Inc. RDA5802E FM Tuner V1.6

Table 8-3 Internal Pin Configuration

PIN DESCRIPTION SYMBOL LNAN/LNAP 2/4 RCLK 11 47KSDIO\\SCLKSinSCLK/SDIO 9/10 SoutMN1 GPIO1/GPIO2/GPIO3 19/20/21

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RDA Microelectronics, Inc. RDA5802E FM Tuner V1.6

9 Application Diagram

9.1

Audio Loading Resistance Larger than 32Ω & TCXO Application:

Notes: 1. J1: Common 32Ω Resistance Headphone; 2. U1: RDA5802E Chip; 3. V1: Analog and Digital Power 19GNDGPIO1GPIO2GPIO3Supply (1.8~5.5V); 4. FM Choke (L3 and C3) for Audio Common and LNA Input Common; 5. Pins NC(22, 23), Should be Leaved Floating; 6.Set MODE to select control NCMODESCLKNCRCLKSDIOSENVIOinterface(GND—I2C,VIO—SPI); 6. Place C6 Close to AVDD pin.

7 Figure 9-1. RDA5802E FM Tuner Application Diagram (TCXO Application)

9.1.1 Bill of Materials: VALUE

DESCRIPTION

SUPPLIER

COMPONENT

U1 J1 C2 L3/C3 C4,C5 C6 F1/F2

RDA5802E 100pF 100nH/24pF 125µF 24nF

1.5K@100MHz

Broadcast FM Radio Tuner

Common 32Ω Resistance Headphone Couple CAP

LC Chock for LNA Input Audio AC Couple Capacitors Power Supply Bypass Capacitor FM Band Ferrite

RDA Murata Murata Murata Murata Murata

The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA. Page 16 of 26

RDA Microelectronics, Inc. RDA5802E FM Tuner V1.6 9.2

Audio Loading Resistance Lower than 32Ω & DCXO Application:

F1 1.5K@100MHzC4 125uFNotes: 1. J1: Common 32Ω Resistance F2 1.5K@100MHzJ1L3 100nHC5 125uFHeadphone 2. U1: RDA5802E Chip 3. V1: Analog and Digital Power Supply (1.8~5.5V) 5. Pins NC(22, 23),Should be Leaved Floating; 6.Set MODE to select control C6 24nFC3 24pF1GNDLNANRFGNDLNAPGNDGNDAVDDGNDV1U1RDA 5802ELOUTROUTGNDDVDDinterface(GND—I2C,VIO—SPI); 7. Place C6 Close to AVDD pin 13SCLKSDIO32.768KVIO Figure 9-2. RDA5802E FM Tuner Application Diagram (32.768K crystal,I2C bus mode) 9.2.1 Bill of Materials: VALUE DESCRIPTION SUPPLIER COMPONENT U1 J1 C4/C5 L3/C3 C6 F1/F2

RDA5802E 125uF 100nH/24pF 24nF 1.5K@100MHz Broadcast FM Radio Tuner Audio Amplifier Audio AC Couple Capacitors LC Chock for LNA Input Power Supply Bypass Capacitor FM Band Ferrite

RDA Murata Murata Murata Murata The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA. Page 17 of 26

RDA Microelectronics, Inc. RDA5802E FM Tuner V1.6 9.3

Audio Loading Resistance Lower than 32Ω & SOP16 Application:

Figure 9-3. RDA5802E SOP16 FM Tuner Application Diagram

9.3.1 Bill of Materials: VALUE

DESCRIPTION

SUPPLIER

COMPONENT

U1 J1 L1/C2 C4,C5 C1 F1/F2

RDA5802E SOP16

100nH/24pF 125µF 24nF

1.5K@100MHz

Broadcast FM Radio Tuner

Common 32Ω Resistance Headphone LC Chock for LNA Input Audio AC Couple Capacitors Power Supply Bypass Capacitor FM Band Ferrite

RDA Murata Murata Murata Murata

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RDA Microelectronics, Inc. RDA5802E FM Tuner V1.6

10 Package Physical Dimension

Figure 10-1 illustrates the package details for the RDA5802E. The package is lead-free and RoHS-compliant.

D □E □D2 MIN NOM 4.00 BSC 4.00 BSC MAX 2.60 2.60 0.30 0.18 0.80 0.00 2.70 2.70 0.50 BSC 0.40 0.25 0.90 0.02 0.20 ref 2.80 2.80 0.50 0.30 1.00 0.05 E2 e □L b A A1 A3

Figure 10-1. 24-Pin 4x4 Quad Flat No-Lead (QFN)

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RDA Microelectronics, Inc. RDA5802E FM Tuner V1.6

Symbol Dimensions In Millimeters Min A A1 A2 b c D E E1 e Θ L 1 0.400 。Dimensions In Inches Min 0.053 0.004 0.053 0.013 0.007 0.386 0.150 0.228 0.050(BSC) Max 0.069 0.010 0.061 0.020 0.010 0.402 0.157 0.244 Max 1.750 0.250 1.550 0.510 0.250 10.200 4.000 6.200 1.270(BSC) 7 1.270 。1.350 0.100 1.350 0.330 0.170 9.800 3.800 5.800 1 0.016 。7 0.050 。

Figure 10-2. 16 PIN SOP

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RDA Microelectronics, Inc. RDA5802E FM Tuner V1.6

11 PCB Land Pattern

Figure 18.Classification Reflow Profile Profile Feature Average Ramp-Up Rate (TSmax to Tp) Preheat -Temperature Min (Tsmin) -Temperature Max (Tsmax) -Time (tsmin to tsmax) Time maintained above: -Temperature (TL) -Time (tL) Peak /Classification Temperature(Tp) Time within 5 oC of actual Peak Temperature (tp) Ramp-Down Rate Sn-Pb Eutectic Assembly 3 oC/second max. Pb-Free Assembly 3 oC/second max. 100 oC 100 oC 60-120 seconds 183 oC 60-150seconds See Table-II 10-30 seconds 6 oC/second max. 150 oC 200 oC 60-180 seconds 217oC 60-150 seconds See Table-III 20-40 seconds 6 oC/seconds max. The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA. Page 21 of 26

RDA Microelectronics, Inc. RDA5802E FM Tuner V1.6

Time 25 oC to Peak Temperature

6 minutes max.

Table-I Classification Reflow Profiles

Volume mm3

<350

240 + 0/-5 o C 225 + 0/-5 o C

8 minutes max.

Package Thickness

Volume mm3

≥350 225 + 0/-5 o C 225 + 0/-5 o C

＜2.5mm ≥2.5mm

Table – II SnPb Eutectic Process – Package Peak Reflow Temperatures

Package Thickness ＜1.6mm 1.6mm – 2.5mm ≥2.5mm Volume mm3 ＜350 260 + 0 o C * 260 + 0 o C * 250 + 0 o C * Volume mm3 350-2000 260 + 0 o C * 250 + 0 o C * 245 + 0 o C * Volume mm3 ＞2000 260 + 0 o C * 245 + 0 o C * 245 + 0 o C * *Tolerance : The device manufacturer/supplier shall assure process compatibility up to and including the stated classification temperature(this mean Peak reflow temperature + 0 o C. For example 260+ 0 o C ) at the rated MSL Level. Table – III Pb-free Process – Package Classification Reflow Temperatures Note 1: All temperature refer topside of the package. Measured on the package body surface. Note 2: The profiling tolerance is + 0 capability)whatever o C, - X o C (based on machine variation is required to control the profile process but at no time will it exceed - 5 o C. The producer assures process compatibility at the peak reflow profile temperatures defined in Table –III. Note 3: Package volume excludes external terminals(balls, bumps, lands, leads) and/or non

integral heat sinks. Note 4: The maximum component temperature reached during reflow depends on package the

thickness and volume. The use of convection reflow processes reduces the thermal gradients between packages. However, thermal gradients due to differences in thermal mass of SMD package may sill exist. Note 5: Components intended for use in a “lead-free” assembly process shall be evaluated

using the “lead free” classification temperatures and profiles defined in Table-I II III whether or not lead free.

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RDA Microelectronics, Inc. RDA5802E FM Tuner V1.6

RoHS Compliant

The product does not contain lead, mercury, cadmium, hexavalent chromium, polybrominated biphenyls (PBB) or polybrominated diphenyl ethers (PBDE), and are therefore considered RoHS compliant.

ESD Sensitivity

Integrated circuits are ESD sensitive and can be damaged by static electricity. Proper ESD

techniques should be used when handling these devices.

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RDA Microelectronics, Inc. RDA5802E FM Tuner V1.6

12 Change List

REV

DATE

AUTHER

CHANGE DESCRIPTION

V1.0 V1.5 V1.6

2009-03-03 2009-03-03 2009-06-03

ChunZhao

ChunZhao,XiaoQiYou ChunZhao,XiaoQiYou

Original Draft.

Add TSSOP 16 Package Add SOP 16 Package

13 Notes：

1: 通过硬件电路设置芯片工作总线控制模式，详细电路如下图：

VIO 77MODEMODE 88SENSENSEN 99SCLKSCLKSCLKSCLK10 10SDIOSDIOSDIOSDIO 附图：I2C总线电路接口电路 SPI 总线电路接口电路

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RDA Microelectronics, Inc. RDA5802E FM Tuner V1.6

14 RDA5802E与RDA5802对比

1、5802E的0x0Ch＝5803、0x0Dh＝5804，可以通过读这两个寄存器的缺省值来区别5800、5802和5802E;

2、FM天线尽量用第4脚（LNAP），不要用第2脚（LNAN）。5802E的这两个输入脚电路结构是不一样的，性能有差别；

3、需要给客户说明5802E的I2C地址有三个：0010000；0010001；1100000（测试模式）

4、RCLK脚接32.768K晶体的时候，要注意尽量减小寄生电容，PCB走线不能太长；否则容易造成32.768K晶体不起振现象。

5、LNAN & LANP 管脚电路做了修改，直流电平必须为0；如果客户天线的直流电平不为0（比如瑞芯微的MP3芯片），则需要加100pF电容隔直。 5802E 5802 5000V 2000V ESD（静电） I2C缺省电平 不需要sclk触发 需要sclk下降沿触发 音量大小 大（250mV） 一般（200mV） 2.7~5.5V 工作电压范围 1.8～5.5V (1.8~2V性能略有下降) 57dB dB 信噪比（SNR） -109dBm -107dBm 灵敏度（SEN） 21.5mA 20mA 工作电流 RDS 无 无 多参考时钟 可以任意设置参考时钟（需改寄存器） 普通 I2C口抗毛刺 有提高 一般 硬件兼容性 普通情况下，全兼容5802 软件兼容性 普通情况下，全兼容5802 32K时钟输入性 对32K时钟电平特性要求小。如果输入时钟如果32K时钟信号幅度过小信号幅度或者占空比小，可将0x02h寄存器或者占空比过小，会导致时bit<10>设置成1，这样参考时钟为直接输入模钟信号输入困难 式，保证可靠性

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RDA Microelectronics, Inc. RDA5802E FM Tuner V1.6

15 Contact Information

RDA Microelectronics (Shanghai), Inc.

Suite 1108 Block A, e-Wing Center, 113 Zhichun Road Haidian District, Beijing Tel: 86-10-62635360 Fax: 86-10-82612663 Postal Code: 100086

Suite 302 Building 2, 690 Bibo Road Pudong District, Shanghai Tel: 86-21-50271108 Fax: 86-21-50271099 Postal Code: 201203

Copyright © RDA Microelectronics Inc. 2006. All rights are reserved.

Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

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