Am29LV004B

Data Sheet

July 2003

The following document specifies Spansion memory products that are now offered by both AdvancedMicro Devices and Fujitsu. Although the document is marked with the name of the company that orig-inally developed the specification, these products will be offered to customers of both AMD andFujitsu.

Continuity of Specifications

There is no change to this datasheet as a result of offering the device as a Spansion product. Anychanges that have been made are the result of normal datasheet improvement and are noted in thedocument revision summary, where supported. Future routine revisions will occur when appropriate,and changes will be noted in a revision summary.

Continuity of Ordering Part Numbers

AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To orderthese products, please use only the Ordering Part Numbers listed in this document.

For More Information

Please contact your local AMD or Fujitsu sales office for additional information about Spansionmemory solutions.

Publication Number 21522 Revision DAmendment +1 Issue Date November 13, 2000

Am29LV004B

4 Megabit (512 K x 8-Bit)

CMOS 3.0 Volt-only Boot Sector Flash Memory

DISTINCTIVE CHARACTERISTICS

sSingle power supply operation

—2.7 to 3.6 volt read and write operations for battery-powered applicationssManufactured on 0.32 µm process technology—Compatible with 0.5 µm Am29LV004 devicesHigh performance

—Access times as fast as 70 ns

sUltra low power consumption (typical values at 5 MHz)—200 nA Automatic Sleep mode current—200 nA standby mode current—7 mA read current

—15 mA program/erase currentsFlexible sector architecture

—One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and seven Kbyte sectors—Supports full chip erase—Sector Protection features:

A hardware method of locking a sector to

prevent any program or erase operations within that sector

Sectors can be locked in-system or via programming equipment

Temporary Sector Unprotect feature allows code changes in previously locked sectorssUnlock Bypass Program Command

—Reduces overall programming time when

issuing multiple program command sequences

sTop or bottom boot block configurations availablesEmbedded Algorithms

—Embedded Erase algorithm automatically

preprograms and erases the entire chip or any combination of designated sectors—Embedded Program algorithm automatically writes and verifies data at specified addressessMinimum 1,000,000 write cycle guarantee per sectors20-year data retention at 125°C

—Reliable operation for the life of the systemsPackage option—40-pin TSOP

sCompatibility with JEDEC standards—Pinout and software compatible with single-power supply Flash—Superior inadvertent write protectionsData# Polling and toggle bits

—Provides a software method of detecting program or erase operation completionsReady/Busy# pin (RY/BY#)

—Provides a hardware method of detecting program or erase cycle completionsErase Suspend/Erase Resume

—Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operationsHardware reset pin (RESET#)

—Hardware method to reset the device to reading array data

This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This DataSheet may be revised by subsequent versions or modifications due to changes in technical specifications.

Publication# 21522Rev: DAmendment/+1Issue Date: November 13, 2000

GENERAL DESCRIPTION

The Am29LV004B is an 4 Mbit, 3.0 volt-only Flashmemory organized as 524,288 bytes. The device isoffered in a 40-pin TSOP package. The byte-wide (x8)data appears on DQ7–DQ0. This device requires onlya single, 3.0 volt VCC supply to perform read, program,and erase operations. A standard EPROM programmercan also be used to program and erase the device. This device is manufactured using AMD’s 0.32 µmprocess technology, and offers all the features and ben-efits of the Am29LV004, which was manufactured using0.5 µm process technology. In addition, theAm29LV004B features unlock bypass programmingand in-system sector protection/unprotection.

The standard device offers access times of 70, 90, and120 ns, allowing high speed microprocessors tooperate without wait states. To eliminate bus contentionthe device has separate chip enable (CE#), writeenable (WE#) and output enable (OE#) controls.The device requires only a single 3.0 volt powersupply for both read and write functions. Internallygenerated and regulated voltages are provided for theprogram and erase operations.

The device is entirely command set compatible with theJEDEC single-power-supply Flash standard. Com-mands are written to the command register usingstandard microprocessor write timings. Register con-tents serve as input to an internal state-machine thatcontrols the erase and programming circuitry. Writecycles also internally latch addresses and data neededfor the programming and erase operations. Readingdata out of the device is similar to reading from otherFlash or EPROM devices.

Device programming occurs by executing the programcommand sequence. This initiates the EmbeddedProgram algorithm—an internal algorithm that auto-matically times the program pulse widths and verifiesproper cell margin. The Unlock Bypass mode facili-tates faster programming times by requiring only twowrite cycles to program data instead of four.

Device erasure occurs by executing the erasecommand sequence. This initiates the Embedded Erasealgorithm—an internal algorithm that automaticallypre-programs the array (if it is not already programmed)

before executing the erase operation. During erase, thedevice automatically times the erase pulse widths andverifies proper cell margin.

The host system can detect whether a program orerase operation is complete by observing the RY/BY#pin, or by reading the DQ7 (Data# Polling) and DQ6(toggle) status bits. After a program or erase cycle hasbeen completed, the device is ready to read array dataor accept another command.

The sector erase architecture allows memory sectorsto be erased and reprogrammed without affecting thedata contents of other sectors. The device is fullyerased when shipped from the factory.

Hardware data protection measures include a lowVCC detector that automatically inhibits write opera-tions during power transitions. The hardware sectorprotection feature disables both program and eraseoperations in any combination of the sectors ofmemory. This can be achieved in-system or via pro-gramming equipment.

The Erase Suspend feature enables the user to puterase on hold for any period of time to read data from,or program data to, any sector that is not selected forerasure. True background erase can thus be achieved.The hardware RESET# pin terminates any operationin progress and resets the internal state machine toreading array data. The RESET# pin may be tied to thesystem reset circuitry. A system reset would thus alsoreset the device, enabling the system microprocessorto read the boot-up firmware from the Flash memory.The device offers two power-saving features. Whenaddresses have been stable for a specified amount oftime, the device enters the automatic sleep mode.The system can also place the device into the standbymode. Power consumption is greatly reduced in boththese modes.

AMD’s Flash technology combines years of Flashmemory manufacturing experience to produce thehighest levels of quality, reliability and cost effectiveness.The device electrically erases all bits within a sectorsimultaneously via Fowler-Nordheim tunneling. Thedata is programmed using hot electron injection.

2Am29LV004B

TABLE OF CONTENTS

Product Selector Guide . . . . . . . . . . . . . . . . . . . . .4Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . .5Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . .6Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6Ordering Information . . . . . . . . . . . . . . . . . . . . . . .7Device Bus Operations . . . . . . . . . . . . . . . . . . . . . .8

Table 1. Am29LV004B Device Bus Operations................................ 8Reading Toggle Bits DQ6/DQ2 ...............................................19DQ5: Exceeded Timing Limits ................................................20DQ3: Sector Erase Timer .......................................................20Figure 6. Toggle Bit Algorithm ........................................................20Table 6. Write Operation Status..................................................... 21Absolute Maximum Ratings . . . . . . . . . . . . . . . . 22

Figure 7. Maximum Negative OvershootWaveform ......................22Figure 8. Maximum Positive OvershootWaveform ........................22Requirements for Reading Array Data .....................................8Writing Commands/Command Sequences ..............................8Program and Erase Operation Status ......................................9Standby Mode ..........................................................................9Automatic Sleep Mode .............................................................9RESET#: Hardware Reset Pin .................................................9Output Disable Mode ................................................................9Table 2. Am29LV004BT Top Boot Block Sector Address Table..... 10Table 3. Am29LV004BB Bottom Boot Block Sector Address Table 10Operating Ranges. . . . . . . . . . . . . . . . . . . . . . . . . 22DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 9. ICC1 Current vs. Time (Showing Active and Automatic SleepCurrents) ..............................................................................24Figure 10. Typical ICC1 vs. Frequency ...........................................24Figure 11. Test Setup .....................................................................25Table 7. Test Specifications........................................................... 25Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Key to Switching Waveforms. . . . . . . . . . . . . . . . 25

Figure 12. Input Waveforms and Measurement Levels .................25Autoselect Mode .....................................................................11Table 4. Am29LV004B Autoselect Codes (High Voltage Method).. 11Sector Protection/Unprotection ...............................................11Temporary Sector Unprotect ..................................................11Figure 1. In-System Sector Protect/Unprotect Algorithms...............12Figure 2. Temporary Sector Unprotect Operation ...........................13AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 26Read Operations ....................................................................26Figure 13. Read Operations Timings .............................................26Hardware Reset (RESET#) ....................................................27Figure 14. RESET# Timings ..........................................................27Hardware Data Protection ......................................................13Low VCC Write Inhibit ..............................................................13Write Pulse “Glitch” Protection ...............................................13Logical Inhibit ..........................................................................13Power-Up Write Inhibit ............................................................13Command Definitions . . . . . . . . . . . . . . . . . . . . . 13Reading Array Data ................................................................13Reset Command .....................................................................14Autoselect Command Sequence ............................................14Byte Program Command Sequence .......................................14Unlock Bypass Command Sequence .....................................14Figure 3. Program Operation ..........................................................15Erase/Program Operations .....................................................28Figure 15. Program Operation Timings ..........................................29Figure 16. Chip/Sector Erase Operation Timings ..........................30Figure 17. Data# Polling Timings (During Embedded Algorithms) .31Figure 18. Toggle Bit Timings (During Embedded Algorithms) ......31Figure 19. DQ2 vs. DQ6 .................................................................32Temporary Sector Unprotect ..................................................32Figure 20. Temporary Sector Unprotect Timing Diagram ..............32Figure 21. Sector Protect/Unprotect Timing Diagram ....................33Alternate CE# Controlled Erase/Program Operations ............34Figure 22. Alternate CE# Controlled Write Operation Timings ......35Chip Erase Command Sequence ...........................................15Sector Erase Command Sequence ........................................15Erase Suspend/Erase Resume Commands ...........................16Figure 4. Erase Operation ...............................................................16Command Definitions .............................................................17Table 5. Am29LV004B Command Definitions................................. 17Write Operation Status . . . . . . . . . . . . . . . . . . . . .18DQ7: Data# Polling .................................................................18Figure 5. Data# Polling Algorithm ...................................................18RY/BY#: Ready/Busy# ...........................................................19DQ6: Toggle Bit I ....................................................................19DQ2: Toggle Bit II ...................................................................19Erase and Programming Performance . . . . . . . 36Latchup Characteristics. . . . . . . . . . . . . . . . . . . . 36TSOP and SO Pin Capacitance . . . . . . . . . . . . . . 36Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 36Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 37TS 040—40-Pin Standard TSOP ............................................37TSR040—40-Pin Reverse TSOP ...........................................38Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 39Revision A (January 1998) .....................................................39Revision B (June 1998) ..........................................................39Revision C (January 1999) .....................................................39Revision D (November 18, 1999) ...........................................39Revision D+1 (November 13, 2000) .......................................39Am29LV004B3

PRODUCT SELECTOR GUIDE

Family Part NumberSpeed Options

Max access time, ns (tACC)Max CE# access time, ns (tCE)Max OE# access time, ns (tOE)

-70707030

Am29LV004B

-90909035

-12012012050

Note: See “AC Characteristics” for full specifications.BLOCK DIAGRAM

RY/BY#

VCCVSSRESET#

Sector SwitchesErase VoltageGenerator

Input/OutputBuffersDQ0–DQ7

WE#

StateControlCommandRegister

PGM VoltageGenerator

Chip EnableOutput Enable

Logic

STB

DataLatch

CE#OE#

STB

VCC Detector

Timer

Address LatchY-DecoderY-Gating

X-Decoder

Cell Matrix

A0–A18

4Am29LV004B

CONNECTION DIAGRAMS

A16A15A14A13A12A11A9A8WE#RESET#NCRY/BY#A18A7A6A5A4A3A2A112345671011121314151617181920Standard TSOP4039383736353433323130292827262524232221A17VSSNCNCA10DQ7DQ6DQ5DQ4VCCVCCNCDQ3DQ2DQ1DQ0OE#VSSCE#A0A17VSSNCNCA10DQ7DQ6DQ5DQ4VCCVCCNCDQ3DQ2DQ1DQ0CE#VSSCE#A012345671011121314151617181920Reverse TSOP4039383736353433323130292827262524232221A16A15A14A13A12A11A9A8WE#RESET#NCRY/BY#A18A7A6A5A4A3A2A1Am29LV004B5

PIN CONFIGURATION

A0–A18

=19 addresses

DQ0–DQ7=8 data inputs/outputsCE#OE#WE#RESET#RY/BY#VCC

=Chip enable= Output enable=Write enable

=Hardware reset pin, active low= Ready/Busy# output

=3.0 volt-only single power supply

(see Product Selector Guide for speedoptions and voltage supply tolerances)=Device ground

=Pin not connected internally

LOGIC SYMBOL

19

A0–A18

DQ0–DQ7

8

CE#OE#WE#RESET#

RY/BY#

VSSNC

6Am29LV004B

ORDERING INFORMATIONStandard Products

AMD standard products are available in several packages and operating ranges. The order number (Valid Combi-nation) is formed by a combination of the elements below.

Am29LV004B

T

-70

E

C

TEMPERATURE RANGEC=Commercial (0°C to +70°C)I = Industrial (–40°C to +85°C)E =Extended (–55°C to +125°C)

PACKAGE TYPEE=40-Pin Thin Small Outline Package (TSOP)

Standard Pinout (TS 040)

F=40-Pin Thin Small Outline Package (TSOP)

Reverse Pinout (TSR040)SPEED OPTION

See Product Selector Guide and Valid CombinationsBOOT CODE SECTOR ARCHITECTURET= Top SectorB= Bottom Sector

DEVICE NUMBER/DESCRIPTION

Am29LV004B

4 Megabit (512 K x 8-Bit) CMOS Flash Memory3.0 Volt-only Read, Program and Erase

Valid Combinations

Valid Combinations

AM29LV004BT-70,AM29LV004BB-70AM29LV004BT-90,AM29LV004BB-90AM29LV004BT-120,AM29LV004BB-120

EC, EI, FC, FI

Valid Combinations list configurations planned to be sup-ported in volume for this device. Consult the local AMD salesoffice to confirm availability of specific valid combinations andto check on newly released combinations.

EC, EI, EE, FC, FI, FE

Am29LV004B7

DEVICE BUS OPERATIONS

This section describes the requirements and use of thedevice bus operations, which are initiated through theinternal command register. The command registeritself does not occupy any addressable memory loca-tion. The register is composed of latches that store thecommands, along with the address and data informa-tion needed to execute the command. The contents of

the register serve as inputs to the internal statemachine. The state machine outputs dictate the func-tion of the device. Table 1 lists the device busoperations, the inputs and control levels they require,and the resulting output. The following subsectionsdescribe each of these operations in further detail.

Table 1.

Operation

ReadWriteStandbyOutput DisableReset

Sector Protect (Note 2)Sector Unprotect (Note 2)Temporary Sector Unprotect

CE#LL

Am29LV004B Device Bus Operations

OE#LHXHXHHX

WE#HLXHXLLX

RESET#

HHVCC ± 0.3 V

HLVIDVIDVID

Addresses (Note 1)

AINAINXXX

Sector Address, A6 = L,

A1 = H, A0 = LSector Address, A6 = H,

A1 = H, A0 = L

AIN

DQ0–DQ7DOUTDINHigh-ZHigh-ZHigh-ZDIN, DOUTDIN, DOUT

DIN

VCC ± 0.3 V

LXLLX

Legend:

L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 ± 0.5 V, X = Don’t Care, AIN = Address In, DIN = Data In, DOUT = Data OutNotes:1.Addresses are A18–A0.2.The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector Protection/Unprotection” section.Requirements for Reading Array Data

To read array data from the outputs, the system mustdrive the CE# and OE# pins to VIL. CE# is the powercontrol and selects the device. OE# is the outputcontrol and gates array data to the output pins. WE#should remain at VIH.

The internal state machine is set for reading array dataupon device power-up, or after a hardware reset. Thisensures that no spurious alteration of the memorycontent occurs during the power transition. Nocommand is necessary in this mode to obtain arraydata. Standard microprocessor read cycles that assertvalid addresses on the device address inputs producevalid data on the device data outputs. The deviceremains enabled for read access until the commandregister contents are altered.

See “Reading Array Data” for more information. Referto the AC Read Operations table for timing specifica-tions and to Figure 13 for the timing diagram. ICC1 in theDC Characteristics table represents the active currentspecification for reading array data.

Writing Commands/Command Sequences

To write a command or command sequence (whichincludes programming data to the device and erasingsectors of memory), the system must drive WE# andCE# to VIL, and OE# to VIH.

The device features an Unlock Bypass mode to facili-tate faster programming. Once the device enters theUnlock Bypass mode, only two write cycles arerequired to program a byte, instead of four. The “ByteProgram Command Sequence” section has details onprogramming data to the device using both standardand Unlock Bypass command sequences.

An erase operation can erase one sector, multiple sec-tors, or the entire device. Tables 2 and 3 indicate theaddress space that each sector occupies. A “sectoraddress” consists of the address bits required touniquely select a sector. The “Command Definitions”section has details on erasing a sector or the entirechip, or suspending/resuming the erase operation.After the system writes the autoselect commandsequence, the device enters the autoselect mode. Thesystem can then read autoselect codes from the

8Am29LV004B

internal register (which is separate from the memoryarray) on DQ7–DQ0. Standard read cycle timings applyin this mode. Refer to the Autoselect Mode and Autose-lect Command Sequence sections for moreinformation.

ICC2 in the DC Characteristics table represents theactive current specification for the write mode. The “ACCharacteristics” section contains timing specificationtables and timing diagrams for write operations.

access timings provide new data when addresses arechanged. While in sleep mode, output data is latchedand always available to the system. ICC4 in the DCCharacteristics table represents the automatic sleepmode current specification.

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of reset-ting the device to reading array data. When theRESET# pin is driven low for at least a period of tRP, thedevice immediately terminates any operation inprogress, tristates all output pins, and ignores allread/write commands for the duration of the RESET#pulse. The device also resets the internal statemachine to reading array data. The operation that wasinterrupted should be reinitiated once the device isready to accept another command sequence, toensure data integrity.

Current is reduced for the duration of the RESET#pulse. When RESET# is held at VSS±0.3 V, the devicedraws CMOS standby current (ICC4). If RESET# is heldat VIL but not within VSS±0.3 V, the standby current willbe greater.

The RESET# pin may be tied to the system reset cir-cuitry. A system reset would thus also reset the Flashmemory, enabling the system to read the boot-up firm-ware from the Flash memory.

If RESET# is asserted during a program or erase oper-ation, the RY/BY# pin remains a “0” (busy) until theinternal reset operation is complete, which requires atime of tREADY (during Embedded Algorithms). Thesystem can thus monitor RY/BY# to determine whetherthe reset operation is complete. If RESET# is assertedwhen a program or erase operation is not executing(RY/BY# pin is “1”), the reset operation is completedwithin a time of tREADY (not during Embedded Algo-rithms). The system can read data tRH after theRESET# pin returns to VIH.

Refer to the AC Characteristics tables for RESET#parameters and to Figure 14 for the timing diagram.

Program and Erase Operation Status

During an erase or program operation, the system maycheck the status of the operation by reading the statusbits on DQ7–DQ0. Standard read cycle timings and ICCread specifications apply. Refer to “Write OperationStatus” for more information, and to “AC Characteris-tics” for timing diagrams.

Standby Mode

When the system is not reading or writing to the device,it can place the device in the standby mode. In thismode, current consumption is greatly reduced, and theoutputs are placed in the high impedance state, inde-pendent of the OE# input.

The device enters the CMOS standby mode when theCE# and RESET# pins are both held at VCC ± 0.3 V.(Note that this is a more restricted voltage range thanVIH.) If CE# and RESET# are held at VIH, but not withinVCC ± 0.3 V, the device will be in the standby mode, butthe standby current will be greater. The device requiresstandard access time (tCE) for read access when thedevice is in either of these standby modes, before it isready to read data.

If the device is deselected during erasure or program-ming, the device draws active current until theoperation is completed.

ICC3 in the DC Characteristics table represents thestandby current specification.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash deviceenergy consumption. The device automatically enablesthis mode when addresses remain stable for tACC + 30ns. The automatic sleep mode is independent of theCE#, WE#, and OE# control signals. Standard address

Output Disable Mode

When the OE# input is at VIH, output from the device isdisabled. The output pins are placed in the high imped-ance state.

Am29LV004B9

Table 2.

SectorSA0SA1SA2SA3SA4SA5SA6SA7SA8SA9SA10

A1800001111111

A1700110011111

Am29LV004BT Top Boot Block Sector Address Table

A1601010101111

A15XXXXXXX0111

A14XXXXXXXX001

A13XXXXXXXX01X

Sector Size(Kbytes)

328816

Address Range(in hexadecimal)00000h-0FFFFh10000h-1FFFFh20000h-2FFFFh30000h-3FFFFh40000h-4FFFFh50000h-5FFFFh60000h-6FFFFh70000h-77FFFh78000h-79FFFh7A000h-7BFFFh7C000h-7FFFFh

Table 3.

SectorSA0SA1SA2SA3SA4SA5SA6SA7SA8SA9SA10

A1800000001111

A1700000110011

Am29LV004BB Bottom Boot Block Sector Address Table

A1600001010101

A150001XXXXXXX

A14011XXXXXXXX

A13X01XXXXXXXX

Sector Size(Kbytes)

Address Range(in hexadecimal)

16 00000h-03FFFh8 04000h-05FFFh8 06000h-07FFFh32 08000h-0FFFFh 10000h-1FFFFh 20000h-2FFFFh 30000h-3FFFFh 40000h-4FFFFh 50000h-5FFFFh 60000h-6FFFFh 70000h-7FFFFh10Am29LV004B

Autoselect Mode

The autoselect mode provides manufacturer anddevice identification, and sector protection verification,through identifier codes output on DQ7–DQ0. Thismode is primarily intended for programming equipmentto automatically match a device to be programmed withits corresponding programming algorithm. However,the autoselect codes can also be accessed in-systemthrough the command register.

When using programming equipment, the autoselectmode requires VID (11.5 V to 12.5 V) on address pinA9. Address pins A6, A1, and A0 must be as shown in

Table 4. In addition, when verifying sector protection,the sector address must appear on the appropriatehighest order address bits (see Tables 2 and 3). Table4 shows the remaining address bits that are don’t care.When all necessary bits have been set as required, theprogramming equipment may then read the corre-sponding identifier code on DQ7–DQ0.

To access the autoselect codes in-system, the hostsystem can issue the autoselect command via thecommand register, as shown in Table 5. This methoddoes not require VID. See “Command Definitions” fordetails on using the autoselect mode.

Table 4.Am29LV004B Autoselect Codes (High Voltage Method)

A18 A12 to toA13A10XXX

XXX

A8toA7XXX

A5toA2XXX

DQ7toDQ001hB5hB6h01h (protected)00h (unprotected)

Description

Manufacturer ID: AMDDevice ID: Am29LV004BT(Top Boot Block)

Device ID: Am29LV004BB(Bottom Boot Block)

CE#LLL

OE#LLL

WE#HHH

A9VIDVIDVID

A6LLL

A1LLL

A0LHH

Sector Protection VerificationLLHSAX

VID

XLXHL

L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.Sector Protection/Unprotection

The hardware sector protection feature disables bothprogram and erase operations in any sector. The hard-ware sector unprotection feature re-enables bothprogram and erase operations in previously protectedsectors. Sector protection/unprotection can be imple-mented via two methods.

The primary method requires VID on the RESET# pinonly, and can be implemented either in-system or viaprogramming equipment. Figure 1 shows the algo-rithms and Figure 21 shows the timing diagram. Thismethod uses standard microprocessor bus cycletiming. For sector unprotect, all unprotected sectorsmust first be protected prior to the first sector unprotectwrite cycle.

The alternate method intended only for programmingequipment requires VID on address pin A9, OE#, andRESET#. This method is compatible with programmerroutines written for earlier 3.0 volt-only AMD flashdevices. Publication number 20874 contains further

details; contact an AMD representative to request acopy.

The device is shipped with all sectors unprotected.AMD offers the option of programming and protectingsectors at its factory prior to shipping the devicethrough AMD’s ExpressFlash™ Service. Contact anAMD representative for details.

It is possible to determine whether a sector is protectedor unprotected. See “Autoselect Mode” for details.

Temporary Sector Unprotect

This feature allows temporary unprotection of previ-ously protected sectors to change data in-system. TheSector Unprotect mode is activated by setting theRESET# pin to VID. During this mode, formerly pro-tected sectors can be programmed or erased byselecting the sector addresses. Once VID is removedfrom the RESET# pin, all the previously protectedsectors are protectedagain. Figure 2 shows the algo-rithm, and Figure 20 shows the timing diagrams, for thisfeature.

Am29LV004B11

STARTPLSCNT = 1RESET# = VIDWait 1 µsProtect all sectors:The indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect addressSTARTPLSCNT = 1RESET# = VIDWait 1 µsTemporary SectorUnprotect ModeNoFirst Write Cycle = 60h?YesSet up sectoraddressSector Protect:Write 60h to sectoraddress withA6 = 0, A1 = 1, A0 = 0Wait 150 µsVerify Sector Protect: Write 40h to sector addresswith A6 = 0, A1 = 1, A0 = 0Read from sector addresswith A6 = 0, A1 = 1, A0 = 0NoFirst Write NoCycle = 60h?YesAll sectorsprotected?YesSet up first sectoraddressSector Unprotect:Write 60h to sectoraddress withA6 = 1, A1 = 1, A0 = 0Temporary SectorUnprotect ModeIncrementPLSCNTResetPLSCNT = 1Wait 15 msVerify Sector Unprotect: Write 40h to sector address with A6 = 1, A1 = 1, A0 = 0Read from sector addresswith A6 = 1, A1 = 1, A0 = 0Set upnext sectoraddressNoNoPLSCNT= 25?YesData = 01h?YesYesDevice failedProtect anothersector?NoRemove VID from RESET#Write reset commandIncrementPLSCNTNoNoPLSCNT= 1000?YesData = 00h?YesDevice failedLast sectorverified?YesNoSector ProtectAlgorithmSector ProtectcompleteSector UnprotectAlgorithmRemove VID from RESET#Write reset commandSector UnprotectcompleteFigure 1.In-System Sector Protect/Unprotect Algorithms12Am29LV004B

START

RESET# = VID

(Note 1)Perform Erase orProgram Operations

command definitions). In addition, the following hard-ware data protection measures prevent accidentalerasure or programming, which might otherwise becaused by spurious system level signals during VCCpower-up and power-down transitions, or from systemnoise.

Low VCC Write Inhibit

When VCC is less than VLKO, the device does notaccept any write cycles. This protects data during VCCpower-up and power-down. The command register andall internal program/erase circuits are disabled, and thedevice resets. Subsequent writes are ignored until VCCis greater than VLKO. The system must provide theproper signals to the control pins to prevent uninten-tional writes when VCC is greater than VLKO.Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE# orWE# do not initiate a write cycle.Logical Inhibit

RESET# = VIH

Temporary SectorUnprotect Completed

(Note 2)

Notes:1.All protected sectors unprotected.2.All previously protected sectors are protected once again.Write cycles are inhibited by holding any one of OE# =VIL, CE# = VIH or WE# = VIH. To initiate a write cycle,CE# and WE# must be a logical zero while OE# is alogical one.

Power-Up Write Inhibit

If WE# = CE# = VIL and OE# = VIH during power up, thedevice does not accept commands on the rising edgeof WE#. The internal state machine is automaticallyreset to reading array data on power-up.

Figure 2.Temporary Sector Unprotect Operation

Hardware Data Protection

The command sequence requirement of unlock cyclesfor programming or erasing provides data protectionagainst inadvertent writes (refer to Table 5 for

COMMAND DEFINITIONS

Writing specific address and data commands orsequences into the command register initiates deviceoperations. Table 5 defines the valid register commandsequences. Writing incorrect address and datavalues or writing them in the improper sequenceresets the device to reading array data.

All addresses are latched on the falling edge of WE# orCE#, whichever happens later. All data is latched onthe rising edge of WE# or CE#, whichever happensfirst. Refer to the appropriate timing diagrams in the“AC Characteristics” section.

After the device accepts an Erase Suspend command,the device enters the Erase Suspend mode. Thesystem can read array data using the standard readtimings, except that if it reads at an address withinerase-suspended sectors, the device outputs statusdata. After completing a programming operation in theErase Suspend mode, the system may once againread array data with the same exception. See “EraseSuspend/Erase Resume Commands” for more infor-mation on this mode.

The system must issue the reset command to re-enable the device for reading array data if DQ5 goeshigh, or while in the autoselect mode. See the “ResetCommand” section, next.

See also “Requirements for Reading Array Data” in the“Device Bus Operations” section for more information.The Read Operations table provides the read parame-ters, and Figure 13 shows the timing diagram.

Reading Array Data

The device is automatically set to reading array dataafter device power-up. No commands are required toretrieve data. The device is also ready to read arraydata after completing an Embedded Program orEmbedded Erase algorithm.

Am29LV004B13

Reset Command

Writing the reset command to the device resets thedevice to reading array data. Address bits are don’tcare for this command.

The reset command may be written between thesequence cycles in an erase command sequencebefore erasing begins. This resets the device to readingarray data. Once erasure begins, however, the deviceignores reset commands until the operation iscomplete.

The reset command may be written between thesequence cycles in a program command sequencebefore programming begins. This resets the device toreading array data (also applies to programming inErase Suspend mode). Once programming begins,however, the device ignores reset commands until theoperation is complete.

The reset command may be written between thesequence cycles in an autoselect command sequence.Once in the autoselect mode, the reset command mustbe written to return to reading array data (also appliesto autoselect during Erase Suspend).

If DQ5 goes high during a program or erase operation,writing the reset command returns the device toreading array data (also applies during EraseSuspend).

program set-up command. The program address anddata are written next, which in turn initiate theEmbedded Program algorithm. The system is notrequired to provide further controls or timings. Thedevice automatically provides internally generatedprogram pulses and verify the programmed cell margin.Table 5 shows the address and data requirements forthe byte program command sequence.

When the Embedded Program algorithm is complete,the device then returns to reading array data andaddresses are no longer latched. The system candetermine the status of the program operation by usingDQ7, DQ6, or RY/BY#. See “Write Operation Status”for information on these status bits.

Any commands written to the device during theEmbedded Program Algorithm are ignored. Note that ahardware reset immediately terminates the program-ming operation. The Byte Program commandsequence should be reinitiated once the device hasreset to reading array data, to ensure data integrity.Programming is allowed in any sequence and acrosssector boundaries. A bit cannot be programmedfrom a “0” back to a “1”. Attempting to do so may haltthe operation and set DQ5 to “1”, or cause the Data#Polling algorithm to indicate the operation was suc-cessful. However, a succeeding read will show that thedata is still “0”. Only erase operations can convert a “0”to a “1”.

Unlock Bypass Command Sequence

The unlock bypass feature allows the system toprogram bytes to the device faster than using the stan-dard program command sequence. The unlock bypasscommand sequence is initiated by first writing twounlock cycles. This is followed by a third write cyclecontaining the unlock bypass command, 20h. Thedevice then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is allthat is required to program in this mode. The first cyclein this sequence contains the unlock bypass programcommand, A0h; the second cycle contains the programaddress and data. Additional data is programmed inthe same manner. This mode dispenses with the initialtwo unlock cycles required in the standard programcommand sequence, resulting in faster total program-ming time. Table 5 shows the requirements for thecommand sequence.

During the unlock bypass mode, only the UnlockBypass Program and Unlock Bypass Reset commandsare valid. To exit the unlock bypass mode, the systemmust issue the two-cycle unlock bypass resetcommand sequence. The first cycle must contain thedata 90h; the second cycle the data 00h. The devicethen returns to reading array data.

Figure 3 illustrates the algorithm for the program oper-ation. See the Erase/Program Operations table in “AC

Autoselect Command Sequence

The autoselect command sequence allows the hostsystem to access the manufacturer and devices codes,and determine whether or not a sector is protected.Table 5 shows the address and data requirements. Thismethod is an alternative to that shown in Table 4, whichis intended for PROM programmers and requires VIDon address bit A9.

The autoselect command sequence is initiated bywriting two unlock cycles, followed by the autoselectcommand. The device then enters the autoselectmode, and the system may read at any address anynumber of times, without initiating another commandsequence. A read cycle at address 00h retrieves themanufacturer code. A read cycle at address 01hreturns the device code. A read cycle containing asector address (SA) and the address 02h returns 01h ifthat sector is protected, or 00h if it is unprotected. Referto Tables 2 and 3 for valid sector addresses.

The system must write the reset command to exit theautoselect mode and return to reading array data.

Byte Program Command Sequence

The byte program command sequence programs onebyte into the device. Programming is a four-bus-cycleoperation. The program command sequence is initi-ated by writing two unlock write cycles, followed by the14

Am29LV004B

Characteristics” for parameters, and to Figure 15 fortiming diagrams.

command sequence should be reinitiated once thedevice has returned to reading array data, to ensuredata integrity.

The system can determine the status of the erase oper-ation by using DQ7, DQ6, DQ2, or RY/BY#. See “WriteOperation Status” for information on these status bits.When the Embedded Erase algorithm is complete, thedevice returns to reading array data and addresses areno longer latched.

Figure 4 illustrates the algorithm for the erase opera-tion. See the Erase/Program Operations tables in “ACCharacteristics” for parameters, and to Figure 16 fortiming diagrams.

STARTWrite ProgramCommand SequenceEmbeddedProgramalgorithm in progressData Poll from SystemSector Erase Command Sequence

Sector erase is a six bus cycle operation. The sectorerase command sequence is initiated by writing twounlock cycles, followed by a set-up command. Twoadditional unlock write cycles are then followed by theaddress of the sector to be erased, and the sectorerase command. Table 5 shows the address and datarequirements for the sector erase command sequence.The device does not require the system to preprogramthe memory prior to erase. The Embedded Erase algo-rithm automatically programs and verifies the sector foran all zero data pattern prior to electrical erase. Thesystem is not required to provide any controls ortimings during these operations.

After the command sequence is written, a sector erasetime-out of 50 µs begins. During the time-out period,additional sector addresses and sector erase com-mands may be written. Loading the sector erase buffermay be done in any sequence, and the number ofsectors may be from one sector to all sectors. The timebetween these additional cycles must be less than 50µs, otherwise the last address and command might notbe accepted, and erasure may begin. It is recom-mended that processor interrupts be disabled duringthis time to ensure all commands are accepted. Theinterrupts can be re-enabled after the last Sector Erasecommand is written. If the time between additionalsector erase commands can be assumed to be lessthan 50 µs, the system need not monitor DQ3. Anycommand other than Sector Erase or EraseSuspend during the time-out period resets thedevice to reading array data. The system mustrewrite the command sequence and any additionalsector addresses and commands.

The system can monitor DQ3 to determine if the sectorerase timer has timed out. (See the “DQ3: Sector EraseTimer” section.) The time-out begins from the risingedge of the final WE# pulse in the command sequence.Once the sector erase operation has begun, only theErase Suspend command is valid. All other commandsare ignored. Note that a hardware reset during the

15

Verify Data?NoYesNoIncrement AddressLast Address?YesProgramming CompletedNote: See Table 5 for program command sequence.Figure 3.Program Operation

Chip Erase Command Sequence

Chip erase is a six bus cycle operation. The chip erasecommand sequence is initiated by writing two unlockcycles, followed by a set-up command. Two additionalunlock write cycles are then followed by the chip erasecommand, which in turn invokes the Embedded Erasealgorithm. The device does not require the system topreprogram prior to erase. The Embedded Erase algo-rithm automatically preprograms and verifies the entirememory for an all zero data pattern prior to electricalerase. The system is not required to provide any con-trols or timings during these operations. Table 5 showsthe address and data requirements for the chip erasecommand sequence.

Any commands written to the chip during theEmbedded Erase algorithm are ignored. Note that ahardware reset during the chip erase operation imme-diately terminates the operation. The Chip Erase

Am29LV004B

sector erase operation immediately terminates theoperation. The Sector Erase command sequenceshould be reinitiated once the device has returned toreading array data, to ensure data integrity.

When the Embedded Erase algorithm is complete, thedevice returns to reading array data and addresses areno longer latched. The system can determine thestatus of the erase operation by using DQ7, DQ6, DQ2,or RY/BY#. (Refer to “Write Operation Status” for infor-mation on these status bits.)

Figure 4 illustrates the algorithm for the erase opera-tion. Refer to the Erase/Program Operations tables inthe “AC Characteristics” section for parameters, and toFigure 16 for timing diagrams.

the status of the program operation using the DQ7 orDQ6 status bits, just as in the standard program oper-ation. See “Write Operation Status” for moreinformation.

The system may also write the autoselect commandsequence when the device is in the Erase Suspendmode. The device allows reading autoselect codeseven at addresses within erasing sectors, since thecodes are not stored in the memory array. When thedevice exits the autoselect mode, the device reverts tothe Erase Suspend mode, and is ready for anothervalid operation. See “Autoselect Command Sequence”for more information.

The system must write the Erase Resume command(address bits are “don’t care”) to exit the erase suspendmode and continue the sector erase operation. Furtherwrites of the Resume command are ignored. AnotherErase Suspend command can be written after thedevice has resumed erasing.

Erase Suspend/Erase Resume Commands

The Erase Suspend command allows the system tointerrupt a sector erase operation and then read datafrom, or program data to, any sector not selected forerasure. This command is valid only during the sectorerase operation, including the 50 µs time-out periodduring the sector erase command sequence. TheErase Suspend command is ignored if written duringthe chip erase operation or Embedded Program algo-rithm. Writing the Erase Suspend command during theSector Erase time-out immediately terminates thetime-out period and suspends the erase operation.Addresses are “don’t-cares” when writing the EraseSuspend command.

When the Erase Suspend command is written during asector erase operation, the device requires a maximumof 20 µs to suspend the erase operation. However,when the Erase Suspend command is written duringthe sector erase time-out, the device immediately ter-minates the time-out period and suspends the eraseoperation.

After the erase operation has been suspended, thesystem can read array data from or program data toany sector not selected for erasure. (The device “erasesuspends” all sectors selected for erasure.) Normalread and write timings and command definitions apply.Reading at any address within erase-suspendedsectors produces status data on DQ7–DQ0. Thesystem can use DQ7, or DQ6 and DQ2 together, todetermine if a sector is actively erasing or is erase-sus-pended. See “Write Operation Status” for informationon these status bits.

After an erase-suspended program operation is com-plete, the system can once again read array data withinnon-suspended sectors. The system can determine

STARTWrite Erase Command SequenceData Poll from SystemNoEmbedded Erasealgorithmin progressData = FFh?YesErasure CompletedNotes:1.See Table 5 for erase command sequence.2.See “DQ3: Sector Erase Timer” for more information.Figure 4.Erase Operation

16Am29LV004B

Command Definitions

Table 5.

CommandSequence(Note 1)

Read (Note 5)Reset (Note 6)

Manufacturer ID

CyclesAm29LV004B Command Definitions

Bus Cycles (Notes 2-4)

First

Second Third Fourth Fifth Sixth Addr

Data

Addr

DataAddr

Data

AddrData

Addr

Data

RDF0AAAAAAAAAAAAA090AAAAB030

2AA2AA2AA2AA2AA2AAPAXXX2AA2AA

555555555555PD005555

555555

8080

555555

AAAA

2AA2AA

5555

555SA

1030

555555555555555555

90909090A020

X00X01X01(SA)X02PA

01B5B60001PD

AddrRAXXX555555555555555555XXXXXX555555XXXXXX

Data

114

Device ID, Top Boot Block 4Auto-Device ID, Bottom Boot Block4select

(Note 7)

Sector Protect Verify

4

(Note 8)ProgramUnlock Bypass

Unlock Bypass Program (Note 9)Unlock Bypass Reset (Note 10)Chip EraseSector Erase

Erase Suspend (Note 11)Erase Resume (Note 12)

43226611

Legend:X = Don’t careRA = Address of the memory location to be read. RD = Data read from location RA during read operation.PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CE# pulse, whichever happens later.Notes:1.See Table 1 for description of bus operations.2.All values are in hexadecimal.3.Except when reading array or autoselect data, all command bus cycles are write operations.4.Address bits A18–A11 are don’t cares for unlock and command cycles.5.No unlock or command cycles required when reading array data.6.The Reset command is required to return to reading array data when device is in the autoselect mode, or if DQ5 goes high (while the device is providing status data).7.The fourth cycle of the autoselect command sequence is a read cycle.PD = Data to be programmed at location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first.SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A18–A13 uniquely select any sector.8.The data is 00h for an unprotected sector and 01h for a protected sector. See “Autoselect Command Sequence” for more information.9.The Unlock Bypass command is required prior to the Unlock Bypass Program command.10.The Unlock Bypass Reset command is required to return to reading array data when the device is in the unlock bypass mode.11.The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation.12.The Erase Resume command is valid only during the Erase Suspend mode.Am29LV004B17

WRITE OPERATION STATUS

The device provides several bits to determine thestatus of a write operation: DQ2, DQ3, DQ5, DQ6,DQ7, and RY/BY#. Table 6 and the following subsec-tions describe the functions of these bits. DQ7,RY/BY#, and DQ6 each offer a method for determiningwhether a program or erase operation is complete or inprogress. These three bits are discussed first.

Table 6 shows the outputs for Data# Polling on DQ7.Figure 5 shows the Data# Polling algorithm.

STARTDQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the hostsystem whether an Embedded Algorithm is in progressor completed, or whether the device is in Erase Sus-pend. Data# Polling is valid after the rising edge of thefinal WE# pulse in the program or erase commandsequence.

During the Embedded Program algorithm, the deviceoutputs on DQ7 the complement of the datum pro-grammed to DQ7. This DQ7 status also applies toprogramming during Erase Suspend. When theEmbedded Program algorithm is complete, the deviceoutputs the datum programmed to DQ7. The systemmust provide the program address to read valid statusinformation on DQ7. If a program address falls within aprotected sector, Data# Polling on DQ7 is active forapproximately 1 µs, then the device returns to readingarray data.

During the Embedded Erase algorithm, Data# Pollingproduces a “0” on DQ7. When the Embedded Erasealgorithm is complete, or if the device enters the EraseSuspend mode, Data# Polling produces a “1” on DQ7.This is analogous to the complement/true datum outputdescribed for the Embedded Program algorithm: theerase function changes all the bits in a sector to “1”;prior to this, the device outputs the “complement,” or“0.” The system must provide an address within any ofthe sectors selected for erasure to read valid statusinformation on DQ7.

After an erase command sequence is written, if allsectors selected for erasing are protected, Data#Polling on DQ7 is active for approximately 100 µs, thenthe device returns to reading array data. If not allselected sectors are protected, the Embedded Erasealgorithm erases the unprotected sectors, and ignoresthe selected sectors that are protected.

When the system detects DQ7 has changed from thecomplement to true data, it can read valid data at DQ7–DQ0 on the following read cycles. This is because DQ7may change asynchronously with DQ0–DQ6 whileOutput Enable (OE#) is asserted low. Figure 17, Data#Polling Timings (During Embedded Algorithms), in the“AC Characteristics” section illustrates this.

Read DQ7–DQ0Addr = VADQ7 = Data?YesNoNoDQ5 = 1?YesRead DQ7–DQ0Addr = VADQ7 = Data?YesNoFAILPASSNotes:1.VA = Valid address for programming. During a sector erase operation, a valid address is an address within any sector selected for erasure. During chip erase, a valid address is any non-protected sector address.2.DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5.Figure 5.Data# Polling Algorithm

18Am29LV004B

RY/BY#: Ready/Busy#

The RY/BY# is a dedicated, open-drain output pin thatindicates whether an Embedded Algorithm is inprogress or complete. The RY/BY# status is valid afterthe rising edge of the final WE# pulse in the commandsequence. Since RY/BY# is an open-drain output,several RY/BY# pins can be tied together in parallelwith a pull-up resistor to VCC.

If the output is low (Busy), the device is actively erasingor programming. (This includes programming in theErase Suspend mode.) If the output is high (Ready),the device is ready to read array data (including duringthe Erase Suspend mode), or is in the standby mode.Table 6 shows the outputs for RY/BY#. Figures 14, 15and 16 shows RY/BY# for reset, program, and eraseoperations, respectively.

Table 6 shows the outputs for Toggle Bit I on DQ6.Figure 6 shows the toggle bit algorithm. Figure 18 in the“AC Characteristics” section shows the toggle bit timingdiagrams. Figure 19 shows the differences betweenDQ2 and DQ6 in graphical form. See also the subsec-tion on DQ2: Toggle Bit II.

DQ2: Toggle Bit II

The “Toggle Bit II” on DQ2, when used with DQ6, indi-cates whether a particular sector is actively erasing(that is, the Embedded Erase algorithm is in progress),or whether that sector is erase-suspended. Toggle BitII is valid after the rising edge of the final WE# pulse inthe command sequence.

DQ2 toggles when the system reads at addresseswithin those sectors that have been selected for era-sure. (The system may use either OE# or CE# tocontrol the read cycles.) But DQ2 cannot distinguishwhether the sector is actively erasing or is erase-sus-pended. DQ6, by comparison, indicates whether thedevice is actively erasing, or is in Erase Suspend, butcannot distinguish which sectors are selected for era-sure. Thus, both status bits are required for sector andmode information. Refer to Table 6 to compare outputsfor DQ2 and DQ6.

Figure 6 shows the toggle bit algorithm in flowchartform, and the section “DQ2: Toggle Bit II” explains thealgorithm. See also the DQ6: Toggle Bit I subsection.Figure 18 shows the toggle bit timing diagram. Figure19 shows the differences between DQ2 and DQ6 ingraphical form.

DQ6: Toggle Bit I

Toggle Bit I on DQ6 indicates whether an EmbeddedProgram or Erase algorithm is in progress or complete,or whether the device has entered the Erase Suspendmode. Toggle Bit I may be read at any address, and isvalid after the rising edge of the final WE# pulse in thecommand sequence (prior to the program or eraseoperation), and during the sector erase time-out.During an Embedded Program or Erase algorithmoperation, successive read cycles to any addresscause DQ6 to toggle. The system may use either OE#or CE# to control the read cycles. When the operationis complete, DQ6 stops toggling.

After an erase command sequence is written, if allsectors selected for erasing are protected, DQ6 togglesfor approximately 100 µs, then returns to reading arraydata. If not all selected sectors are protected, theEmbedded Erase algorithm erases the unprotectedsectors, and ignores the selected sectors that areprotected.

The system can use DQ6 and DQ2 together to deter-mine whether a sector is actively erasing or is erase-suspended. When the device is actively erasing (that is,the Embedded Erase algorithm is in progress), DQ6toggles. When the device enters the Erase Suspendmode, DQ6 stops toggling. However, the system mustalso use DQ2 to determine which sectors are erasingor erase-suspended. Alternatively, the system can useDQ7 (see the subsection on DQ7: Data# Polling).If a program address falls within a protected sector,DQ6 toggles for approximately 2 µs after the programcommand sequence is written, then returns to readingarray data.

DQ6 also toggles during the erase-suspend-programmode, and stops toggling once the EmbeddedProgram algorithm is complete.

Reading Toggle Bits DQ6/DQ2

Refer to Figure 6 for the following discussion. When-ever the system initially begins reading toggle bitstatus, it must read DQ7–DQ0 at least twice in a row todetermine whether a toggle bit is toggling. Typically, thesystem would note and store the value of the toggle bitafter the first read. After the second read, the systemwould compare the new value of the toggle bit with thefirst. If the toggle bit is not toggling, the device has com-pleted the program or erase operation. The system canread array data on DQ7–DQ0 on the following readcycle.

However, if after the initial two read cycles, the systemdetermines that the toggle bit is still toggling, thesystem also should note whether the value of DQ5 ishigh (see the section on DQ5). If it is, the systemshould then determine again whether the toggle bit istoggling, since the toggle bit may have stopped tog-gling just as DQ5 went high. If the toggle bit is no longertoggling, the device has successfully completed theprogram or erase operation. If it is still toggling, thedevice did not completed the operation successfully,and the system must write the reset command to returnto reading array data.

19

Am29LV004B

The remaining scenario is that the system initiallydetermines that the toggle bit is toggling and DQ5 hasnot gone high. The system may continue to monitor thetoggle bit and DQ5 through successive read cycles,determining the status as described in the previousparagraph. Alternatively, it may choose to performother system tasks. In this case, the system must startat the beginning of the algorithm when it returns todetermine the status of the operation (top of Figure 6).

STARTRead DQ7–DQ0(Note 1)DQ5: Exceeded Timing Limits

DQ5 indicates whether the program or erase time hasexceeded a specified internal pulse count limit. Underthese conditions DQ5 produces a “1.” This is a failurecondition that indicates the program or erase cycle wasnot successfully completed.

The DQ5 failure condition may appear if the systemtries to program a “1” to a location that is previously pro-grammed to “0.” Only an erase operation can changea “0” back to a “1.” Under this condition, the devicehalts the operation, and when the operation hasexceeded the timing limits, DQ5 produces a “1.”Under both these conditions, the system must issue thereset command to return the device to reading arraydata.

Read DQ7–DQ0Toggle Bit = Toggle?YesNoNoDQ5 = 1?YesRead DQ7–DQ0Twice(Notes1, 2)DQ3: Sector Erase Timer

After writing a sector erase command sequence, thesystem may read DQ3 to determine whether or not anerase operation has begun. (The sector erase timerdoes not apply to the chip erase command.) If addi-tional sectors are selected for erasure, the entire time-out also applies after each additional sector erase com-mand. When the time-out is complete, DQ3 switchesfrom “0” to “1.” If the time between additional sectorerase commands from the system can be assumed tobe less than 50 µs, the system need not monitor DQ3.See also the “Sector Erase Command Sequence”section.

After the sector erase command sequence is written,the system should read the status on DQ7 (Data#Polling) or DQ6 (Toggle Bit I) to ensure the device hasaccepted the command sequence, and then read DQ3.If DQ3 is “1”, the internally controlled erase cycle hasbegun; all further commands (other than Erase Sus-pend) are ignored until the erase operation is complete.If DQ3 is “0”, the device will accept additional sectorerase commands. To ensure the command has beenaccepted, the system software should check the statusof DQ3 prior to and following each subsequent sectorerase command. If DQ3 is high on the second statuscheck, the last command might not have beenaccepted. Table 6 shows the outputs for DQ3.

Toggle Bit = Toggle?YesProgram/EraseOperation Not Complete, Write Reset CommandNoProgram/EraseOperation CompleteNotes:1.Read toggle bit twice to determine whether or not it is toggling. See text.2.Recheck toggle bit because it may stop toggling as DQ5 changes to “1” . See text.Figure 6.Toggle Bit Algorithm

20Am29LV004B

Table 6.

Operation

Standard Embedded Program AlgorithmModeEmbedded Erase AlgorithmErase Suspend Mode

Reading within Erase Suspended SectorReading within Non-Erase Suspended SectorErase-Suspend-Program

Write Operation Status

DQ6ToggleToggleNo toggleDataToggle

DQ5(Note 1)

000Data0

DQ3N/A1N/ADataN/A

DQ2(Note 2)No toggleToggleToggleDataN/A

RY/BY#

00110

DQ7(Note 2)DQ7#01DataDQ7#

Notes:1.DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. See “DQ5: Exceeded Timing Limits” for more information.2.DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.Am29LV004B21

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°CAmbient Temperature

with Power Applied. . . . . . . . . . . . . . –65°C to +125°CVoltage with Respect to Ground

VCC (Note 1). . . . . . . . . . . . . . . . .–0.5 V to +4.0 VA9, OE#,

and RESET# (Note 2). . . . . . . . .–0.5 V to +12.5 VAll other pins

(Note 1). . . . . . . . . . . . . . . . . –0.5 V to VCC+0.5 VOutput Short Circuit Current (Note 3) . . . . . . 200 mA

Notes:1.Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, input or I/O pins may overshoot VSS to –2.0 V for periods of up to 20 ns. See Figure 7. Maximum DC voltage on input or I/O pins is VCC +0.5 V. During voltage transitions, input or I/O pins may overshoot to VCC +2.0 V for periods up to 20 ns. See Figure 8.2.Minimum DC input voltage on pins A9, OE#, and RESET# is –0.5 V. During voltage transitions, A9, OE#, and RESET# may overshoot VSS to –2.0 V for periods of up to 20 ns. See Figure 7. Maximum DC input voltage on pin A9 is +12.5 V which may overshoot to 14.0 V for periods up to 20 ns.3.No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second.Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability.VCC+2.0 VVCC+0.5 V2.0 V

20 ns20 ns+0.8 V–0.5 V–2.0 V20 ns20 ns20 nsFigure 7.Maximum Negative

OvershootWaveform

20 nsFigure 8.Maximum Positive

OvershootWaveform

OPERATING RANGES

Commercial (C) Devices

Ambient Temperature (TA) . . . . . . . . . . . 0°C to +70°CIndustrial (I) Devices

Ambient Temperature (TA) . . . . . . . . . –40°C to +85°CExtended (E) Devices

Ambient Temperature (TA) . . . . . . . . –55°C to +125°CVCC Supply Voltages

VCC for all devices . . . . . . . . . . . . . . . . .2.7 V to 3.6 V

Operating ranges define those limits between which the func-tionality of the device is guaranteed.22Am29LV004B

DC CHARACTERISTICSCMOS Compatible

Parameter

ILIILITILOICC1ICC2ICC3ICC4ICC5VILVIHVIDVOLVOH1VOH2VLKO

Description

Input Load CurrentA9 Input Load CurrentOutput Leakage CurrentVCC Active Read Current (Notes 1, 2)

VCC Active Write Current (Notes 2, 3, 5)

VCC Standby Current (Note 2)VCC Reset Current (Note 2)Automatic Sleep Mode (Notes 2, 4)Input Low VoltageInput High Voltage

Voltage for Autoselect and Temporary Sector UnprotectOutput Low VoltageOutput High VoltageLow VCC Lock-Out Voltage (Note 5)

VCC = 3.3 V

Test Conditions

VIN = VSS to VCC, VCC = VCC max

VCC = VCC max; A9 = 12.5 VVOUT = VSS to VCC, VCC = VCC maxCE# = VIL, OE# = VIHCE# = VIL, OE# = VIHCE#, RESET# = VCC±0.3 VRESET# = VSS ± 0.3 VVIH = VCC ± 0.3 V; VIL = VSS ± 0.3 V

–0.50.7 x VCC11.5

5 MHz1 MHz

72150.20.20.2

Min

Typ

Max±1.035±1.0124305550.8VCC + 0.312.5

UnitµAµAµA

mA

mAµAµAµAVVVVV

IOL = 4.0 mA, VCC = VCC min 0.45IOH = –2.0 mA, VCC = VCC min IOH = –100 µA, VCC = VCC min

0.85 VCCVCC–0.42.3

2.5

V

Notes:1.The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH. Typical VCC is 3.0 V.2.Maximum ICC specifications are tested with VCC = VCCmax.3.ICC active while Embedded Erase or Embedded Program is in progress.4.Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns.5.Not 100% tested.Am29LV004B23

DC CHARACTERISTICS (continued)Zero Power Flash

20Supply Current in mA15

10

5

0

0

500

1000

1500

2000Time in ns

Note: Addresses are switching at 1 MHz2500300035004000

Figure 9.

ICC1 Current vs. Time (Showing Active and Automatic SleepCurrents)

10

8Supply Current in mA3.6 V

6

2.7 V

4

2

01

2

3

Frequency in MHz

Note: T = 25 °C45

Figure 10.

Typical ICC1 vs. Frequency

24Am29LV004B

TEST CONDITIONS

3.3 V

2.7 kΩ

Table 7.

Test Condition

Test Specifications

-70

-90,-1201 TTL gate 30

50.0–3.0

100

pFnsVUnit

DeviceUnderTest

CL

6.2 kΩ

Output Load

Output Load Capacitance, CL(including jig capacitance) Input Rise and Fall TimesInput Pulse LevelsInput timing measurement reference levels

Output timing measurement reference levels

1.5 V1.5

V

Note: Diodes are IN30 or equivalentFigure 11.Test Setup

KEY TO SWITCHING WAVEFORMS

WAVEFORM

INPUTS

Steady

Changing from H to LChanging from L to H

Don’t Care, Any Change Permitted

Does Not Apply

Changing, State Unknown

Center Line is High Impedance State (High Z)

OUTPUTS

3.0 V0.0 VInput1.5 VMeasurement Level1.5 VOutputFigure 12.Input Waveforms and Measurement Levels

Am29LV004B25

AC CHARACTERISTICSRead Operations

ParameterJEDECtAVAVtAVQVtELQVtGLQVtEHQZtGHQZ

StdtRCtACCtCEtOEtDFtDFtOEH

Description

Read Cycle Time (Note 1)Address to Output DelayChip Enable to Output DelayOutput Enable to Output DelayChip Enable to Output High Z (Note 1)Output Enable to Output High Z (Note 1)Output Enable Hold Time (Note 1)

ReadToggle and Data# Polling

CE# = VILOE# = VILOE# = VIL

Test Setup

MinMaxMaxMaxMaxMaxMinMinMin

-70707070302525

Speed Option

-909090903530300100

-120120120120503030

Unitnsnsnsnsnsnsnsnsns

tAXQXtOH

Output Hold Time From Addresses, CE# or OE#, Whichever Occurs First (Note 1)

Notes:1.Not 100% tested.2.See Figure 11andTable 7 for test specifications.tRCAddressesCE#tOEtOEHWE#HIGH ZtCEOutput ValidtOHHIGH ZtDFAddresses StabletACCOE#OutputsRESET#RY/BY#0 VFigure 13.Read Operations Timings

26Am29LV004B

AC CHARACTERISTICSHardware Reset (RESET#)

ParameterJEDEC

StdtREADYtREADYtRPtRHtRPDtRB

Description

RESET# Pin Low (During Embedded Algorithms) to Read or Write (See Note)RESET# Pin Low (NOT During Embedded Algorithms) to Read or Write (See Note)RESET# Pulse Width

RESET# High Time Before Read (See Note)RESET# Low to Standby ModeRY/BY# Recovery Time

Test Setup

MaxMaxMinMinMinMin

All Speed Options

2050050050200

Unitµsnsnsnsµsns

Note: Not 100% tested.RY/BY#CE#, OE#tRHRESET#tRPtReadyReset Timings NOT during Embedded AlgorithmsReset Timings during Embedded AlgorithmstReadyRY/BY#tRBCE#, OE#RESET#tRPFigure 14.RESET# Timings

Am29LV004B27

AC CHARACTERISTICSErase/Program Operations

ParameterJEDECtAVAVtWLAXtDVWHtWLWHtAVWLtWHDX

StdtWCtAHtDStWPtAStDHtOES

tGHWLtELWLtWHEHtWHWLtWHWH1tWHWH2

tGHWLtCStCHtWPHtWHWH1tWHWH2tVCStRBtBUSY

Description

Write Cycle Time (Note 1)Address Hold TimeData Setup TimeWrite Pulse WidthAddress Setup TimeData Hold Time

Output Enable Setup Time Read Recovery Time Before Write (OE# High to WE# Low)CE# Setup TimeCE# Hold TimeWrite Pulse Width High

Programming Operation (Note 2)Sector Erase Operation (Note 2)VCC Setup Time (Note 1)Recovery Time from RY/BY#

Program/Erase Valid to RY/BY# Delay

MinMinMinMinMinMinMinMinMinMinMinTypTypMinMinMin

-7070453535

Speed Options

-909045350000003090.750090

-120120505050

Unitnsnsnsnsnsnsnsnsnsnsnsµssecµsnsns

Notes:1.Not 100% tested.2.See the “Erase and Programming Performance” section for more information.28Am29LV004B

AC CHARACTERISTICS

Program Command Sequence (last two cycles)tWCAddresses555htASPAtAHCE#OE#tWPWE#tCStDSDatatDHPDtBUSYRY/BY#VCCtVCSNote: PA = program address, PD = program data, DOUT is the true data at the program address.Read Status Data (last two cycles)PAPAtCHtWHWH1tWPHA0hStatusDOUTtRBFigure 15.Program Operation Timings

Am29LV004B29

AC CHARACTERISTICS

Erase Command Sequence (last two cycles)tWCAddresses2AAhtASSA555h for chip eraseRead Status DataVAtAHVACE#tCHtWPWE#tCStDStDHData55h30h10 for Chip EraseInProgressCompleteOE#tWPHtWHWH2tBUSYRY/BY#tVCSVCCtRBNote: SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”).Figure 16.Chip/Sector Erase Operation Timings

30Am29LV004B

AC CHARACTERISTICS

tRCAddressesVAtACCCE#tCHOE#tOEHWE#tOHDQ7ComplementComplementTrueValid DataHigh ZVAVAtCEtOEtDFDQ0–DQ6tBUSYRY/BY#Status DataStatus DataTrueValid DataHigh ZNote: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.Figure 17.Data# Polling Timings (During Embedded Algorithms)

tRCAddressesVAtACCCE#tCHOE#tOEHWE#tOHDQ6/DQ2tBUSYRY/BY#High ZVAVAVAtCEtOEtDFValid Status(first read)Valid Status(second read)Valid Status(stops toggling)Valid DataNote: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle.Figure 18.Toggle Bit Timings (During Embedded Algorithms)

Am29LV004B31

AC CHARACTERISTICS

EnterEmbeddedErasing

WE#

EraseSuspendEraseEnter EraseSuspend Program

EraseSuspendProgram

EraseResume

Erase Suspend

Read

Erase

EraseComplete

Erase SuspendRead

DQ6

DQ2

Note: The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an erase-suspended sector. Figure 19.DQ2 vs. DQ6

Temporary Sector Unprotect

ParameterJEDEC

StdtVIDRtRSP

Description

VID Rise and Fall Time (See Note)RESET# Setup Time for Temporary Sector Unprotect

MinMin

All Speed Options

5004

Unitnsµs

Note: Not 100% tested.12 VRESET#0 or 3 VtVIDRProgram or Erase Command SequencetVIDR0 or 3 VCE#WE#tRSPRY/BY# Figure 20.Temporary Sector Unprotect Timing Diagram

32Am29LV004B

AC CHARACTERISTICS

VIDVIHRESET#SA, A6,A1, A0Valid*Sector Protect/UnprotectValid*Verify40hSector Protect: 150 µsSector Unprotect: 15 msValid*Data1 µsCE#60h60hStatusWE#OE#* For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.Figure 21.Sector Protect/Unprotect Timing Diagram

Am29LV004B33

AC CHARACTERISTICS

Alternate CE# Controlled Erase/Program Operations

ParameterJEDECtAVAVtELAXtDVEHtELEHtAVELtEHDX

StdtWCtAHtDStCPtAStDHtOES

tGHELtWLELtEHWHtEHELtWHWH1tWHWH2

tGHELtWStWHtCPHtWHWH1tWHWH2

Description

Write Cycle Time (Note 1)Address Hold TimeData Setup TimeCE# Pulse WidthAddress Setup TimeData Hold Time

Output Enable Setup TimeRead Recovery Time Before Write (OE# High to WE# Low)WE# Setup TimeWE# Hold TimeCE# Pulse Width High

Programming Operation (Note 2)Sector Erase Operation (Note 2)

MinMinMinMinMinMinMinMinMinMinMinTypTyp

-7070453535

Speed Options

-909045350000003090.7

-120120505050

Unitnsnsnsnsnsnsnsnsnsnsnsµssec

Notes:1.Not 100% tested.2.See the “Erase and Programming Performance” section for more information.34Am29LV004B

AC CHARACTERISTICS

555 for program2AA for erase PA for programSA for sector erase555 for chip erase Data# PollingPAAddressestWCtWHWE#tGHELOE#tCPCE#tWStCPHtDStDHDatatRHA0 for program55 for erase PD for program30 for sector erase10 for chip erase tAStAHtWHWH1 or 2tBUSYDQ7#DOUTRESET#RY/BY#Notes: 1.PA = Program Address, PD = Program Data, DQ7# = complement of the data written to the device, DOUT is the data written to the device.2.Figure indicates the last two bus cycles of the command sequence.Figure 22.Alternate CE# Controlled Write Operation Timings

Am29LV004B35

ERASE AND PROGRAMMING PERFORMANCE

ParameterSector Erase TimeChip Erase Time Byte Programming TimeChip Programming Time(Note 3)

Typ (Note 1)

0.7794.5

30013.5Max (Note 2)

15

Unitssµss

Excludes system level overhead (Note 5)

Comments

Excludes 00h programming prior to erasure (Note 4)

Notes:1.Typical program and erase times assume the following conditions: 25°C, 3.0 V VCC, 1,000,000 cycles. Additionally, programming typicals assume checkerboard pattern.2.Under worst case conditions of 90°C, VCC = 2.7 V, 1,000,000 cycles.3.The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed.4.In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.5.System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 5 for further information on command definitions.6.The device has a minimum guaranteed erase and program cycle endurance of 1,000,000 cycles. LATCHUP CHARACTERISTICS

Description

Input voltage with respect to VSS on all pins except I/O pins (including A9, OE#, and RESET#)

Input voltage with respect to VSS on all I/O pinsVCC Current

Min–1.0 V–1.0 V–100 mA

Max12.5 VVCC + 1.0 V+100 mA

Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time.TSOP AND SO PIN CAPACITANCE

Parameter Symbol

CINCOUTCIN2

Parameter DescriptionInput CapacitanceOutput CapacitanceControl Pin Capacitance

Test SetupVIN = 0VOUT = 0VIN = 0

Typ68.57.5

Max7.5129

UnitpFpFpF

Notes:1.Sampled, not 100% tested.2.Test conditions TA = 25°C, f = 1.0 MHz.DATA RETENTION

Parameter

Minimum Pattern Data Retention Time

Test Conditions

150°C125°C

Min1020

UnitYearsYears

36Am29LV004B

PHYSICAL DIMENSIONS*TS 040—40-Pin Standard TSOP

Dwg rev AA; 10/99* For reference only. BSC is an ANSI standard for Basic Space Centering.Am29LV004B37

PHYSICAL DIMENSIONS*TSR040—40-Pin Reverse TSOP

Dwg rev AA; 10/99* For reference only. BSC is an ANSI standard for Basic Space Centering.38Am29LV004B

REVISION SUMMARYRevision A (January 1998)

Initial release.

Distinctive Characteristics

Added bullet for 20-year data retention at 125°C.DC Characteristics—CMOS Compatible

Revision B (June 1998)

Expanded data sheet from Advanced Information toPreliminary version.Distinctive Characteristics

Changed “Manufactured on 0.35 µm process technology”to “Manufactured on 0.32 µm process technology”.General Description

ICC1, ICC2, ICC3, ICC4, ICC5: Added Note 2 “MaximumICC specifications are tested with VCC = VCCmax”.

Revision D (November 18, 1999)

AC Characteristics—Figure 15. Program

Operations Timing and Figure 16. Chip/Sector Erase Operations

Deleted tGHWL and changed OE# waveform to start athigh.

Physical Dimensions

Replaced figures with more detailed illustrations.

Second paragraph: Changed “This device is manufac-tured using AMD’s 0.35 µm process technology” to“This device is manufactured using AMD’s 0.32 µmprocess technology”.

Revision C (January 1999)

Global

Removed the -80 speed option.

Revision D+1 (November 13, 2000)

Global

Added table of contents. Deleted burn-in option fromOrdering Information section.

TrademarksCopyright © 2000 Advanced Micro Devices, Inc. All rights reserved.

AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc.

Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

Am29LV004B39