专利名称：Method And Apparatus For Improving The
Efficiency Of A Processor Instruction Pipeline
发明人：Atsushi Hayashi申请号：US11551833申请日：20061023
公开号：US20080098204A1公开日：20080424
专利附图：
摘要：A system and method are disclosed which may include providing a processorinstruction pipeline having a main line and a branch line; executing at least one wait cyclefor at least one wait instruction in said pipeline; and advancing at least selected
instructions, that are initially located subsequent to at least one wait instruction in saidpipeline, through the pipeline during the at least one wait cycle.
申请人：Atsushi Hayashi
地址：Austin TX US
国籍：US
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