Method, architecture and circuit for product term

专利名称：Method, architecture and circuit for product

term allocation

发明人：Jeffrey Mark Marshall申请号：US09322946申请日：19990528公开号：US06236230B1公开日：20010522

专利附图：

摘要：A product-term allocation architecture for a programmable device, comprisinga plurality of logic gate sections and a fully rotatable, programmable OR-type array. Afirst one of the logic gate sections may comprise a first plurality of fixed logic gates. Each

of the first plurality of fixed logic gates may have m inputs, m being an integer of at leastone. A second one of the logic gate sections may comprise a second plurality of fixedlogic gates. Each of the second plurality of fixed logic gates having n inputs, n being aninteger of at least two and being different from m. The plurality of logic gate sectionsmay be configured to provide p outputs, p being an integer equal to or greater than thetotal number of the fixed logic gates and less than the total number of fixed logic gateinputs. The fully rotatable, programmable OR-type array may receive the p outputs andmay be configured to generate a plurality of array outputs.

申请人：CYPRESS SEMICONDUCTOR CORP.

代理人：Christopher P. Maiorana, P.C.

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