Digital signal processor containing scalar process

专利名称：Digital signal processor containing scalar

processor and a plurality of vectorprocessors operating from a singleinstruction

发明人：Steven G. Morton申请号：US09256961申请日：19990224公开号：US06317819B1公开日：20011113

专利附图：

摘要：A digital data processor integrated circuit () includes a plurality of functionally

identical first processor elements (A) and a second processor element (). The firstprocessor elements are bidirectionally coupled to a first cache () via a crossbar switchmatrix (). The second processor element is coupled to a second cache (). Each of the firstcache and the second cache contain a two-way, set-associative cache memory that uses aleast-recently-used (LRU) replacement algorithm and that operates with a use-as-fillmode to minimize a number of wait states said processor elements need experiencebefore continuing execution after a cache-miss. An operation of each of the firstprocessor elements and an operation of the second processor element are lockedtogether during an execution of a single instruction read from the second cache. Theinstruction specifies, in a first portion that is coupled in common to each of the pluralityof first processor elements, the operation of each of the plurality of first processorelements in parallel. A second portion of the instruction specifies the operation of thesecond processor element. Also included is a motion estimator () and an internal data buscoupling together a first parallel port (A), a second parallel port (B), a third parallel port(C), an external memory interface (), and a data input/output of the first cache and thesecond cache.

申请人：MORTON STEVEN G.

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