元器件交易网www.cecb2b.comMOTOROLASEMICONDUCTOR TECHNICAL DATA Order this documentby MCM6226BB/D128K x 8 Bit Static RandomAccess MemoryThe MCM6226BB is a 1,048,576 bit static random access memory organizedas 131,072 words of 8 bits. Static design eliminates the need for external clocksor timing strobes while CMOS circuitry reduces power consumption and providesfor greater reliability.The MCM6226BB is equipped with both chip enable (E1 and E2) and outputenable (G) pins, allowing for greater system flexibility and eliminating bus conten-tion problems.The MCM6226BB is available in 300 mil and 400 mil, 32 lead surface–mountSOJ packages.••••••Single 5 V ± 10% Power SupplyFast Access Times:15/17/20/25/35 nsEqual Address and Chip Enable Access TimesAll Inputs and Outputs are TTL CompatibleThree State OutputsLow Power Operation: 190/180/165/150/130 mA Maximum, Active ACBLOCK DIAGRAMMCM6226BBXJ PACKAGE400 MIL SOJCASE 857A–02EJ PACKAGE300 MIL SOJCASE 857–02PIN ASSIGNMENTNCAAAAA12345671011121314151632313029282726252423222120191817VCCAE2WAAAAGAE1DQDQDQDQDQAAAAAAAAAROWDECODERMEMORY MATRIX512 ROWS x 2048 COLUMNSAAAAAADQDQDQVSSDQDQINPUTDATACONTROLCOLUMN I/OCOLUMN DECODERPIN NAMESA. . . . . . . . . . . . . . . . . . . . Address InputsW. . . . . . . . . . . . . . . . . . . . . Write EnableG. . . . . . . . . . . . . . . . . . . Output EnableE1, E2. . . . . . . . . . . . . . . . Chip EnablesDQ. . . . . . . . . . . . . Data Inputs/OutputsNC. . . . . . . . . . . . . . . . . . No ConnectionVCC. . . . . . . . . . . . . + 5 V Power SupplyVSS. . . . . . . . . . . . . . . . . . . . . . . . GroundE1E2WGAAAAAAAAREV 210/31/96© Motorola, Inc. 1996MOTOROLA FAST SRAMMCM6226BB1元器件交易网www.cecb2b.com TRUTH TABLEE1HXLLLE2XLHHHGXXHLXWXXHHLModeNot SelectedNot SelectedOutput DisabledReadWriteI/O PinHigh–ZHigh–ZHigh–ZDoutDinCycle———ReadWriteCurrentISB1, ISB2ISB1, ISB2ICCAICCAICCAH = High, L = Low, X = Don’t CareABSOLUTE MAXIMUM RATINGS (See Note)RatingPower Supply Voltage Relative to VSSVoltage Relative to VSS for Any Pin Except VCCOutput Current (per I/O)Power DissipationTemperature Under BiasOperating TemperatureStorage TemperatureSymbolVCCVin, VoutIoutPDTbiasTAValue– 0.5 to 7.0– 0.5 to VCC + 0.5±201.0– 10 to + 850 to + 70UnitVVmAW°C°CThis device contains circuitry to protect theinputs against damage due to high static volt-ages or electric fields; however, it is advisedthat normal precautions be taken to avoidapplication of any voltage higher than maxi-mum rated voltages to these high–impedancecircuits.This CMOS memory circuit has been de-signed to meet the dc and ac specificationsshown in the tables, after thermal equilibriumhas been established. The circuit is in a testsocket or mounted on a printed circuit boardand transverse air flow of at least 500 linear feetper minute is maintained.Tstg– 55 to + 150°CNOTE:Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS areexceeded. Functional operation should be restricted to RECOMMENDED OPER-ATING CONDITIONS. Exposure to higher than recommended voltages forextended periods of time could affect device reliability.DC OPERATING CONDITIONS AND CHARACTERISTICS(VCC = 5.0 V ±10%, TA = 0 to 70°C, Unless Otherwise Noted)RECOMMENDED OPERATING CONDITIONSParameterSupply Voltage (Operating Voltage Range)Input High VoltageInput Low Voltage*VIL (min) = – 0.5 V dc; VIL (min) = –2.0 V ac (pulse width ≤ 20 ns).**VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC +2 V ac (pulse width ≤ 20 ns).SymbolVCCVIHVILMin4.52.2–0.5*Max5.5VCC + 0.3**0.8UnitVVVDC CHARACTERISTICS AND SUPPLY CURRENTSParameterInput Leakage Current (All Inputs, Vin = 0 to VCC)Output Leakage Current (E* = VIH, Vout = 0 to VCC)AC Active Supply Current (Iout = 0 mA, all inputs =VIL or VIH, VIL = 0, VIH ≥ 3 V, cycle time ≥tAVAV min, VCC = max)MCM6226BB–15: tAVAV = 15 nsMCM6226BB–17: tAVAV = 17 nsMCM6226BB–20: tAVAV = 20 nsMCM6226BB–25: tAVAV = 25 nsMCM6226BB–35: tAVAV = 35 nsMCM6226BB–15: tAVAV = 15 nsMCM6226BB–17: tAVAV = 17 nsMCM6226BB–20: tAVAV = 20 nsMCM6226BB–25: tAVAV = 25 nsMCM6226BB–35: tAVAV = 35 nsSymbolIlkg(I)Ilkg(O)ICCAMin——————————————2.4Max± 1± 11951801651501304035302550.4—UnitµAµAmAAC Standby Current (VCC = max, E* = VIH, f = fmax)ISB1mACMOS Standby Current (E* ≥ VCC –0.2 V, Vin ≤ VSS +0.2 Vor ≥ VCC –0.2 V, VCC = max, f = 0 MHz)Output Low Voltage (IOL = +8.0 mA)Output High Voltage (IOH = –4.0 mA)*E1 and E2 are represented by E in this data sheet. E2 is of opposite polarity to E1.ISB2VOLVOHmAVVMCM6226BB2MOTOROLA FAST SRAM元器件交易网www.cecb2b.comCAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25°C, Periodically Sampled Rather Than 100% Tested)CharacteristicInput Capacitance I/O Capacitance All Inputs Except Clocks and DQsE1, E2, G, and WDQSymbolCinCckCI/OTyp455Max688UnitpFpFAC OPERATING CONDITIONS AND CHARACTERISTICS(VCC = 5.0 V ±10%, TA = 0 to + 70°C, Unless Otherwise Noted)Input Pulse Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 VInput Rise/Fall Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 nsInput Timing Measurement Reference Level. . . . . . . . . . . . . . . 1.5 VOutput Timing Measurement Reference Level. . . . . . . . . . . . . 1.5 VOutput Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1aREAD CYCLE TIMING (See Notes 1, 2, and 3)6226BB–15ParameterRead Cycle TimeAddress Access TimeEnable Access TimeOutput Enable Access TimeOutput Hold from AddressChangeEnable Low to Output ActiveOutput Enable Low to OutputActiveEnable High to Output High–ZOutput Enable High to OutputHigh–ZSymboltAVAVtAVQVtELQVtGLQVtAXQXtELQXtGLQXtEHQZtGHQZMin15———350——Max—15156———666226BB–17Min17———350——Max—17177———776226BB–20Min20———350——Max—20207———776226BB–25Min25———350——Max—25258———886226BB–35Min35———350——Max—35358———88Unitnsnsnsnsnsnsnsnsns6, 7, 86, 7, 86, 7, 86, 7, 85Notes4NOTES:1.W is high for read cycle.2.Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus con-tention conditions during read and write cycles.3.E1 and E2 are represented by E in this data sheet. E2 is of opposite polarity to E1.4.All timings are referenced from the last valid address to the first transitioning address.5.Addresses valid prior to or coincident with E going low.6.At any given voltage and temperature, tEHQZ max is less than tELQX min, and tGHQZ max is less than tGLQX min, both for a given deviceand from device to device.7.Transition is measured ± 500 mV from steady–state voltage with load of Figure 1b.8.This parameter is sampled and not 100% tested.9.Device is continuously selected (E ≤ VIL, G ≤ VIL).TIMING LIMITS+5 VOUTPUTZ0 = 50 ΩRL = 50 ΩVL = 1.5 VOUTPUT255 Ω5 pF480 ΩThe table of timing values shows either aminimum or a maximum limit for each param-eter. Input requirements are specified fromthe external system point of view. Thus, ad-dress setup time is shown as a minimumsince the system must supply at least thatmuch time. On the other hand, responsesfrom the memory are specified from the de-vice point of view. Thus, the access time isshown as a maximum since the device neverprovides data later than that time.(a)(b)Figure 1. AC Test LoadsMOTOROLA FAST SRAMMCM6226BB3元器件交易网www.cecb2b.comREAD CYCLE 1 (See Notes 1, 2, 3, and 9)tAVAVA (ADDRESS)tAXQXQ (DATA OUT)PREVIOUS DATA VALIDtAVQVDATA VALIDREAD CYCLE 2 (See Notes 3 and 5)tAVAVA (ADDRESS)tELQVE (CHIP ENABLE)tELQXG (OUTPUT ENABLE)tGLQVtGLQXQ (DATA OUT)HIGH–ZtAVQVtELICCHICCSUPPLY CURRENTISBtEHICCLDATA VALIDtGHQZtEHQZMCM6226BB4MOTOROLA FAST SRAM元器件交易网www.cecb2b.comWRITE CYCLE 1 (W Controlled, See Notes 1, 2, 3, and 4)6226BB–15ParameterWrite Cycle TimeAddress Setup TimeAddress Valid to End of WriteWrite Pulse WidthData Valid to End of WriteData Hold TImeWrite Low to Data High–ZWrite High to Output ActiveWrite Recovery TimeSymboltAVAVtAVWLtAVWHtWLWH,tWLEHtDVWHtWHDXtWLQZtWHQXtWHAXMin150121270—50Max——————6——6226BB–17Min170141480—50Max——————7——6226BB–20Min200151590—50Max——————7——6226BB–25Min2501717100—50Max——————8——6226BB–35Min3502020110—50Max——————8——Unitnsnsnsnsnsnsnsnsns6, 7, 86, 7, 8Notes5NOTES:1.A write occurs during the overlap of E low and W low.2.Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus con-tention conditions during read and write cycles.3.E1 and E2 are represented by E in this data sheet. E2 is of opposite polarity to E1.4.If G goes low coincident with or after W goes low, the output will remain in a high–impedance state.5.All timings are referenced from the last valid address to the first transitioning address.6.Transition is measured ± 500 mV from steady–state voltage with load of Figure 1b.7.This parameter is sampled and not 100% tested.8.At any given voltage and temperature, tWLQZ max is less than tWHQX min both for a given device and from device to device.WRITE CYCLE 1 (W Controlled See Notes 1, 2, 3, and 4)tAVAVA (ADDRESS)tAVWHE (CHIP ENABLE)tWLWHtWLEHtWHAXW (WRITE ENABLE)tAVWLD (DATA IN)tWLQZQ (DATA OUT)HIGH–ZHIGH–ZtDVWHDATA VALIDtWHQXtWHDXMOTOROLA FAST SRAMMCM6226BB5元器件交易网www.cecb2b.comWRITE CYCLE 2 (E Controlled, See Notes 1, 2, 3, and 4)6226BB–15ParameterWrite Cycle TimeAddress Setup TimeAddress Valid to End of WriteEnable to End of WriteWrite Pulse WidthData Valid to End of WriteData Hold TimeWrite Recovery TimeSymboltAVAVtAVELtAVEHtELEH,tELWHtWLEHtDVEHtEHDXtEHAXMin150121212700Max————————6226BB–17Min170141414800Max————————6226BB–20Min200151515900Max————————6226BB–25Min2501717171000Max————————6226BB–35Min3502020201100Max————————Unitnsnsnsnsnsnsnsns6, 7Notes5NOTES:1.A write occurs during the overlap of E low and W low.2.Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus con-tention conditions during read and write cycles.3.E1 and E2 are represented by E in this data sheet. E2 is of opposite polarity to E1.4.If G goes low coincident with or after W goes low, the output will remain in a high–impedance state.5.All timings are referenced from the last valid address to the first transitioning address.6.If E goes low coincident with or after W goes low, the output will remain in a high–impedance state.7.If E goes high coincident with or before W goes high, the output will remain in a high–impedance state.WRITE CYCLE 2 (E Controlled See Notes 1, 2, 3, and 4)tAVAVA (ADDRESS)tAVEHE (CHIP ENABLE)tAVELW (WRITE ENABLE)tWLEHtELWHtEHAXtELEHtDVEHD (DATA IN)DATA VALIDtEHDXQ (DATA OUT)HIGH–ZORDERING INFORMATION(Order by Full Part Number)MCM6226BBXXMotorola Memory PrefixPart NumberXXXXShipping Method (R2 = Tape and Reel, Blank = Rails)Speed (15 = 15 ns, 17 = 17 ns, 20 = 20 ns, 25 = 25 ns,35 = 35 ns)Package (XJ = 400 mil SOJ, EJ = 300 mil SOJ)Full Part Numbers —MCM6226BBXJ15MCM6226BBXJ17MCM6226BBXJ20MCM6226BBXJ25MCM6226BBXJ35MCM6226BBXJ15R2MCM6226BBXJ17R2MCM6226BBXJ20R2MCM6226BBXJ25R2MCM6226BBXJ35R2MCM6226BBEJ15MCM6226BBEJ17MCM6226BBEJ20MCM6226BBEJ25MCM6226BBEJ35MCM6226BBEJ15R2MCM6226BBEJ17R2MCM6226BBEJ20R2MCM6226BBEJ25R2MCM6226BBEJ35R2MCM6226BB6MOTOROLA FAST SRAM元器件交易网www.cecb2b.comPACKAGE DIMENSIONS32 LEAD400 MIL SOJCASE 857A–02NOTES:1.DIMENSIONING AND TOLERANCING PER ANSIY14.5M, 1982.2.CONTROLLING DIMENSION: INCH.3.TO BE DETERMINED AT PLANE -T-.4.DIMENSION A & B DO NOT INCLUDE MOLDPROTRUSION. MOLD PROTRUSION SHALL NOTEXCEED 0.15 (0.006) PER SIDE.5.DIMENSION A & B INCLUDE MOLD MISMATCH ANDARE DETERMINED AT THE PARTING LINE.DIMABCDEFGKLNPRSMILLIMETERSMINMAX20.8321.0810.0310.293.753.260.500.412.482.240.810.671.27 BSC1.140.0. BSC1.140.7611.3011.059.529.271.010.77INCHESMINMAX0.8200.8300.3950.4050.1280.1480.0160.0200.0880.0980.0260.0320.050 BSC0.0350.0450.025 BSC0.0300.0450.4350.4450.3650.3750.0300.0403217FN32 PL0.17 (0.007)DETAIL ZSTBSAS116D0.17 (0.007)S32 PLSTBSASSNOTE 3-A-LGP0.17 (0.007)-B-0.10 (0.004)TABSER0.25 (0.010)SCKDETAIL Z-T-SEATINGPLANESRADIUSTASBSNOTE 3MOTOROLA FAST SRAMMCM6226BB7元器件交易网www.cecb2b.com32 LEAD300 MIL SOJCASE 857–02F32 PL0.17 (0.007)3211716SASMNOTE 4–A–LG–X–KDETAIL ZNOTE 3D32 PL0.17 (0.007)P0.17 (0.007)SB-B-NOTE 5SSASNOTES:1.DIMENSIONING AND TOLERANCING PER ANSIY14.5M, 1982.2.CONTROLLING DIMENSION: INCH.3.DATUM PLANE -X- LOCATED AT TOP OF MOLDPARTING LINE AND COINCIDENT WITH TOP OFLEAD, WHERE LEAD EXITS BODY.4.TO BE DETERMINED AT PLANE -X-.5.TO BE DETERMINED AT PLANE -T-.6.DIMENSION A & B DO NOT INCLUDE MOLDPROTRUSION. MOLD PROTRUSION SHALL NOTEXCEED 0.15 (0.006) PER SIDE.7.857-01 IS OBSOLETE, NEW STANDARD 857-02.DIMABCDEFGKLNPRSMILLIMETERSMINMAX20.8321.087.747.503.753.260.500.412.482.240.810.671.27 BSC1.140.0. BSC1.140.768.8.386.866.601.010.77INCHESMINMAX0.8200.8300.2950.3050.1280.1480.0160.0200.0880.0980.0260.0320.050 BSC0.0350.0450.025 BSC0.0300.0450.3300.3400.2600.2700.0300.040ECR0.25 (0.010)S0.10 (0.004)-T-SEATINGPLANESRADIUSBSNOTE 5Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regardingthe suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, andspecifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motoroladata sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights ofothers. 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Motorola, Inc. is an EqualOpportunity/Affirmative Action Employer.Mfax is a trademark of Motorola, Inc.How to reach us:USA/EUROPE/Locations Not Listed: Motorola Literature Distribution;P.O. Box 05, Denver, Colorado 80217. 303–675–2140 or 1–800–441–2447JAPAN: Nippon Motorola Ltd.: SPD, Strategic Planning Office, 4–32–1,Nishi–Gotanda, Shinagawa–ku, Tokyo 141, Japan. 81–3–87–8488Mfax™: RMFAX0@email.sps.mot.com– TOUCHTONE 602–244–6609ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park,– US & Canada ONLY 1–800–774–184851 Ting Kok Road, Tai Po, N.T., . 852–26629298INTERNET: http://motorola.com/spsMCM6226BB8◊MCM6226BB/DMOTOROLA FAST SRAM
