IC42S16100Document Title512K x 16 Bit x 2 Banks (16-MBIT) SDRAM
Revision HistoryRevision No0A0B0C0D
HistoryInitial Draft
revise for typo on page 17Add Pb-free packageAdd speed grade -5nsObselte speed grade -8ns
Draft DateRemarkAugust 28,2001January 10,2002December 02,2003June 25,2004
The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications andproducts. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.
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IC42S16100512K x 16 Bits x 2 Banks (16-MBIT)SYNCHRONOUS DYNAMIC RAM
FEATURES
•Clock frequency: 200, 166, 143 MHz
•Fully synchronous; all signals referenced to apositive clock edge
•Two banks can be operated simultaneously andindependently
•Dual internal bank controlled by A11 (bank select)•Single 3.3V power supply•LVTTL interface
•Programmable burst length– (1, 2, 4, 8, full page)
•Programmable burst sequence:Sequential/Interleave•Auto refresh, self refresh
•4096 refresh cycles every ms
•Random column address every clock cycle•Programmable CAS latency (2, 3 clocks)•Burst read/write and burst read/single writeoperations capability
•Burst termination by burst stop and prechargecommand
•Byte controlled by LDQM and UDQM•Package 400mil 50-pin TSOP-2•Pb(lead)-free package is available
DESCRIPTION
ICSI's 16Mb Synchronous DRAM IC42S16100 is organized
as a 524,288-word x 16-bit x 2-bank for improvedperformance. The synchronous DRAMs achieve high-speeddata transfer using pipeline architecture. All inputs andoutputs signals refer to the rising edge of the clock input.
PIN CONFIGURATIONS
50-Pin TSOP-2
VCCI/O0I/O1GNDQI/O2I/O3VCCQI/O4I/O5GNDQI/O6I/O7 VCCQLDQMWECASRASCSA11A10A0A1A2A3VCC1234567101112131415161718192021222324255049484744434241403938373635343332313029282726GNDI/O15I/O14GNDQI/O13I/O12VCCQI/O11I/O10GNDQI/O9I/O8VCCQNCUDQMCLKCKENCA9A8A7A6A5A4GNDPIN DESCRIPTIONS
A0-A11A0-A10A11A0-A7I/O0 to I/O15CLKCKECSRAS
Address InputRow Address InputBank Select AddressColumn Address InputData I/O
System Clock InputClock EnableChip Select
Row Address Strobe Command
CASWELDQMUDQMVccGNDVccQGNDQNC
Column Address Strobe CommandWrite Enable
Lower Bye, Input/Output MaskUpper Bye, Input/Output MaskPowerGround
Power Supply for I/O PinGround for I/O PinNo Connection
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errorswhich may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
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IC42S16100PIN FUNCTIONS
Pin No.20 to 2427 to 32SymbolA0-A10TypeInput PinFunction (In Detail)A0 to A10 are address inputs. A0-A10 are used as row address inputs during activecommand input and A0-A7 as column address inputs during read or write commandinput. A10 is also used to determine the precharge mode during other commands. IfA10 is LOW during precharge command, the bank selected by A11 is precharged,but if A10 is HIGH, both banks will be precharged.When A10 is HIGH in read or write command cycle, the precharge starts automati-cally after the burst access.These signals become part of the OP CODE during mode register set commandinput.A11 is the bank selection signal. When A11 is LOW, bank 0 is selected and whenhigh, bank 1 is selected. This signal becomes part of the OP CODE during moderegister set command input.CAS, in conjunction with the RAS and WE, forms the device command. See the\"Command Truth Table\" item for details on device commands.The CKE input determines whether the CLK input is enabled within the device.When is CKE HIGH, the next rising edge of the CLK signal will be valid, and whenLOW, invalid. When CKE is LOW, the device will be in either the power-down mode,the clock suspend mode, or the self refresh mode. The CKE is an asynchronous input.CLK is the master clock input for this device. Except for CKE, all inputs to thisdevice are acquired in synchronization with the rising edge of this pin.The CS input determines whether command input is enabled within the device.Command input is enabled when CS is LOW, and disabled with CS is HIGH. Thedevice remains in the previous state when CS is HIGH.I/O0 to I/O15 are I/O pins. I/O through these pins can be controlled in byte unitsusing the LDQM and UDQM pins.LDQM and UDQM control the lower and upper bytes of the I/O buffers. In readmode, LDQM and UDQM control the output buffer. When LDQM or UDQM is LOW,the corresponding buffer byte is enabled, and when HIGH, disabled. The outputs goto the HIGH impedance state when LDQM/UDQM is HIGH. This function corre-sponds to OE in conventional DRAMs. In write mode, LDQM and UDQM control theinput buffer. When LDQM or UDQM is LOW, the corresponding buffer byte isenabled, and data can be written to the device. When LDQM or UDQM is HIGH,input data is masked and cannot be written to the device.RAS, in conjunction with CAS and WE, forms the device command. See the\"Command Truth Table\" item for details on device commands. WE, in conjunction with RAS and CAS, forms the device command. See the\"Command Truth Table\" item for details on device commands.VCCQ is the output buffer power supply.VCC is the device internal power supply.GNDQ is the output buffer ground.GND is the device internal ground.19A11Input Pin1634CASCKEInput PinInput Pin3518CLKCSInput PinInput Pin2, 3, 5, 6, 8, 9, 11I/O0 to12, 39, 40, 42, 43,I/O15, 46, 48, 4914, 36LDQM,UDQMI/O PinInput Pin17157, 13, 38, 441, 2, 10, 41, 4726, 50RAS WEVCCQVCCGNDQGNDInput PinInput PinPower Supply PinPower Supply PinPower Supply PinPower Supply PinIntegrated Circuit Solution Inc.
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IC42S16100FUNCTIONAL BLOCK DIAGRAM
COMMANDDECODER&CLOCKGENERATORROW DECODERCLKCKECSRASCASWEA11MODEREGISTER1111ROWADDRESSBUFFER2048MEMORY CELLARRAY11BANK 0DQMSENSE AMP I/O GATEA10A9A8A7A6A5A4A3A2A1A0REFRESHCONTROLLER SELFREFRESHCONTROLLERCOLUMNADDRESS BUFFERBURST COUNTERCOLUMNADDRESS LATCHDATA INBUFFER1616 256COLUMN DECODER8I/O 0-158 256SENSE AMP I/O GATEREFRESHCOUNTERDATA OUTBUFFER1616ROW DECODERMULTIPLEXER11ROWADDRESSLATCH11ROWADDRESSBUFFER2048MEMORY CELLARRAYVcc/VccQGND/GNDQBANK 111S16BLK.eps4Integrated Circuit Solution Inc.
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IC42S16100ABSOLUTE MAXIMUM RATINGS(1)
SymbolVCC MAXVCCQ MAX
VINVOUTPD MAXICSTOPRTSTG
Parameters
Maximum Supply Voltage
Maximum Supply Voltage for Output BufferInput VoltageOutput Voltage
Allowable Power DissipationOutput Shorted CurrentOperating TemperatureStorage Temperature
Rating–1.0 to +4.6–1.0 to +4.6–1.0 to +4.6–1.0 to +4.6
1500 to +70–55 to +150
UnitVVVVWmA°C°C
DC RECOMMENDED OPERATING CONDITIONS(2) (At TA = 0 to +70°C)
SymbolVCC, VCCQ
VIHVIL
ParameterSupply Voltage
Input High Voltage(3)Input Low Voltage(4)
Min.3.02.0-0.3
Typ.3.3——
Max.3.6VDD + 0.3+0.8
UnitVVV
CAPACITANCE CHARACTERISTICS(1,2) (At TA = 0 to +25°C, Vcc = VccQ = 3.3 ± 0.3V, f = 1 MHz)
SymbolCIN1CIN2CI/O
Parameter
Input Capacitance: A0-A11
Input Capacitance: (CLK, CKE, CS, RAS, CAS, WE, LDQM, UDQM)Data Input/Output Capacitance: I/O0-I/O15
Typ.———
Max.445
UnitpFpFpF
Notes:
1.Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated inthe operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extendedperiods may affect reliability.
2.All voltages are referenced to GND.
3.VIH (max) = VCCQ + 2.0V with a pulse width ≤ 3 ns.
4.VIL (min) = GND – 2.0V with a pulse < 3 ns and -1.5V with a pulse < 5ns.
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IC42S16100DC ELECTRICAL CHARACTERISTICS (Recommended Operation Conditions unless otherwise noted.)
SymbolParameterIILIOLVOHVOLICC1
Input Leakage CurrentOutput Leakage CurrentOutput High Voltage LevelOutput Low Voltage LevelOperating Current(1,2)
Test Condition
0V ≤ VIN ≤ VCC, with pins other thanthe tested pin at 0VOutput is disabled0V ≤ VOUT ≤ VCCIOUT = –2 mAIOUT = +2 mAOne Bank Operation,Burst Length=1tRC ≥ tRC (min.)IOUT = 0mA
CKE ≤ VIL (MAX)CKE ≥ VIH (MIN)
CAS latency = 3
-5-6-7————-5-6-7-5-6-7—Speed
Min.–5–102.4——————5—6—7———————
Max.510—0.41501451402504015014013010090801
UnitµAµAVVmAmAmAmAmAmAmAmAmAmAmAmAmAmA
ICC2ICC3
Precharge Standby Current(In Power-Down Mode)Active Standby Current(In Non Power-Down Mode)Operating Current(In Burst Mode)(1)Auto-Refresh Current
tCK = tCK (MIN)tCK = tCK (MIN)
ICC4
tCK = tCK (MIN)IOUT = 0mAtRC = tRC (MIN)
ICC5
ICC6Self-Refresh CurrentCKE ≤ 0.2V
Notes:
1. These are the values at the minimum cycle time. Since the currents are transient, these values decrease as the cycle time
increases. Also note that a bypass capacitor of at least 0.01 µF should be inserted between Vcc and GND for eachmemory chip to suppress power supply voltage noise (voltage drops) due to these transient currents.2. Icc1 and Icc4 depend on the output load.
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IC42S16100AC CHARACTERISTICS(1,2,3)
-5SymboltCK3tCK2tAC3tAC2tCHItCLtOHtLZtHZ3tHZ2tDStDHtAStAHtCKStCKHtCKAtCStCHtRCtRAStRPtRCDtRRDtDPLtDALtTtREFParameterClock Cycle TimeAccess Time From CLK(4)CLK HIGH Level WidthCLK LOW Level WidthOutput Data Hold TimeOutput LOW Impedance TimeOutput HIGH Impedance Time(5)CAS Latency = 3CAS Latency = 2CAS Latency = 3CAS Latency = 2Min.Max.Min.5—7——4.5—52—2—2—0——4.5—52—1—2—1—2—1—1CLK+3—2—1—50—30100,00015—15—10—2CLK—2CLK+tRP—1—10-6Max.Min.6—8——5.5—62—2—2—0——5.5—62—1—2—1—2—1—1CLK+3—2—1—60—36100,00018—18—12—2CLK—2CLK+tRP—1—10-7MaxUnitsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsms7—8.6——6—62.5—2.5—2—0——6—62—1—2—1—2—1—1CLK+3—2—1—70—42100,00021—21—14—2CLK—2CLK+tRP—1—10CAS Latency = 3CAS Latency = 2Input Data Setup TimeInput Data Hold TimeAddress Setup TimeAddress Hold TimeCKE Setup TimeCKE Hold TimeCKE to CLK Recovery Delay TimeCommand Setup Time (CS, RAS, CAS, WE, DQM)Command Hold Time (CS, RAS, CAS, WE, DQM)Command Period (REF to REF / ACT to ACT)Command Period (ACT to PRE)Command Period (PRE to ACT)Active Command To Read / Write Command Delay TimeCommand Period (ACT [0] to ACT[1])Input Data To PrechargeCommand Delay timeInput Data To Active / RefreshCommand Delay time (During Auto-Precharge)Transition TimeRefresh Cycle Time (4096)Notes:
1.When power is first applied, memory operation should be started 100 µs after Vcc and VccQ reach their stipulated
voltages. Also note that the power-on sequence must be executed before starting memory operation.2.Measured with tT = 1 ns.
3.The reference level is 1.4 V when measuring input signal timing. Rise and fall times are measured between VIH (min.) and
VIL (max.).
4.Access time is measured at 1.4V with the load shown in the figure below.
5.The time tHZ (max.) is defined as the time required for the output voltage to transition by ± 200 mV from VOH (min.) or VOL
(max.) when the output is in the high impedance state.
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IC42S16100OPERATING FREQUENCY / LATENCY RELATIONSHIPS
SymbolParameter——tCACtRCDtRACtRCtRAStRPtRRDtCCDtDPLtDALtRBDtWBDtRQLtWDLtPQLtQMDtDMDtMCD
Clock Cycle TimeOperating FrequencyCAS Latency
Active Command To Read/Write Command Delay TimeRAS Latency (tRCD + tCAC)
Command Period (REF to REF / ACT to ACT)Command Period (ACT to PRE)Command Period (PRE to ACT)
Command Period (ACT[0] to ACT [1])Column Command Delay Time(READ, READA, WRIT, WRITA)
Input Data To Precharge Command Delay TimeInput Data To Active/Refresh Command Delay Time(During Auto-Precharge)
Burst Stop Command To Output in HIGH-Z Delay Time(Read)
Burst Stop Command To Input in Invalid Delay Time(Write)
Precharge Command To Output in HIGH-Z Delay Time(Read)
Precharge Command To Input in Invalid Delay Time(Write)
Last Output To Auto-Precharge Start Time (Read)DQM To Output Delay Time (Read)DQM To Input Delay Time (Write)
Mode Register Set To Command Delay Time
-55200336106321253030–2202
-66166336106321253030–2202
-77143336106321253030–2202
UnitsnsMHzcyclecyclecyclecyclecyclecyclecyclecyclecyclecyclecyclecyclecyclecyclecyclecyclecyclecycle
AC TEST CONDITIONS (Input/Output Reference Level: 1.4V)InputtCHI2.4VtCKtCLCLK1.4V0.4VtCS2.4VtCHINPUT1.4V0.4VtOHOUTPUT1.4VtAC1.4VOutput LoadI/O ZO = 50Ω50 Ω+1.4V 30 pF8Integrated Circuit Solution Inc.
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IC42S16100COMMANDS
Active CommandCLKCKEHIGHCSRASCASWEA0-A9A10ROWRead CommandCLKCKEHIGHCSRASCASWEA0-A9A10NO PRECHARGEBANK 1COLUMN(1)AUTO PRECHARGEROWBANK 1A11BANK 0A11BANK 0Write CommandCLKCKEHIGHCSRASCASWEA0-A9A10NO PRECHARGEBANK 1COLUMN(1)AUTO PRECHARGEPrecharge CommandCLKCKEHIGHCSRASCASWEA0-A9BANK 0 AND BANK 1A10BANK 0 OR BANK 1BANK 1A11BANK 0A11BANK 0No-Operation CommandCLKCKECSRASCASWEA0-A9A10A11HIGHDevice Deselect CommandCLKCKECSRASCASWEA0-A9A10A11HIGHNotes:1.A8-A9 = Don't Care.Don’t CareIntegrated Circuit Solution Inc.
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IC42S16100COMMANDS (cont.)
Mode Register Set CommandCLKCKECSRASCASWEA0-A9A10A11OP-CODEHIGHAuto-Refresh CommandCLKCKECSRASCASWEA0-A9A10A11HIGHOP-CODEOP-CODESelf-Refresh CommandCLKCKECSRASCASWEA0-A9A10A11Power Down CommandCLKCKECSRASCASWEA0-A9A10A11ALL BANKS IDLENOPNOPNOPNOP Clock Suspend CommandCLKCKECSRASCASWEA0-A9A10A11BANK(S) ACTIVEBurst Stop CommandCLKCKEHIGHNOPCSRASCASWEA0-A9A10A11NOPNOPNOP Don’t Care10Integrated Circuit Solution Inc.
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IC42S16100Mode Register Set Command
(CS, RAS, CAS, WE = LOW)
The IC42S16100 product incorporates a register that definesthe device operating mode. This command functions as adata input pin that loads this register from the pins A0 toA11. When power is first applied, the stipulated power-onsequence should be executed and then the IC42S16100should be initialized by executing a mode register setcommand.
Note that the mode register set command can be executedonly when both banks are in the idle state (i.e. deactivated).Another command cannot be executed after a moderegister set command until after the passage of the periodtMCD, which is the period required for mode register setcommand execution.
When the A10 pin is HIGH, this command functions as aread with auto-precharge command. After the burst readcompletes, the bank selected by pin A11 is precharged.When the A10 pin is LOW, the bank selected by the A11 pinremains in the activated state after the burst read completes.
Write Command
(CS, CAS, WE = LOW, RAS = HIGH)
When burst write mode has been selected with the moderegister set command, this command selects the bankspecified by the A11 pin and starts a burst write operationat the start address specified by pins A0 to A9. This firstdata must be input to the I/O pins in the cycle in which thiscommand.
The selected bank must be activated before executing thiscommand.
When A10 pin is HIGH, this command functions as a writewith auto-precharge command. After the burst writecompletes, the bank selected by pin A11 is precharged.When the A10 pin is low, the bank selected by the A11 pinremains in the activated state after the burst write completes.After the input of the last burst write data, the applicationmust wait for the write recovery period (tDPL, tDAL) to elapseaccording to CAS latency.
Active Command
(CS, RAS = LOW, CAS, WE= HIGH)
The IC42S16100 includes two banks of 4096 rows each.This command selects one of the two banks according tothe A11 pin and activates the row selected by the pins A0to A10.
This command corresponds to the fall of the RAS signalfrom HIGH to LOW in conventional DRAMs.
Precharge Command
(CS, RAS, WE = LOW, CAS = HIGH)
This command starts precharging the bank selected bypins A10 and A11. When A10 is HIGH, both banks areprecharged at the same time. When A10 is LOW, the bankselected by A11 is precharged. After executing thiscommand, the next command for the selected bank(s) isexecuted after passage of the period tRP, which is theperiod required for bank precharging.
This command corresponds to the RAS signal from LOWto HIGH in conventional DRAMs
Auto-Refresh Command
(CS, RAS, CAS = LOW, WE, CKE = HIGH)
This command executes the auto-refresh operation. Therow address and bank to be refreshed are automaticallygenerated during this operation.
Both banks must be placed in the idle state before executingthis command.
The stipulated period (tRC) is required for a single refreshoperation, and no other commands can be executedduring this period.
The device goes to the idle state after the internal refreshoperation completes.
This command must be executed at least 4096 times every ms.
This command corresponds to CBR auto-refresh inconventional DRAMs.
Read Command
(CS, CAS = LOW, RAS, WE = HIGH)
This command selects the bank specified by the A11 pinand starts a burst read operation at the start addressspecified by pins A0 to A9. Data is output following CASlatency.
The selected bank must be activated before executing thiscommand.
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IC42S16100Self-Refresh Command
(CS, RAS, CAS, CKE = LOW, WE = HIGH)
This command executes the self-refresh operation. Therow address to be refreshed, the bank, and the refreshinterval are generated automatically internally during thisoperation. The self-refresh operation is started by droppingthe CKE pin from HIGH to LOW. The self-refresh operationcontinues as long as the CKE pin remains LOW and thereis no need for external control of any other pins. The self-refresh operation is terminated by raising the CKE pin fromLOW to HIGH. The next command cannot be executeduntil the device internal recovery period (tRC) has elapsed.After the self-refresh, since it is impossible to determine theaddress of the last row to be refreshed, an auto-refreshshould immediately be performed for all addresses (4096cycles).
Both banks must be placed in the idle state before executingthis command.
Power-Down Command
(CKE = LOW)
When both banks are in the idle (inactive) state, or when atleast one of the banks is not in the idle (inactive) state, thiscommand can be used to suppress device power dissipationby reducing device internal operations to the absoluteminimum. Power-down mode is started by dropping theCKE pin from HIGH to LOW. Power-down mode continuesas long as the CKE pin is held low. All pins other than theCKE pin are invalid and none of the other commands canbe executed in this mode. The power-down operation isterminated by raising the CKE pin from LOW to HIGH. Thenext command cannot be executed until the recoveryperiod (tCKA) has elapsed.
Since this command differs from the self-refresh commanddescribed above in that the refresh operation is notperformed automatically internally, the refresh operationmust be performed within the refresh period (tREF). Thusthe maximum time that power-down mode can be held isjust under the refresh cycle time.
Burst Stop Command
(CS, WE, = LOW, RAS, CAS = HIGH)
The command forcibly terminates burst read and writeoperations. When this command is executed during a burstread operation, data output stops after the CAS latencyperiod has elapsed.
Clock Suspend
(CKE = LOW)
This command can be used to stop the device internalclock temporarily during a read or write cycle. Clocksuspend mode is started by dropping the CKE pin fromHIGH to LOW. Clock suspend mode continues as long asthe CKE pin is held LOW. All input pins other than the CKEpin are invalid and none of the other commands can beexecuted in this mode. Also note that the device internalstate is maintained. Clock suspend mode is terminated byraising the CKE pin from LOW to HIGH, at which pointdevice operation restarts. The next command cannot beexecuted until the recovery period (tCKA) has elapsed.Since this command differs from the self-refresh commanddescribed above in that the refresh operation is notperformed automatically internally, the refresh operationmust be performed within the refresh period (tREF). Thusthe maximum time that clock suspend mode can be heldis just under the refresh cycle time.
No Operation
(CS, = LOW, RAS, CAS, WE = HIGH)This command has no effect on the device.
Device Deselect Command
(CS = HIGH)
This command does not select the device for an object ofoperation. In other words, it performs no operation withrespect to the device.
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IC42S16100COMMAND TRUTH TABLE(1,2)
SymbolMRSREFSREFPREPALLACTWRITWRITAREADREADABSTNOPDESLSBYENBMASKCommandMode Register Set(3,4)Auto-Refresh(5)Self-Refresh(5,6)Precharge Selected BankPrecharge Both BanksBank Activate(7)WriteWrite With Auto-Precharge(8)Read(8)Read With Auto-Precharge(8)Burst Stop(9)No OperationDevice DeselectClock Suspend / Standby ModeData Write / Output EnableData Mask / Output Disable CKEn-1nHHHHHHHHHHHHHLHHXHLXXXXXXXXXXXXXCSRASCASWEDQMA11A10LLLLLLLLLLLLHXXXLLLLLLHHHHHHXXXXLLLHHHLLLLHHXXXXLHHLLHLLHHLHXXXXXXXXXXXXXXXXXXLHXXBSXBSBSBSBSBSXXXXXXA9-A0I/OnXHIGH-ZHIGH-ZXXXXXXXXXXXActiveHIGH-ZOPCODEXXXXLXHXRowRowLColumn(18)HColumn(18)LColumn(18)H Column(18)XXXXXXXXXXXXDQM TRUTH TABLE(1,2)
SymbolENBMASKENBUENBLMASKUMASKLCommandData Write / Output EnableData Mask / Output DisableUpper Byte Data Write / Output EnableLower Byte Data Write / Output EnableUpper Byte Data Mask / Output DisableLower Byte Data Mask / Output Disable CKEn-1nHHHHHHXXXXXX DQMUPPERLOWERLHLXHXLHXLXH CKE TRUTH TABLE(1,2)
SymbolSPND——REFSELFSELFXPDWN—CommandStart Clock Suspend ModeClock SuspendTerminate Clock Suspend ModeAuto-RefreshStart Self-Refresh ModeTerminate Self-Refresh ModeStart Power-Down ModeTerminate Power-Down ModeCurrent StateActiveOther StatesClock SuspendIdleIdleSelf-RefreshIdlePower-Down CKEn-1nHLLHHLLHHLLLHHLHHLLHCSRASCASWEA11A10A9-A0XXXLLLHLHXXXXLLHXHXXXXXLLHXHXXXXXHHHXHXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXIntegrated Circuit Solution Inc.
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IC42S16100OPERATION COMMAND TABLE(1,2)
Current StateCommandIdleDESLNOPBSTREAD / READAWRIT/WRITAACTPRE/PALLREF/SELFMRSDESLNOPBSTREAD/READAWRIT/WRITAACTPRE/PALLREF/SELFMRSDESLNOPBSTREAD/READAWRIT/WRITAACTPRE/PALLREF/SELFMRSDESLNOPBSTREAD/READAWRIT/WRITAACTPRE/PALLREF/SELFMRSDESLNOPBSTREAD/READAWRIT/WRITAACTPRE/PALLREF/SELFMRSOperationNo Operation or Power-Down(12)No Operation or Power-Down(12)No Operation or Power-DownIllegalIllegalRow ActiveNo OperationAuto-Refresh or Self-Refresh(13)Mode Register SetNo OperationNo OperationNo OperationRead Start(17)Write Start(17)Illegal(10)Precharge(15)IllegalIllegalBurst Read Continues, Row Active When DoneBurst Read Continues, Row Active When DoneBurst Interrupted, Row Active After InterruptBurst Interrupted, Read Restart After Interrupt(16)Burst Interrupted Write Start After Interrupt(11,16)Illegal(10)Burst Read Interrupted, Precharge After InterruptIllegalIllegalBurst Write Continues, Write Recovery When DoneBurst Write Continues, Write Recovery When DoneBurst Write Interrupted, Row Active After InterruptBurst Write Interrupted, Read Start After Interrupt(11,16)Burst Write Interrupted, Write Restart After Interrupt(16)Illegal(10)Burst Write Interrupted, Precharge After InterruptIllegalIllegalBurst Read Continues, Precharge When DoneBurst Read Continues, Precharge When DoneIllegalIllegalIllegalIllegal(10)Illegal(10)IllegalIllegalCSRASCASWEA11A10A9-A0HLLLLLLLLHLLLLLLLLHLLLLLLLLHLLLLLLLLHLLLLLLLLXHHHHLLLLXHHHHLLLLXHHHHLLLLXHHHHLLLLXHHHHLLLLXHHLLHHLLXHHLLHHLLXHHLLHHLLXHHLLHHLLXHHLLHHLLXHLHLHLHLXHLHLHLHLXHLHLHLHLXHLHLHLHLXHLHLHLHLXXXVVVVXXXXVVVVXXXXVVVVXXXXVVVVXXXXVVVVXXXXXXXVV(18)VV(18)VV(18)VXXXOP CODEXXXXXXVV(18)VV(18)VV(18)VXXXOP CODEXXXXXXVV(18)VV(18)VV(18)VXXXOP CODEXXXXXXVV(18)VV(18)VV(18)VXXXOP CODEXXXXXXVV(18)VV(18)VV(18)VXXXOP CODERow ActiveReadWriteRead WithAuto-Precharge14Integrated Circuit Solution Inc.
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IC42S16100OPERATION COMMAND TABLE(1,2)
Current StateCommandWrite WithDESLAuto-PrechargeNOPBSTREAD/READAWRIT/WRITAACTPRE/PALLREF/SELFMRSRow PrechargeDESLNOPBSTREAD/READAWRIT/WRITAACTPRE/PALLREF/SELFMRSImmediatelyDESLFollowingNOPRow ActiveBSTREAD/READAWRIT/WRITAACTPRE/PALLREF/SELFMRSWriteDESLRecoveryNOPBSTREAD/READAWRIT/WRITAACTPRE/PALLREF/SELFMRSOperationBurst Write Continues, Write Recovery And PrechargeWhen DoneBurst Write Continues, Write Recovery And PrechargeIllegalIllegalIllegalIllegal(10)Illegal(10)IllegalIllegalNo Operation, Idle State After tRP Has ElapsedNo Operation, Idle State After tRP Has ElapsedNo Operation, Idle State After tRP Has ElapsedIllegal(10)Illegal(10)Illegal(10)No Operation, Idle State After tRP Has Elapsed(10)IllegalIllegalNo Operation, Row Active After tRCD Has ElapsedNo Operation, Row Active After tRCD Has ElapsedNo Operation, Row Active After tRCD Has ElapsedIllegal(10)Illegal(10)Illegal(10,14)Illegal(10)IllegalIllegalNo Operation, Row Active After tDPL Has ElapsedNo Operation, Row Active After tDPL Has ElapsedNo Operation, Row Active After tDPL Has ElapsedRead StartWrite RestartIllegal(10)Illegal(10)IllegalIllegalCSRASCASWEA11A10A9-A0HLLLLLLLLHLLLLLLLLHLLLLLLLLHLLLLLLLLXHHHHLLLLXHHHHLLLLXHHHHLLLLXHHHHLLLLXHHLLHHLLXHHLLHHLLXHHLLHHLLXHHLLHHLLXHLHLHLHLXHLHLHLHLXHLHLHLHLXHLHLHLHLXXXVVVVXXXXVVVVXXXXVVVVXXXXVVVVXXXXXXXVV(18)VV(18)VV(18)VXXXOPCODEXXXXXXVV(18)VV(18)VV(18)VXXXOP CODEXXXXXXVV(18)VV(18)VV(18)VXXXOP CODEXXXXXXVV(18)VV(18)VV(18)VXXXOP CODEIntegrated Circuit Solution Inc.
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IC42S16100OPERATION COMMAND TABLE(1,2)
Current StateCommandWrite RecoveryDESLWith Auto-NOPPrechargeBSTREAD/READAWRIT/WRITAACTPRE/PALLREF/SELFMRSRefreshDESLNOPBSTREAD/READAWRIT/WRITAACTPRE/PALLREF/SELFMRSMode RegisterDESLSetNOPBSTREAD/READAWRIT/WRITAACTPRE/PALLREF/SELFMRSOperationNo Operation, Idle State After tDAL Has ElapsedNo Operation, Idle State After tDAL Has ElapsedNo Operation, Idle State After tDAL Has ElapsedIllegal(10)Illegal(10)Illegal(10)Illegal(10)IllegalIllegalNo Operation, Idle State After tRP Has ElapsedNo Operation, Idle State After tRP Has ElapsedNo Operation, Idle State After tRP Has ElapsedIllegalIllegalIllegalIllegalIllegalIllegalNo Operation, Idle State After tMCD Has ElapsedNo Operation, Idle State After tMCD Has ElapsedNo Operation, Idle State After tMCD Has ElapsedIllegalIllegalIllegalIllegalIllegalIllegalCSRASCASWEA11A10A9-A0HLLLLLLLLHLLLLLLLLHLLLLLLLLXHHHHLLLLXHHHHLLLLXHHHHLLLLXHHLLHHLLXHHLLHHLLXHHLLHHLLXHLHLHLHLXHLHLHLHLXHLHLHLHLXXXVVVVXXXXVVVVXXXXVVVVXXXXXXXVV(18)VV(18)VV(18)VXXXOP CODEXXXXXXVV(18)VV(18)VV(18)VXXXOP CODEXXXXXXVV(18)VV(18)VV(18)VXXXOP CODENotes:
1.H: HIGH level input, L: LOW level input, X: HIGH or LOW level input, V: Valid data input2.All input signals are latched on the rising edge of the CLK signal.3.Both banks must be placed in the inactive (idle) state in advance.
4.The state of the A0 to A11 pins is loaded into the mode register as an OP code.
5.The row address is generated automatically internally at this time. The I/O pin and the address pin data is ignored.6.During a self-refresh operation, all pin data (states) other than CKE is ignored.7.The selected bank must be placed in the inactive (idle) state in advance.8.The selected bank must be placed in the active state in advance.9.This command is valid only when the burst length set to full page.
10.This is possible depending on the state of the bank selected by the A11 pin.11.Time to switch internal busses is required.
12.The IC42S16100 can be switched to power-down mode by dropping the CKE pin LOW when both banks in the idle state.
Input pins other than CKE are ignored at this time.
13.The IC42S16100 can be switched to self-refresh mode by dropping the CKE pin LOW when both banks in the idle state.
Input pins other than CKE are ignored at this time.14.Possible if tRRD is satisfied.15.Illegal if tRAS is not satisfied.
16.The conditions for burst interruption must be observed. Also note that the IC42S16100 will enter the precharged state
immediately after the burst operation completes if auto-precharge is selected.
17.Command input becomes possible after the period tRCD has elapsed. Also note that the IC42S16100 will enter the
precharged state immediately after the burst operation completes if auto-precharge is selected.18. A8,A9 = don't care.
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IC42S16100CKE RELATED COMMAND TRUTH TABLE(1)
Current StateSelf-RefreshOperationUndefinedSelf-Refresh Recovery(2)Self-Refresh Recovery(2)Illegal(2)Illegal(2)Self-RefreshIdle State After tRC Has ElapsedIdle State After tRC Has ElapsedIllegalIllegalPower-Down on the Next CyclePower-Down on the Next CycleIllegalIllegalClock Suspend Termination on the Next Cycle (2)Clock SuspendUndefinedPower-Down Mode Termination, Idle AfterThat Termination(2)Power-Down ModeNo OperationSee the Operation Command TableBank Active Or PrechargeAuto-RefreshMode Register SetSee the Operation Command TableSee the Operation Command TableSee the Operation Command TableSelf-Refresh(3)See the Operation Command TablePower-Down Mode(3)See the Operation Command TableClock Suspend on the Next Cycle(4)Clock Suspend Termination on the Next CycleClock Suspend Termination on the Next Cycle CKEn-1nHLLLLLHHHHHHHHLLHLLHHHHHHHHHHLHHLLXHHHHLHHHHLLLLHLXHLHHHHHLLLLLXHLHLCSRASCASWEA11A10A9-A0XHLLLXHLLLHLLLXXXXXHLLLLHLLLLXXXXXXXHHLXXHHLXHHLXXXXXXHLLLXHLLLXXXXXXXHLXXXHLXXHLXXXXXXXXHLLXXHLLXXXXXXXXXXXXXXXXXXXXXXXXXXXHLXXXHLXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXOP CODEXXXXOP CODEXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXSelf-Refresh RecoveryPower-DownBoth Banks IdleOther StatesNotes:
1.H: HIGH level input, L: LOW level input, X: HIGH or LOW level input
2.The CLK pin and the other input are reactivated asynchronously by the transition of the CKE level from LOW to HIGH. The
minimum setup time (tCKA) required before all commands other than mode termination must be satisfied.
3.Both banks must be set to the inactive (idle) state in advance to switch to power-down mode or self-refresh mode.4.The input must be command defined in the operation command table.
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IC42S16100TWO BANKS OPERATION COMMAND TRUTH TABLE(1,2)
OperationDESLNOPBST Previous State Next StateCSRASCASWEA11A10A9-A0BANK 0BANK 1BANK 0BANK 1HLLXHHXHHXHLXXXXXXXXXAnyAnyR/W/AII/AI/AI/AR/WI/AR/WR/W/AAR/W/AAAnyAnyI/AI/AR/W/AIR/W/AAR/W/AAI/AR/WI/AR/WAnyAnyAII/AI/AI/AAI/AARPRPRRAnyAnyI/AI/AAIRPRPRRI/AAI/AAREAD/READALHLHHHHHLLLLHHHHLLLLHLXXHHLLXHHLLHHLLCA(3)CA(3)CA(3)CA(3)CA(3)CA(3)CA(3)CA(3)
WRIT/WRITALHLLACTPRE/PALLLLLLHHHLREFMRSLLLLLLHLHCA(3)HCA(3)LCA(3)LCA(3)HCA(3)HCA(3)LCA(3)LCA(3)RARARARAHXHXLXLXLXLXXXOPCODEI/AR/W/AR/WAI/AR/W/AR/WAR/W/AI/AAR/WR/W/AI/AAR/WAnyIIAnyR/W/A/II/AI/AR/W/A/II/AR/W/A/IR/W/A/II/AR/W/A/II/AI/AR/W/A/IIIIII/AWPAWPI/AWAWWPI/AWPAWI/AWAAnyAAAnyIIIII/AIR/W/A/IIII/AIR/W/A/IIIIINotes:
1.H: HIGH level input, L: LOW level input, X: HIGH or LOW level input, RA: Row Address, CA: Column
Address
2.The device state symbols are interpreted as follows:IIdle (inactive state)ARow Active StateRReadWWriteRPRead With Auto-PrechargeWPWrite With Auto-PrechargeAnyAny State
3. CA: A8,A9 = don't care.
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IC42S16100SIMPLIFIED STATE TRANSITION DIAGRAM (One Bank Operation)
SELFREFRESHSREF entrySREF exitMODEREGISTERSETMRSIDLEREFAUTOREFRESHCKE_CKEACTIDLEPOWERDOWNACTIVEPOWERDOWNCKE_CKEBSTBANKACTIVEWRIT READBSTWRITWRITAREADCKE_READAREADWRITEWRITREADCKE_CLOCKSUSPENDCKEWRITACKE_CKEWRITAREADAREADACKE_CKECLOCKSUSPENDWRITE WITHAUTOPRECHARGEPREPRE PREREAD WITHAUTOPRECHARGECKEPOWER APPLIEDPOWER ONPRE PRE-CHARGEAutomatic transition following the completion of command execution.Transition due to command input.Integrated Circuit Solution Inc.
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IC42S16100Device Initialization At Power-On
(Power-On Sequence)
As is the case with conventional DRAMs, the IC42S16100product must be initialized by executing a stipulated power-on sequence after power is applied.
After power is applied and VCC and VCCQ reach theirstipulated voltages, set and hold the CKE and DQM pinsHIGH for 100 µs. Then, execute the precharge commandto precharge both bank. Next, execute the auto-refreshcommand twice or more and define the device operationmode by executing a mode register set command.The mode register set command can be also set beforeauto-refresh command.
Burst Length
When writing or reading, data can be input or output datacontinuously. In these operations, an address is input onlyonce and that address is taken as the starting addressinternally by the device. The device then automaticallygenerates the following address. The burst length field inthe mode register stipulates the number of data items inputor output in sequence. In the IC42S16100 product, a burstlength of 1, 2, 4, 8, or full page can be specified. See thetable on the next page for details on setting the moderegister.
Burst Type
The burst data order during a read or write operation isstipulated by the burst type, which can be set by the moderegister set command. The IC42S16100 product supportssequential mode and interleaved mode burst type settings.See the table on the next page for details on setting themode register. See the \"Burst Length and Column AddressSequence\" item for details on I/O data orders in thesemodes.
Mode Register Settings
The mode register set command sets the mode register.When this command is executed, pins A0 to A9, A10, andA11 function as data input pins for setting the register, andthis data becomes the device internal OP code. This OPcode has four fields as listed in the table below.
Input PinA11, A10, A9, A8A6, A5, A4
A3A2, A1, A0
FieldMode OptionsCAS LatencyBurst TypeBurst Length
Write Mode
Burst write or single write mode is selected by the OP code(A11, A10, A9) of the mode register.
A burst write operation is enabled by setting the OP code(A11, A10, A9) to (0,0,0). A burst write starts on the samecycle as a write command set. The write start address isspecified by the column address and bank select addressat the write command set cycle.
A single write operation is enabled by setting OP code(A11, A10, A9) to (0,0,1). In a single write operation, datais only written to the column address and bank selectaddress specified by the write command set cycle withoutregard to the bust length setting.
Note that the mode register set command can be executedonly when both banks are in the idle (inactive) state. Waitat least two cycles after executing a mode register setcommand before executing the next command.
CAS Latency
During a read operation, the between the execution of theread command and data output is stipulated as the CASlatency. This period can be set using the mode register setcommand. The optimal CAS latency is determined by theclock frequency and device speed grade (-10/12). See the\"Operating Frequency / Latency Relationships\" item fordetails on the relationship between the clock frequencyand the CAS latency. See the table on the next page fordetails on setting the mode register.
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IC42S16100MODE REGISTER
111098765LT MODE43BT21BL0WRITE MODEAddress Bus
Mode Register (Mx)
M2Burst Length00001111M3Burst Type01M100110011M001010101TypeSequentialInterleavedSequential1248ReservedReservedReservedFull PageInterleaved1248ReservedReservedReservedReservedM6Latency Mode00001111M500110011M401010101CAS LatencyReservedReserved23ReservedReservedReservedReservedM1100M1000M901othersM800M700Write ModeBurst Read & Burst WriteBurst Read & Single WriteReservedIntegrated Circuit Solution Inc.
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IC42S16100BURST LENGTH AND COLUMN ADDRESS SEQUENCE Column AddressBurst LengthA2A1A0
24
X
XXXXX00001111n
XX001100110011n
01010101010101n
Address Sequence
SequentialInterleaved
0-1
1-00-1-2-31-2-3-02-3-0-13-0-1-20-1-2-3-4-5-6-71-2-3-4-5-6-7-02-3-4-5-6-7-0-13-4-5-6-7-0-1-24-5-6-7-0-1-2-35-6-7-0-1-2-3-46-7-0-1-2-3-4-57-0-1-2-3-4-5-6Cn, Cn+1, Cn+2Cn+3, Cn+4........Cn-1(Cn+255),Cn(Cn+256).....
0-11-00-1-2-31-0-3-22-3-0-13-2-1-00-1-2-3-4-5-6-71-0-3-2-5-4-7-62-3-0-1-6-7-4-53-2-1-0-7-6-5-44-5-6-7-0-1-2-35-4-7-6-1-0-3-26-7-4-5-2-3-0-17-6-5-4-3-2-1-0
None
8
Full Page(256)
Notes:
1.The burst length in full page mode is 256.
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IC42S16100BANK SELECT AND PRECHARGE ADDRESS ALLOCATION
Row
X0X1X2X3X4X5X6X7X8X9X10X11
Column
Y0Y1Y2Y3Y4Y5Y6Y7Y8Y9Y10Y11
——————————0101——————————0101
Row AddressRow AddressRow AddressRow AddressRow AddressRow AddressRow AddressRow AddressRow AddressRow Address
Precharge of the Selected Bank (Precharge Command)Row AddressPrecharge of Both Banks (Precharge Command)(Active Command)Bank 0 Selected (Precharge and Active Command)Bank 1 Selected (Precharge and Active Command)Column AddressColumn AddressColumn AddressColumn AddressColumn AddressColumn AddressColumn AddressColumn AddressDon't CareDon't Care
Auto-Precharge - DisabledAuto-Precharge - Enables
Bank 0 Selected (Read and Write Commands)Bank 1 Selected (Read and Write Commands)
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IC42S16100Burst Read
The read cycle is started by executing the read command.The address provided during read command execution isused as the starting address. First, the data correspondingto this address is output in synchronization with the clocksignal after the CAS latency period. Next, data correspondingto an address generated automatically by the device isoutput in synchronization with the clock signal.
The output buffers go to the LOW impedance state CASlatency minus one cycle after the read command, and goto the HIGH impedance state automatically after the lastdata is output. However, the case where the burst length
is a full page is an exception. In this case the output buffersmust be set to the high impedance state by executing aburst stop command.
Note that upper byte and lower byte output data can bemasked independently under control of the signals appliedto the U/LDQM pins. The delay period (tQMD) is fixed at two,regardless of the CAS latency setting, when this functionis used.
The selected bank must be set to the active state beforeexecuting this command.
CLKCOMMANDUDQMLDQMI/O8-I/O15I/O0-I/O 7DOUTA0DOUTA2DOUTA3READ A0tQMD=2HI-ZHI-ZDOUTA0READ (CA=A, BANK 0)DOUTA1HI-ZCAS latency = 2, burst length = 4DATA MASK (LOWER BYTE)DATA MASK (UPPER BYTE)Burst Write
The write cycle is started by executing the command. Theaddress provided during write command execution is usedas the starting address, and at the same time, data for thisaddress is input in synchronization with the clock signal.Next, data is input in other in synchronization with the clocksignal. During this operation, data is written to addressgenerated automatically by the device. This cycle terminatesautomatically after a number of clock cycles determined bythe stipulated burst length. However, the case where theburst length is a full page is an exception. In this case thewrite cycle must be terminated by executing a burst stopcommand. The latency for I/O pin data input is zero,
regardless of the CAS latency setting. However, a waitperiod (write recovery: tDPL) after the last data input isrequired for the device to complete the write operation.Note that the upper byte and lower byte input data can bemasked independently under control of the signals appliedto the U/LDQM pins. The delay period (tDMD) is fixed atzero, regardless of the CAS latency setting, when thisfunction is used.
The selected bank must be set to the active state beforeexecuting this command.
CLKCOMMANDI/OWRITEDIN0DIN1DIN2DIN 3BURST LENGTHCAS latency = 2,3, burst length = 424
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IC42S16100Read With Auto-Precharge
The read with auto-precharge command first executes aburst read operation and then puts the selected bank in theprecharged state automatically. After the precharge com-pletes, the bank goes to the idle state. Thus this commandperforms a read command and a precharge command ina single operation.
During this operation, the delay period (tPQL) between thelast burst data output and the start of the prechargeoperation differs depending on the CAS latency setting.When the CAS latency setting is two, the prechargeoperation starts on one clock cycle before the last burstdata is output (tPQL = –1). When the CAS latency setting is
three, the precharge operation starts on two clock cyclesbefore the last burst data is output (tPQL = –2). Therefore,the selected bank can be made active after a delay of tRPfrom the start position of this precharge operation.The selected bank must be set to the active state beforeexecuting this command.
The auto-precharge function is invalid if the burst length isset to full page.
CAS Latency
tPQL
3–2
2–1
CLKCOMMANDI/OREAD WITH AUTO-PRECHARGE(BANK 0)READA 0tPQLDOUT 0DOUT 1DOUT 2DOUT 3tRPACT 0PRECHARGE STARTCAS latency = 2, burst length = 4CLKCOMMANDI/OREAD WITH AUTO-PRECHARGE(BANK 0)READA 0tPQLDOUT 0PRECHARGE STARTACT 0DOUT 1DOUT 2tRPDOUT 3CAS latency = 3, burst length = 4Integrated Circuit Solution Inc.
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IC42S16100Write With Auto-Precharge
The write with auto-precharge command first executes aburst write operation and then puts the selected bank in theprecharged state automatically. After the prechargecompletes the bank goes to the idle state. Thus thiscommand performs a write command and a prechargecommand in a single operation.
During this operation, the delay period (tDAL) between thelast burst data input and the completion of the prechargeoperation differs depending on the CAS latency setting.The delay (tDAL) is tRP plus one CLK period. That is, theprecharge operation starts one clock period after the lastburst data input.
Therefore, the selected bank can be made active after adelay of tDAL.
The selected bank must be set to the active state beforeexecuting this command.
The auto-precharge function is invalid if the burst length isset to full page.
CAS Latency
tDAL
31CLK+tRP
21CLK+tRP
CLKCOMMANDI/OWRITE A0ACT 0PRECHARGE STARTDIN 0DIN 1DIN 2DIN 3tRPtDALWRITE WITH AUTO-PRECHARGE(BANK 0)CAS latency = 2, burst length = 4CLKCOMMANDI/OWRITE A0PRECHARGE STARTACT 0DIN 0DIN 1DIN 2DIN 3tRPtDALWRITE WITH AUTO-PRECHARGE(BANK 0)CAS latency = 3, burst length = 426Integrated Circuit Solution Inc.
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IC42S16100Interval Between Read Command
A new command can be executed while a read cycle is inprogress, i.e., before that cycle completes. When thesecond read command is executed, after the CAS latencyhas elapsed, data corresponding to the new read commandis output in place of the data due to the previous readcommand.
The interval between two read command (tCCD) must be atleast one clock cycle.
The selected bank must be set to the active state beforeexecuting this command.
CLKCOMMANDI/OtCCDREAD (CA=A, BANK 0)READ (CA=B, BANK 0)READ A0READ B0DOUT A0DOUT B0DOUT B1DOUT B2DOUT B3CAS latency = 2, burst length = 4Interval Between Write Command
A new command can be executed while a write cycle is inprogress, i.e., before that cycle completes. At the point thesecond write command is executed, data correspondingto the new write command can be input in place of the datafor the previous write command.
The interval between two write commands (tCCD) must beat least one clock cycle.
The selected bank must be set to the active state beforeexecuting this command.
CLKtCCDCOMMANDI/OWRITE A0WRITE B0DIN A0DIN B0DIN B1DIN B2DIN B3WRITE (CA=A, BANK 0)WRITE (CA=B, BANK 0)CAS latency = 2, burst length = 4Integrated Circuit Solution Inc.
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IC42S16100Interval Between Write and Read Commands
A new read command can be executed while a write cycleis in progress, i.e., before that cycle completes. Datacorresponding to the new read command is output afterthe CAS latency has elapsed from the point the new readcommand was executed. The I/On pins must be placed inthe HIGH impedance state at least one cycle before datais output during this operation.
The interval (tCCD) between command must be at least oneclock cycle.
The selected bank must be set to the active state beforeexecuting this command.
CLKtCCDCOMMANDI/OWRITE A0READ B0DIN A0WRITE (CA=A, BANK 0)HI-ZDOUT B0DOUT B1DOUT B2DOUT B3READ (CA=B, BANK 0)CAS latency = 2, burst length = 4CLKtCCDCOMMANDI/OWRITE A0READ B0DIN A0WRITE (CA=A, BANK 0)HI-ZREAD (CA=B, BANK 0)DOUT B0DOUT B1DOUT B2DOUT B3CAS latency = 3, burst length = 4Don’t Care28Integrated Circuit Solution Inc.
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IC42S16100Interval Between Read and Write Commands
A read command can be interrupted and a new writecommand executed while the read cycle is in progress, i.e., before that cycle completes. Data corresponding to thenew write command can be input at the point new writecommand is executed. To prevent collision between inputand output data at the I/On pins during this operation, the
output data must be masked using the U/LDQM pins. Theinterval (tCCD) between these commands must be at leastone clock cycle.
The selected bank must be set to the active state beforeexecuting this command.
CLKtCCDCOMMANDU/LDQMI/OREAD A0WRITE B0HI-ZDIN B0DIN B1DIN B2DIN B3READ (CA=A, BANK 0)WRITE (CA=B, BANK 0)CAS latency = 2, 3, burst length = 4Integrated Circuit Solution Inc.
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IC42S16100Precharge
The precharge command sets the bank selected by pinA11 to the precharged state. This command can beexecuted at a time tRAS following the execution of an activecommand to the same bank. The selected bank goes to theidle state at a time tRP following the execution of theprecharge command, and an active command can beexecuted again for that bank.
If pin A10 is low when this command is executed, the bankselected by pin A11 will be precharged, and if pin A10 isHIGH, both banks will be precharged at the same time.This input to pin A11 is ignored in the latter case.
Read Cycle InterruptionUsing the Precharge Command
A read cycle can be interrupted by the execution of theprecharge command before that cycle completes. Thedelay time (tRQL) from the execution of the prechargecommand to the completion of the burst output is the clockcycle of CAS latency.
CAS Latency
tRQL
33
22
CLKtRQLCOMMANDI/OREAD A0PRE 0DOUT A0READ (CA=A, BANK 0)DOUT A1DOUT A2HI-Z PRECHARGE (BANK 0)CAS latency = 2, burst length = 4CLKtRQLCOMMANDI/OREAD A0PRE 0DOUT A0READ (CA=A, BANK 0)DOUT A1DOUT A2HI-Z PRECHARGE (BANK 0)CAS latency = 3, burst length = 430Integrated Circuit Solution Inc.
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IC42S16100Write Cycle Interruption Using thePrecharge Command
A write cycle can be interrupted by the execution of theprecharge command before that cycle completes. Thedelay time (tWDL) from the precharge command to the pointwhere burst input is invalid, i.e., the point where input datais no longer written to device internal memory is zero clockcycles regardless of the CAS.
To inhibit invalid write, the DQM signal must be assertedHIGH with the precharge command.
This precharge command and burst write command mustbe of the same bank, otherwise it is not precharge interruptbut only another bank precharge of dual bank operation.
Inversely, to write all the burst data to the device, theprecharge command must be executed after the write datarecovery period (tDPL) has elapsed. Therefore, theprecharge command must be executed on one clock cyclethat follows the input of the last burst data item.
CAS Latency
tWDLtDPL
301
201
CLKtWDL=0COMMANDDQMI/OWRITE A0PRE 0DIN A0DIN A1DIN A2DIN A3MASKED BY DQMWRITE (CA=A, BANK 0)PRECHARGE (BANK 0)CAS latency = 2, 3, burst length = 4CLKtDPLCOMMANDI/OWRITE A0PRE 0DIN A0DINA1DIN A2DIN A3PRECHARGE (BANK 0)WRITE (CA=A, BANK 0)CAS latency = 2, 3, burst length = 4Integrated Circuit Solution Inc.
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IC42S16100Read Cycle (Full Page) Interruption Usingthe Burst Stop Command
The IC42S16100 can output data continuously from theburst start address (a) to location a+255 during a readcycle in which the burst length is set to full page. TheIC42S16100 repeats the operation starting at the 256thcycle with the data output returning to location (a) andcontinuing with a+1, a+2, a+3, etc. A burst stop commandmust be executed to terminate this cycle. A prechargecommand must be executed within the ACT to PREcommand period (tRAS max.) following the burst stopcommand.
After the period (tRBD) required for burst data output to stopfollowing the execution of the burst stop command haselapsed, the outputs go to the HIGH impedance state. Thisperiod (tRBD) is two clock cycle when the CAS latency is twoand three clock cycle when the CAS latency is three.
CAS Latency
tRBD
33
22
CLKtRBDCOMMANDI/OREAD A0BSTDOUT A0READ (CA=A, BANK 0)DOUT A0DOUT A1DOUT A2BURST STOPDOUT A3HI-ZCAS latency = 2, burst length = full pageCLKtRBDCOMMANDI/OREAD A0BSTDOUT A0 READ (CA=A, BANK 0)DOUT A0DOUT A1BURST STOPDOUT A2DOUT A3HI-ZCAS latency = 3, burst length = full page32Integrated Circuit Solution Inc.
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IC42S16100Write Cycle (Full Page) Interruption Usingthe Burst Stop Command
The IC42S16100 can input data continuously from theburst start address (a) to location a+255 during a writecycle in which the burst length is set to full page. TheIC42S16100 repeats the operation starting at the 256thcycle with data input returning to location (a) and continuingwith a+1, a+2, a+3, etc. A burst stop command must beexecuted to terminate this cycle. A precharge command
must be executed within the ACT to PRE command period(tRAS max.) following the burst stop command. After theperiod (tWBD) required for burst data input to stop followingthe execution of the burst stop command has elapsed, thewrite cycle terminates. This period (tWBD) is zero clockcycles, regardless of the CAS latency.
CLKtWBD=0tRPPRE 0COMMANDI/OWRITE A0 DIN A0DIN A1DINADIN A1DIN A2BSTINVALID DATAREAD (CA=A, BANK 0)BURST STOPPRECHARGE (BANK 0)CAS latency = 2, 3, burst length = full pageDon’t CareBurst Data Interruption Using the U/LDQM Pins (Read Cycle)
Burst data output can be temporarily interrupted (masked)during a read cycle using the U/LDQM pins. Regardless ofthe CAS latency, two clock cycles (tQMD) after one of the U/LDQM pins goes HIGH, the corresponding outputs go tothe HIGH impedance state. Subsequently, the outputs aremaintained in the high impedance state as long as that U/LDQM pin remains HIGH. When the U/LDQM pin goes
LOW, output is resumed at a time tQMD later. This outputcontrol operates independently on a byte basis with theUDQM pin controlling upper byte output (pinsI/O8-I/O15) and the LDQM pin controlling lower byteoutput (pins I/O0 to I/O7).
Since the U/LDQM pins control the device output buffersonly, the read cycle continues internally and, in particular,incrementing of the internal burst counter continues.
CLKCOMMANDUDQMLDQMI/O8-I/O15I/O0-I/O 7READ (CA=A, BANK 0)READ A0tQMD=2DOUTA0HI-ZDOUTA2DOUTA3HI-ZDOUTA0DOUTA1HI-ZDATA MASK (LOWER BYTE)CAS latency = 2, burst length = 4Integrated Circuit Solution Inc.
DR024-0D 06/25/2004
DATA MASK (UPPER BYTE)33
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IC42S16100Burst Data Interruption U/LDQM Pins(Write Cycle)
Burst data input can be temporarily interrupted (muted )during a write cycle using the U/LDQM pins. Regardlessof the CAS latency, as soon as one of the U/LDQM pinsgoes HIGH, the corresponding externally applied inputdata will no longer be written to the device internal circuits.Subsequently, the corresponding input continues to bemuted as long as that U/LDQM pin remains HIGH.The IC42S16100 will revert to accepting input as soon as
CLKCOMMANDUDQMtDMD=0WRITE A0that pin is dropped to LOW and data will be written to thedevice. This input control operates independently on abyte basis with the UDQM pin controlling upper byte input(pin I/O8 to I/O15) and the LDQM pin controlling the lowerbyte input (pins I/O0 to I/O7).
Since the U/LDQM pins control the device input buffersonly, the cycle continues internally and, inparticular,incrementing of the internal burst counter continues.
LDQMI/O8-I/O15I/O0-I/O7WRITE (CA=A, BANK 0)DINA1DINA2DINA3DINA0DATA MASK (LOWER BYTE)DINA3CAS latency = 2, burst length = 4DATA MASK (UPPER BYTE)Don’t CareBurst Read and Single Write
The burst read and single write mode is set up using themode register set command. During this operation, theburst read cycle operates normally, but the write cycle onlywrites a single data item for each write cycle. The CASlatency and DQM latency are the same as in normal mode.
CLKCOMMANDI/OCAS latency = 2, 334
WRITE A0DIN A0WRITE (CA=A, BANK 0)Integrated Circuit Solution Inc.
DR024-0D 06/25/2004
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IC42S16100Bank Active Command Interval
When the selected bank is precharged, the period trp haselapsed and the bank has entered the idle state, the bankcan be activated by executing the active command. If theother bank is in the idle state at that time, the activecommand can be executed for that bank after the periodtRRD has elapsed. At that point both banks will be in theactive state. When a bank active command has beenexecuted, a precharge command must be executed for
CLKtRRDthat bank within the ACT to PRE command period (tRASmax). Also note that a precharge command cannot beexecuted for an active bank before tRAS (min) has elapsed.After a bank active command has been executed and thetrcd period has elapsed, read write (including auto-precharge) commands can be executed for that bank.
COMMANDACT 0ACT 1BANK ACTIVE (BANK 1)BANK ACTIVE (BANK 0)CLKtRCDCOMMANDACT 0READ 0BANK ACTIVE (BANK 0)CAS latency = 3BANK ACTIVE (BANK 0)Clock Suspend
When the CKE pin is dropped from HIGH to LOW during aread or write cycle, the IC42S16100 enters clock suspendmode on the next CLK rising edge. This command reducesthe device power dissipation by stopping the device internalclock. Clock suspend mode continues as long as the CKEpin remains low. In this state, all inputs other than CKE pinare invalid and no other commands can be executed. Also,the device internal states are maintained. When the CKEpin goes from LOW to HIGH clock suspend mode isterminated on the next CLK rising edge and device operationresumes.
CLKThe next command cannot be executed until the recoveryperiod (tCKA) has elapsed.
Since this command differs from the self-refresh commanddescribed previously in that the refresh operation is notperformed automatically internally, the refresh operationmust be performed within the refresh period (tref). Thus themaximum time that clock suspend mode can be held is justunder the refresh cycle time.
CKECOMMANDI/OREAD 0DOUT0READ (BANK 0)DOUT1DOUT2DOUT 3CAS latency = 2, burst length = 4Integrated Circuit Solution Inc.
DR024-0D 06/25/2004
CLOCK SUSPEND35
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IC42S16100OPERATION TIMING EXAMPLE
Power-On Sequence, Mode Register Set Cycle
T0CLKtCKtCHItCLT1T2T3T10T17 T18T19T20CKEHIGHtCStCHtCStCHtCHtCHtAStAHCODEtAStAHBANK 0 & 1CSRAStCSCAStCSWEA0-A9tASCODEtAStAHCODEBANK 0 ROWtAHROWBANK 1A10A11DQMHIGHI/OWAIT TIMET=100 s DR024-0D 06/25/2004 元器件交易网www.cecb2b.com IC42S16100Power-Down Mode Cycle T0CLKtCKStCKtCKAtCHtCStCHtCHtCHtAStAHROWtAStAHBANK 0 & 1BANK 0 OR 1T1tCHIT2T3Tn Tn+1Tn+2Tn+3tCLtCKStCKHtCKACKEtCSCSRAStCSCAStCSWEA0-A9A10A11DQMI/OtRP DR024-0D 06/25/2004 37 元器件交易网www.cecb2b.com IC42S16100Auto-Refresh Cycle T0CLKtCKStCKtCHItCLT1T2T3TlTmTnTn+1CKEtCStCHtCStCHtCHtCHCSRAStCSCAStCSWEA0-A9tAStAHBANK 0 & 1ROWROWBANK 1A10A11BANK 0 DQMI/OtRP DR024-0D 06/25/2004 元器件交易网www.cecb2b.com IC42S16100Self-Refresh Cycle