74F573资料

元器件交易网www.cecb2b.comPhilips Semiconductors Product specificationLatch/flip-flop74F573/74F57474F573 Octal Transparent Latch (3-State)74F574 Octal D Flip-Flop (3-State)FEATURESThe 74F574 is functionally identical to the 74F374 but has a•74F573 is broadside pinout version of 74F373broadside pinout configuration to facilitate PC board layout and•allow easy interface with microprocesors.74F574 is broadside pinout version of 74F374It is an 8-bit, edge triggered register coupled to eight 3-State output•Inputs and Outputs on opposite side of package allow easybuffers. The two sections of the device are controlled independentlyinterface to Microprocessorsby the clock (CP) and Output Enable (OE) control gates.•Useful as an Input or Output port for MicroprocessorsThe register is fully edge-triggered. The state of each D input, one•setup time before the Low-to-High clock transition is transferred to3-State Outputs for Bus interfacingthe corresponding flip-flop’s Q output.•Common Output EnableThe 3-State output buffers are designed to drive heavily loaded•74F563 and 74F5 are inverting version of 74F573 and 74F5743-State buses, MOS memories, or MOS microprocessors. Therespectivelyactive Low Output Enable (OE) controls all eight 3-State buffersindependently of the latch operation. When OE is Low, the latched•3-State Outputs glitch free during power-up and power-downor transparent data appears at the outputs. When OE is High, the•These are High-Speed replacements for N8TS805 and N8TS806outputs are in high impedance “off” state, which means they willneither drive nor load the bus.DESCRIPTIONTYPICAL SUPPLYThe 74F573 is an octal transparent latch coupled to eight 3-StateTYPETYPICALCURRENToutput buffers. The two sections of the device are controlledPROPAGATION DELAY(TOTAL)independently by Enable (E) and Output Enable (OE) control gates.74F5735.0ns35mAThe 74F573 is functionally identical to the 74F373 but has abroadside pinout configuration to facilitate PC board layout andallow easy interface with microprocessors.TYPICAL SUPPLYTYPETYPICAL fMAXCURRENTThe data on the D inputs is transferred to the latch outputs when the(TOTAL)Enable (E) input is High. The latch remains transparent to the datainput while E is High and stores the data that is present one setup74F574180MHz50mAtime before the High-to-Low enable transition.The 3-State output buffers are designed to drive heavily loadedORDERING INFORMATION3-State buses, MOS memories, or MOS microprocessors. TheCOMMERCIAL RANGEactive Low Output Enable (OE) controls all eight 3-State buffersDESCRIPTIONVCC = 5V ±10%, PKG DWG #independent to the latch operation. When OE is Low, the latched orTamb = 0°C to +70°Ctransparent data appears at the outputs. When OE is High, theoutputs are in high impedance “off” state, which means they will20-Pin Plastic DIPN74F573N, N74F574NSOT146-1neither drive nor load the bus.20-PinPlasticSOLN74F573D, N74F574DSOT163-120-PinPlasticSSOPN74F573DBSOT339-1INPUT AND OUTPUT LOADING AND FAN-OUT TABLEPINSDESCRIPTION74F (U.L.)LOAD VALUEHIGH/LOWHIGH/LOWD0 - D7Data inputs1.0/1.020µA/0.6mAE (74F573)Latch Enable input (active falling edge)1.0/1.020µA/0.6mAOEOutput Enable input (active Low)1.0/1.020µA/0.6mACP (74F574)Clock Pulse input (active rising edge)1.0/1.020µA/0.6mAQ0 - Q73-State outputs150/403.0mA/24mANOTE: One (1.0) FAST Unit Load is defined as: 20µA in the High state and 0.6mA in the Low state.19 Oct 162853-0083 977元器件交易网www.cecb2b.comPhilips Semiconductors Latch/flip-flopPIN CONFIGURATION – 74F573OE120VCCD0219Q0D1318Q1D2417Q2D3516Q3D4615Q4D5714Q5D6813Q6D7912Q7GND1011ESF01073LOGIC SYMBOL – 74F573234567D0D1D2D3D4D5D6D711E1OEQ0Q1Q2Q3Q4Q5Q6Q71918171615141312VCC=Pin 20GND=Pin 10SF01075LOGIC SYMBOL (IEEE/IEC) – 74F5731EN111EN222D119318417516615714813912SF0107719 Oct 16Product specification74F573/74F574PIN CONFIGURATION – 74F574OE120VCCD0219Q0D1318Q1D2417Q2D3516Q3D4615Q4D5714Q5D6813Q6D7912Q7GND1011CPSF01074LOGIC SYMBOL – 74F574234567D0D1D2D3D4D5D6D711CP1OEQ0Q1Q2Q3Q4Q5Q6Q71918171615141312VGND=Pin 10CC=Pin 20SF01076LOGIC SYMBOL (IEEE/IEC) – 74F5741EN111C222D119318417516615714813912SF010783元器件交易网www.cecb2b.comPhilips Semiconductors Product specificationLatch/flip-flop74F573/74F574LOGIC DIAGRAM – 74F573D0D1D2D3D4D5D6D7234567DDDDDDDDEQEQEQEQEQEQEQEQE11OE11918171615141312VCC=Pin 20GND=Pin 10Q0Q1Q2Q3Q4Q5Q6Q7SF01079FUNCTION TABLE – 74F573INPUTSINTERNAL OUTPUTSOEEDnREGISTERQ0 – Q7OPERATINGOPERATING MODESMODESLHLLLLHHHHLoad and read registerL↓lLLL↓hHHLatch and read registerLLXNCNCHoldHLXNCZHHDnDnZDisable outputsH=High voltage levelh=High voltage level one setup time prior to the High-to-Low E transitionL=Low voltage levell=Low voltage level one setup time prior to the High-to-Low E transitionNC=No changeX=Don’t careZ=High impedance “off” state↓=High-to-Low E transitionLOGIC DIAGRAM – 74F574D0D1D2D3D4D5D6D7234567DDDDDDDDCPQCPQCPQCPQCPQCPQCPQCPQCP11OE11918171615141312VCC=Pin 20GND=Pin 10Q0Q1Q2Q3Q4Q5Q6Q7SF0108019 Oct 1元器件交易网www.cecb2b.comPhilips Semiconductors Product specificationLatch/flip-flop74F573/74F574FUNCTION TABLE – 74F574INPUTSINTERNAL OUTPUTSOECPDnREGISTERQ0 – Q7OPERATINGOPERATING MODESMODESL↑lLLL↑hHHLoad and read registerL↑XNCNCHoldH↑DnDnZDisable outputsH=High voltage levelh=High voltage level one setup time prior to the Low-to-High clock transitionL=Low voltage levell=Low voltage level one setup time prior to the Low-to-High clock transitionNC=No changeX=Don’t careZ=High impedance “off” state↑=Low-to-High clock transition↑=Not a Low-to-High clock transitionABSOLUTE MAXIMUM RATINGS(Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.)SYMBOLPARAMETERRATINGUNITVCCSupply voltage–0.5 to +7.0VVINInput voltage–0.5 to +7.0VIINInput current–30 to +5.0mAVOUTVoltage applied to output in High output state–0.5 to +VCCVIOUTCurrent applied to output in Low output state48mATambOperating free-air temperature range0 to +70°CTstgStorage temperature–65 to +150°CRECOMMENDED OPERATING CONDITIONSSYMBOLPARAMETERLIMITSMINNOMMAXUNITVCCSupply voltage4.55.05.5VVIHHigh-level input voltage2.0VVILLow-level input voltage0.8VIIKInput clamp current–18mAIOHHigh-level output current–3mAIOLLow-level output current24mATambOperating free-air temperature range070°C19 Oct 165元器件交易网www.cecb2b.comPhilips Semiconductors Product specificationLatch/flip-flop74F573/74F574DC ELECTRICAL CHARACTERISTICS(Over recommended operating free-air temperature range unless otherwise noted.)LIMITSSYMBOLPARAMETERTEST CONDITIONSNONO TAGTAGMINNO TAGTYPMAXUNITVHighHigh-level output voltageleveloutputvoltageVCC = MIN, V MIN, VIL = MAX, MAX, ±10%VCC2.4VOHOVIH = MIN, IOH = MAX±5%VCC2.73.4VVOLOLowLow-level output voltageleveloutputvoltageVCC = MIN, V MIN, VIL = MAX, MAX, ±10%VCC0.350.50VVIH = MIN, IOL = MAX±5%VCC0.350.50VVIKInput clamp voltageVCC = MIN, II = IIK–0.73–1.2VIIInput current at maximum input voltageVCC = MAX, VI = 7.0V100µAIIHHigh-level input currentVCC = MAX, VI = 2.7V20µAIILLow-level input currentVCC = MAX, VI = 0.5V–0.6mAIOZHOff-state output current,High-level voltage appliedVCC = MAX, VO = 2.7V 50µAIOZLOff-state output current,Low-level voltage appliedVCC = MAX, VO = 0.5V –50µAIOSShort-circuit output currentNO TAGVCC = MAX–60–150mAICCH3040mAICCL74F573VCC = MAX3550mASupplyI60mACCcurrentICCZ40(total)()ICCH4565mAICCL74F574VCC = MAX5070mAICCZ5585mANOTES:1.For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.2.All typical values are at VCC = 5V, Tamb = 25°C.3.Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-holdtechniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shortingof a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In anysequence of parameter tests, IOS tests should be performed last.19 Oct 166元器件交易网www.cecb2b.comPhilips Semiconductors Product specificationLatch/flip-flop74F573/74F574AC ELECTRICAL CHARACTERISTICSLIMITSTEST TTSYMBOLPARAMETERCONDITIONSamb= +25°CVamb = 0°C to +70°CV = 50pF, RCC = +5VCCC = +5V ± 10%UNITLL = 500ΩCL = 50pF, RL = 500ΩMINTYPMAXMINMAXtPropagation delayWaveform3.05.58.02.59.0tPLHPHLDn to QnNO TAG1.03.56.01.07.0nstPropagation delayWaveform4.58.511..012.5tPLHPHLE to QnNO TAG3.05.07.02.58.0nsWaveformtOutput Enable time NO TAG2.55.59.52.010.5tPZHPZLto High or Low level74F573Waveform2.55.58.02.08.5nsNO TAGWaveformtOutput Disable timeNO TAG1.03.06.01.06.5tPHZPLZfrom High or Low levelWaveform1.02.55.51.05.5nsNO TAGfMAXMaximum Clock frequencyWaveformNO TAG160180150MHztPropagation delayWaveform3.55.07.53.08.0tPLHPHLCP to QnNO TAG3.55.07.53.08.0nsWaveformtOutput Enable time 74F574NO TAG2..57.52.07.5tPZHPZLto High or Low levelWaveform3.05.08.03.08.5nsNO TAGWaveformtPHZOutput Disable timeNO TAG1.03.05.51.06.0tPLZfrom High or Low levelWaveform1.02.55.51.06.0nsNO TAGAC SETUP REQUIREMENTSLIMITSTSYMBOLPARAMETERTEST Tamb= +25°Camb = 0°C to +70°CCONDITIONSVVCCC = +5VCC = +5.0V ± 10%UNITL = 50pF, RL = 500ΩCL = 50pF, RL = 500ΩMINTYPMAXMINMAXtSetup time,0.0ts(H)s(L)Dn to EWaveform 40.01.52.0nsth(H)Hold time,2.5th(L)Dn to E74F573Waveform 42..04.0nstw(H)E pulse width,HighWaveform NO TAG3.03.5nstSetup time,3.0ts(H)s(L)Dn to CPWaveform NO TAG2.52.53.0nsth(H)Hold time,0th(L)Dn to CP74F574Waveform NO TAG000nstw(H)CP Pulse width,3.0tw(L)High or LowWaveform NO TAG3.03..0ns19 Oct 167元器件交易网www.cecb2b.comPhilips Semiconductors Product specificationLatch/flip-flop74F573/74F574AC WAVEFORMSFor all waveforms, VM = 1.5VThe shaded areas indicate when the input is permitted to change for predictable output performance.1/fMAXE, CPVMVMVMtW(H)tW(L)tPHLtPLHQnVMVMSF01081Waveform 1. Propagation Delay, Clock and Enable Inputs to Output, Enable, Clock Pulse Widths, and Maximum Clock FrequencyDnVMVMVMVMts(H)th(H)ts(L)th(L)CPVMVMSF00191Waveform 3. Data Setup and Hold TimesOEVMVMtPZHtPHZVOH -0.3VQnVM0VSF00343Waveform 5. 3-State Output Enable Time to High Leveland Output Disable Time from High Level19 Oct 16DnVMVMtPLHtPHLQnVMVMSF01082Waveform 2. Propagation Delay for Data to OutputsDnVMVMVMVMts(H)th(H)ts(L)th(L)EVMVMSF00992Waveform 4. Data Setup and Hold TimesOEVMVMtPZLtPLZQnVMVOL +0.3VSF00344Waveform 6. 3-State Output Enable Time to Low Leveland Output Disable Time from Low Level8元器件交易网www.cecb2b.comPhilips Semiconductors Product specificationLatch/flip-flop74F573/74F574TEST CIRCUIT AND WAVEFORMVCC7.0V90%tw90%AMP (V)VINVOUTRLNEGATIVEPULSEVMVMPULSEGENERATORD.U.T.10%10%0VtTHL (tf )tTLH (tr )RTCLRLtTLH (tr )tTHL (tf )90%90%AMP (V)Test Circuit for 3-State OutputsPOSITIVEPULSEVMVMSWITCH POSITION10%t10%w0VTESTSWITCHtPLZclosedInput Pulse DefinitiontPZLclosedAll otheropenDEFINITIONS:RL=Load resistor; see AC electrical characteristics for value.CL=Load capacitance includes jig and probe capacitance; familyINPUT PULSE REQUIREMENTSsee AC electrical characteristics for value.amplitudeVMrep. ratetwtTLHtTHLRT=Termination resistance should be equal to ZOUT of pulse generators.74F3.0V1.5V1MHz500ns2.5ns2.5nsSF0077719 Oct 169元器件交易网www.cecb2b.com

Philips Semiconductors

Product specification

Latch/flip-flop74F573, 74F574

DIP20:plastic dual in-line package; 20 leads (300 mil)SOT146-1

19 Oct 1610

元器件交易网www.cecb2b.com

Philips Semiconductors

Product specification

Latch/flip-flop74F573, 74F574

SO20:plastic small outline package; 20 leads; body width 7.5 mmSOT163-1

19 Oct 1611

元器件交易网www.cecb2b.com

Philips Semiconductors

Product specification

Latch/flip-flop74F573, 74F574

SSOP20:plastic shrink small outline package; 20 leads; body width 5.3 mmSOT339-1

19 Oct 1612

元器件交易网www.cecb2b.com

Philips Semiconductors

Latch/flip-flop19 Oct 16Product specification

74F573, 74F574

NOTES

13

元器件交易网www.cecb2b.com

Philips Semiconductors

Product specification

Latch/flip-flop74F573, 74F574

Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. Fordetailed information see the relevant data sheet or data handbook.

Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above oneor more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these orat any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extendedperiods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. PhilipsSemiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing ormodification.

Disclaimers

Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products canreasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applicationsdo so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standardcells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes noresponsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to theseproducts, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unlessotherwise specified.

Philips Semiconductors811 East Arques AvenueP.O. Box 3409

Sunnyvale, California 94088–3409Telephone 800-234-7381

© Copyright Philips Electronics North America Corporation 1998

All rights reserved. Printed in U.S.A.

print code

Document order number:Date of release: 10-98

9397-750-05141PhilipsSemiconductorsyyyy mmm dd14