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PCI Express External Cabling Specification Version_0_3 draft J

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PCI EXPRESS EXTERNAL CABLING SPECIFICATION, REV. 0.3

PCI Express™ External Cabling

Specification Revision 0.3 Draft J

April 21, 2004

PCI EXPRESS EXTERNAL CABLING SPECIFICATION, REV. 0.3

REVISION REVISION HISTORY 0.3A 0.3B 0.3C 0.3D 0.3E 0.3F 0.3G 0.3H 0.3I 0.3J

Initial WG-only release

Updated cable application matrix and added explanatory

notes

Updated cable application explanatory notes Added preliminary content and table

Added DC specifications for the cable detect mechanism Incorporated feedback from the 1/21/04 WG review. Added content on electrical budget, eye pattern and more Added cable electrical specs. and connector information Incorporated feedback from the 4/7/04 & 4/14/04 WG review.

Incorporated feedback from the 4/21/04 WG review.

DATE 11/5/03 11/11/03 11/13/03 12/05/03 1/20/04 1/26/04 2/06/04 3/31/04 4/16/04 4/21/04

PCI-SIG disclaims all warranties and liability for the use of this document and the information

contained herein and assumes no responsibility for any errors that may appear in this document, nor does PCI-SIG make a commitment to update the information contained herein.

Contact the PCI-SIG office to obtain the latest revision of the specification.

Questions regarding the PCI Express™ External Cabling Specification or membership in PCI-SIG may be forwarded to:

Membership Services www.pcisig.com

E-mail: administration@pcisig.com Phone: 503-291-2569 Fax: 503-297-1090

Technical Support techsupp@pcisig.com

DISCLAIMER

This PCI Express™ External Cabling Specification is provided “as is” with no warranties whatsoever, including any warranty of merchantability, noninfringement, fitness for any particular purpose, or any warranty otherwise arising out of any proposal, specification, or sample. PCI-SIG disclaims all liability for infringement of proprietary rights, relating to use of information in this specification. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. PCI Express is a trademark of PCI-SIG.

All other product names are trademarks, registered trademarks, or servicemarks of their respective owners.

PCI EXPRESS EXTERNAL CABLING SPECIFICATION, REV. 0.3

Contents

INTRODUCTION..................................................................................................................7 1.1. TERMS AND ACRONYMS..................................................................................................7 1.2. OBJECTIVE OF THE SPECIFICATION...................................................................................8 1.3. REFERENCE DOCUMENTS.................................................................................................8 1.4. DOCUMENTATION CONVENTIONS....................................................................................8 1.5. CABLE APPLICATIONS......................................................................................................9 2.

ELECTRICAL OVERVIEW.............................................................................................11 2.1. PCI EXPRESS SIGNALS...................................................................................................11 2.1.1. Interconnect............................................................................................................11 2.1.2. Electrical Budgets...................................................................................................13 2.1.3. Eye Diagrams Compliance Measurements.............................................................18 2.2. AUXILIARY SIGNALS......................................................................................................19 2.2.1. Cable Reference Clock............................................................................................20 2.2.2. Cable Presence Detect............................................................................................25 2.2.3. Power......................................................................................................................28 2.2.4. ESD.........................................................................................................................28 2.3. L2 POWER STATE TRANSITION......................................................................................29

CABLE CONNECTOR DEFINITION..............................................................................30 3.1. SIGNAL DESCRIPTION....................................................................................................30 3.1.1. PCI Express............................................................................................................30 3.1.2. CREFCLK...............................................................................................................30 3.1.3. Presence Detect......................................................................................................30 3.1.4. Power......................................................................................................................30 3.2. BOARD CONNECTOR......................................................................................................30 3.2.1. Description..............................................................................................................30 3.2.2. Physical and Mechanical Performance..................................................................30 3.2.3. Electrical Performance...........................................................................................31 3.2.4. Environmental Performance...................................................................................32 3.2.5. x1 Link.....................................................................................................................32 3.2.6. x4 Link.....................................................................................................................32 3.2.7. x8 Link.....................................................................................................................32 3.2.8. x16 Link...................................................................................................................33 3.3. SHIELDING.....................................................................................................................33 3.4. KEYING..........................................................................................................................33 3.5. MECHANICAL.................................................................................................................33

4. CABLE SPECIFICATION.................................................................................................34 4.1. INTRODUCTION..............................................................................................................34 4.2. REQUIREMENTS..............................................................................................................34 4.2.1. Physical and Mechanical Performance..................................................................34

PCI EXPRESS EXTERNAL CABLING SPECIFICATION, REV. 0.3

4.2.2. Electrical Performance...........................................................................................34 4.2.3. Environmental Performance...................................................................................35 4.3. CONNECTOR DESCRIPTION.............................................................................................35 4.3.1. x1 Link.....................................................................................................................35 4.3.2. x4 Link.....................................................................................................................36 4.3.3. x8 Link.....................................................................................................................36 4.3.4. x16 Link...................................................................................................................36 4.4. SHIELDING.....................................................................................................................36 4.5. KEYING..........................................................................................................................36 4.6. LABELING......................................................................................................................36 4.7. M

ECHANICAL.................................................................................................................36

PCI EXPRESS EXTERNAL CABLING SPECIFICATION, REV. 0.3

Figures

FIGURE 1-1: EXTERNAL CABLE APPLICATION MATRIX...................................................................9 FIGURE 2-1: LINK AND LOSS DEFINITION......................................................................................12 FIGURE 2-3: JITTER MEASUREMENT..............................................................................................15 FIGURE 2-4: DIFFERENTIAL CREFCLK WAVEFORM....................................................................23 FIGURE 2-5: SINGLE-ENDED MEASUREMENT POINTS FOR DELTA CROSS POINT...........................23 FIGURE 2-6: SINGLE-ENDED MEASUREMENT POINTS FOR RISE AND FALL TIME MATCHING........23 FIGURE 2-7: DIFFERENTIAL MEASUREMENT POINTS FOR DUTY CYCLE AND PERIOD....................24 FIGURE 2-8: DIFFERENTIAL MEASUREMENT POINTS FOR RISE AND FALL TIME............................24 FIGURE 2-9: DIFFERENTIAL MEASUREMENT POINTS FOR RINGBACK............................................24 FIGURE 2-10: REFERENCE CLOCK SYSTEM MEASUREMENT POINT AND LOADING........................24 FIGURE 2-11: PRESENT DETECT FUNCTIONAL DIAGRAM.............................................................26 FIGURE 2-12: POWER-UP TIMING SLAVE DEVICE..........................................................................28

PCI EXPRESS EXTERNAL CABLING SPECIFICATION, REV. 0.3

Tables

TABLE 2-1: ALLOCATION OF INTERCONNECT PATH INSERTION LOSS BUDGET 14

TABLE 2-2: ALLOCATION OF JITTER BUDGET 15 TABLE 2-3: ALLOWABLE INTERCONNECT LANE-TO-LANE SKEW 16 TABLE 2-4: TRANSMITTER PATH COMPLIANCE EYE REQUIREMENTS 18 TABLE 2-4: RECEIVER PATH COMPLIANCE EYE REQUIREMENTS 19

TABLE 2-4: TRANSMITTER AC TIMING REQUIREMENTS 21 TABLE 2-5: RECEIVER AC TIMING REQUIREMENTS 22 TABLE 2-6: CABLE PRESENT DETECT DC SPECIFICATIONS 27

TABLE 2-7: POWER-UP TIMING SLAVE DEVICE 28

PCI EXPRESS EXTERNAL CABLING SPECIFICATION, REV. 0.3

1. Introduction

This document covers external cabling solutions for PCI Express. Its purpose is to define electromechanical specifications for the complete interconnect, including cables and cable connectors. Some of the projected usage models for such solutions are:

Expansion I/O Split-system desktop

Tethered docking for mobile platforms External graphics controllers

The focus of this document is on copper-based cabling. Optical-based solutions might be covered in subsequent revisions.

Other than providing signaling compliant with the PCI Express Base Specification, and any erratea thereof that might exist, this cable specification makes no assumptions as to the source and destination thereoff. For instance, a source could be the Root Complex, Switch or other PCI Express device and the destination could be a Switch, end-point or other PCI Express compliant device. Contained within this specification are the cable, connector and board side requirements for providing a reliable cabled PCI Express solution.

1.1. Terms and Acronyms

Auxiliary signals Basic bandwidth x1, x2, x4, x8, x16 Endpoint

Signals not required by the PCI Express architecture but necessary

for certain desired functions or system implementation, for example, the REFCLK signal. Contains one PCI Express Lane.

x1 refers to one PCI Express Lane of basic bandwidth; x4 to a collection of four PCI Express Lanes; etc.

A device connected to a host system via a PCI Express external cable The compute entity which contains the PCI Express root complex and is the source of the reference clock signal

Insertion and/or removal of a cable into an active subsystem A collection of one or more PCI Express Lanes

Host System Hot-Plug Link

PCI Express Lane One PCI Express Lane contains two differential lines for Transmitter and two differential lines for Receiver. A by-N Link is composed of N Lanes.

PCI EXPRESS EXTERNAL CABLING SPECIFICATION, REV. 0.3

Sideband signaling A method for signaling events and conditions using physical signals separate from signals forming the Link between two components. Subsystem

In the context of this presentation Subsystem is a generic term identifying either an upstream or downstream device providing a cabled PCI Express Link

Wakeup A mechanism used by a component to request the reapplication of main power when in the L2 Link state. Two such mechanisms are defined in the PCI Express Base Specification: Beacon and WAKE#.

1.2. Objective of the Specification

The objectives of this specification are as follows:

Define PCI Express external cables and associated connectors. • Forward looking for future scalability

• Allows revolutionary partitioning of the PC architecture • Upgradeability

• This specification contains the following information: • Subsystem requirements

• Sideband signaling and usage models • Subsystem electrical budgets • Cable and connector electrical budget • Cable and connector specifications

1.3. Reference Documents

PCI Express Base Specification, Revision 1.0a

1.4. Documentation Conventions

Capitalization

Some terms are capitalized to distinguish their definition in the context of this document from their common English meaning. Words not capitalized have their common English meaning. When terms such as “memory write” or “memory read” appear completely in lower case, they include all transactions of that type.

Register names and the names of fields and bits in registers and headers are presented with the first letter capitalized and the remainder in lower case.

PCI EXPRESS EXTERNAL CABLING SPECIFICATION, REV. 0.3

Numbers and Number Bases

Hexadecimal numbers are written with a lower case “h” suffix, e.g., FFFh and 80h. Hexadecimal numbers larger than four digits are represented with a space dividing each group of four digits, as in 1E FFFF FFFFh. Binary numbers are written with a lower case “b” suffix, e.g., 1001b and 10b. Binary numbers larger than four digits are written with a space dividing each group of four digits, as in 1000 0101 0010b.

All other numbers are decimal. Implementation Notes

Implementation Notes should not be considered to be part of this specification. They are included for clarification and illustration only.

1.5. Cable Applications

The following graph illustrates some of the external cable applications or usage models. Each application is mapped against one or more cable length and PCI Express link widths. Colors are simply used to differentiate the different applications.

Objetives of this specification include “Forward looking for future scalability”. Any list of applications is by no means intended to limit any other applications that could be conceived.

Figure 1-1: External Cable Application Matrix

PCI EXPRESS EXTERNAL CABLING SPECIFICATION, REV. 0.3

NOTES:

1. A split-system, or disaggregate PC, might have a desktop “console” that contains a removable media drive (e.g. CD/DVD), I/O ports (e.g. USB, 1394), and audio jacks.

2. I/O expansion with narrower link widths (e.g. x1, x4) might be used for test and measurement or instrumentation equipment racks. 3. I/O expansion with wider link widths (e.g. x8) might be used to extend the I/O card capabilities of the main system. 4. I/O expansion using optical cables might be used to support distances greater than 10m 10

5.6.7.15

between host and remote I/O expansion chassis.

Server expansion I/O might be used to support conventional PCI Express add-in cards (with or without hot-plug support) and/or Server I/O Modules (SIOM). The graphics subsystem (i.e. controller and memory) could be located external to the main system unit.

The graphics subsystem (i.e. controller and memory) could be located a substantial distance away from and external to the main system unit. This would utilize optical cabling.

PCI EXPRESS EXTERNAL CABLING SPECIFICATION, REV. 0.3

2. Electrical Overview

The electrical part of this specification covers auxiliary signals, hot insertion and removal, and cabled PCI Express electrical budgets. The PCI Express Transmitter and Receiver electrical requirements are specified in the PCI Express Base Specification.

Besides the signals that are required to transmit/receive data on the PCI Express interface, there are also signals that may be necessary to implement the PCI Express interface in a system environment, or to provide certain desired functions, including power for data conditioning within the connector receptacle. These signals are referred to as the auxiliary signals. They include:

Cable Reference Clock (CREFCLK) Cable Presence Detect Power

2.1. PCI Express Signals

Each PCI Express lane consists of a pair of differential signals. The transmitter pair is labeled

PETpN and PETnN where N is the lane number (starting with 0); “p” is the true signal while “n” is the complement signal. The transmitter pair originates in the host system or upstream device and is connected to a receiver pair at the endpoint or downstream device. The receiver pair is labeled PERpN and PERnN with the same labeling convention as the transmitter pair. The receiver pair originates in the endpoint or downstream device.

The \"p\" and \"n\" connections may be reversed to simplify PCB trace routing and minimize vias if needed. All PCI Express receivers incorporate automatic Polarity Inversion as part of the Link Initialization and Training and will correct the polarity independently on each lane. Refer to Section 4.2.4 in the PCI Express Base Specification.

Lane reversal is an optional feature within the PCI Express Base specification and must not be relied upon unless a particular product taking advantage of this is guaranteed to support this feature.

2.1.1. Interconnect

In the context of this specification, the interconnect is comprised of everything between the pins of a Transmitter package and the pins of a Receiver package. This consists of traces on printed circuit boards, cable, AC coupling capacitors and connectors. The interconnect total capacitance to ground seen by the Receiver Detection circuit (see Section 4.3.1.8 of the PCI Express Base specification) must not exceed 3 nF, including capacitance added by attached test instrumentation. Note that this capacitance is separate and distinct from the AC Coupling capacitance value (see Section 2.1.2.1).

PCI EXPRESS EXTERNAL CABLING SPECIFICATION, REV. 0.3

2.1.1.1. Link Definition

Typical cabled PCI Express Links, from source to destination, consist of the following: • Transmitters on an ASIC on a printed circuit board • Package fan-in-out trace topologies

• PCB coupled microstrip and/or stripline traces • Vias for layer changes • External cable mated connector • External cable

• External cable mated connector

• Coupled microstrip line and/or stripline traces • AC-coupling capacitors

• Package fan-in-out trace topologies

• Receivers on an ASIC on a printed circuit board

The electrical parameters for the Link are subdivided into three components. Note that for

validation purposes the separation is somewhat different to facilitate ease of connecting any test & measurement equipment.

• Upstream subsystem interconnect • Cable including mated connectors • Downstream subsystem interconnect

Upstream Subsystem Cable InterconnectDownstream Subsystem TX LUT LCLDRRX RX LUR LCLDTTX AC Coupling

Figure 2-1: Link and Loss Definition

PCI EXPRESS EXTERNAL CABLING SPECIFICATION, REV. 0.3

2.1.2.

Electrical Budgets

A budget is incorporated for each of the following electrical parameters associated with the Link: • AC coupling capacitors

• Insertion Loss (Voltage Transfer Function) • Jitter • Bit-to-bit skew • Crosstalk

• Transmitter de-emphasis • Skew within a differential pair

The electrical budgets are different for two of the three Link components: • Upstream and Downstream subsystem • Cable and connector budgets

The interconnect Link budget allocations associated with the Transmitters and Receivers differ. This is to account for any electrical characteristics the AC coupling capacitors may contribute to the Link.

2.1.2.1. AC Coupling

Each Lane of a Link must be AC coupled. The requirement for the inclusion of AC coupling capacitors on the interconnect media is specified at the Receiver for external cabled applications. Cable and other media losses result in reduced signal swing and rise/fall time at the receiver and as such placing the AC coupling capacitors downstream reduces the risk of standing waves due to

impedance mismatches. Suggested is a maximum 0603-type (or smaller 0402-type) capacitor package size with a value as specified in the PCI Express Base Specification. Any additional attenuation or jitter caused by the coupling capacitors of packages larger than 0603 must be accounted for as part of the budget allocation for the physical interconnect path of that particular component on which the capacitors are mounted. The electrical budgets allocated for the AC coupling capacitors are defined in the following subsections. The allocated budget includes the electrical parasitic effects associated with the component’s placement as mounted on the printed circuit board.

2.1.2.2. Insertion Loss

The maximum loss values in dB (decibels) are specified for the subsystem boards and the cable. The insertion loss values for a Subsystem are defined as the ratio of the voltage at the ASIC package pin and the voltage at the PCI Express cable connector interface, terminated by 100 Ω differential

PCI EXPRESS EXTERNAL CABLING SPECIFICATION, REV. 0.3

termination, realized as two 50 Ω resistances. These resistances are referenced to ground at the interface. The maximum loss value in dB (decibels) for the cable is defined as the ratio of the source voltage at one end of the cable and the output voltage, terminated by 100 Ω differential termination, realized as two 50 Ω resistances, at the other end. The cable loss budget includes mated connectors at both ends.

IMPLEMENTATION NOTE

Usage of Loss Budget

Loss budgets have been provided as guidance for product development. Final product validation is to be performed against provided eye patterns and detailed specifications of the cable assembly.

NOTE: All loss budget values are preliminary and subject to change in future revisions of this specification!!! Table 2-1: Allocation of Interconnect Path Insertion Loss Budget

Loss Parameter Total Loss Crosstalk Subsystem

Symbol LT LUT/DT LUR/DR

Cable and Connectors Notes:

1. All values are referenced to 100 Ω, realized as two 50 Ω resistances. The loss budget values include all possible

crosstalk impacts (near-end and far-end) and potential mismatch of the actual interconnect with respect to the 100 Ω reference load.

The PCI Express Base Specification allows an interconnect loss of 13.2 dB for 2.5 Gbps (non de-emphasized) signals and 9.2 dB for 625 MHz (de-emphasized) signals. The allocated loss budget values in the table directly correlate to the eye diagram voltages in Section TBD. Tradeoffs in terms of attenuation, crosstalk, and mismatch can be made within the budget allocations specified.

Loss Budget Value at 2.5 Gbps (dB) < 13.20 < 3.20 < 1.50 < 1.75 < 6.75

Loss Budget Value at 625 MHz (dB) < 9.20 < 2.00 < 0.80 < 1.00 < 5.40

Notes 1, 3 Comments Note 1

Notes 1, 2

Unlike some PCI Express based form factors this external cable specification does not provide a safety loss budget.

2. Subsystem budgets are provided for one end of the Link. For total subsystem losses the RX and TX budgets are

added for each half of a lane. The receiver budget includes AC coupling capacitors attenuation. No specific trace geometry is explicitly defined in this specification. The subscripts of the Symbol designators, T and R, represent the Transmitter and Receiver respectively and U and D represent the Upstream and Downstream subsystem respectively. 3. The cable loss budget includes both mated connectors including their footprint. Refer to Section xx.xx for

specifics on the standalone cable budget and detailed specification.

Note: The insertion loss budget distributions above are used to derive the eye diagram heights as described in Section TBD. However, they are provided here only as a design guideline. Compliance measurements must be verified against eye diagrams.

PCI EXPRESS EXTERNAL CABLING SPECIFICATION, REV. 0.3

2.1.2.3. Jitter Budget

The maximum jitter values in terms of percentage of Unit Interval (UI = 400 ps for

2.5 G transfers/s) are specified for the subsystem boards and the cable. The jitter values are defined with respect to 100 Ω differential termination, realized as two 50 Ω resistances. These resistances are referenced to ground at the interface.

Alignment with measurement is achieved through including the PCI Express Transmitter jitter budget within the below allocations. Transmitter jitter measurements are performed at the output side of the cable connector and, similar to the validation procedure, includes a mated connector. Jitter measurement of the cable assembly is performed at the, from the transmitter, opposite end of the cable. Therefore includes both the transmitter budget and the true cable budget. Below budget specifies the sum only. Note however that this measurement is not intended to be a

validation procedure for the cable assembly. Cable assembly requirements and test are provided in a separate chapter.

IMPLEMENTATION NOTE

Jitter Budget

The media jitter budget effectively is specified at 0.2UI or 80 picoseconds at 2.5Gbps. Through specification of the jitter summation some of the DDJ (Data Dependent Jitter) is included with the transmitter output. Any DDJ and crosstalk induced jitter from the cable can be controlled while the jitter budget for the receiver PLL is maximized to cover some Reference Clock induced jitter.

Transmitting Subsystem Cable InterconnectReceiving Subsystem20

TX RX JR JT JC25

Figure 2-2: Jitter Measurement Table 2-2: Allocation of Jitter Budget

Jitter Parameter TX Subsystem Cable Assy RX Subsystem

Symbol JT JC JR

Jitter Budget Value (UI) <= 0.35 <= 0.45 <= 0.50

Comments Notes 1, 2 Notes 1, 3

Notes:

PCI EXPRESS EXTERNAL CABLING SPECIFICATION, REV. 0.3

1. All values are referenced to 100 Ω, realized as two 50 Ω resistances. The jitter budget values include

all possible crosstalk impacts (near-end and far-end) and potential mismatch of the actual interconnect with respect to the 100 Ω reference load. The total jitter budget of 0.50UI includes the Transmitter and interconnect budget, reserving 0.50UI for the Receiver component.

2. All values are referenced to 100 Ω. The Transmitter budget includes the Transmitter silicon, subsystem

interconnect and one mated connector. No specific trace geometry is explicitly defined in this specification. 3. All values are referenced to 100 Ω. The jitter budget at the far side of the cable includes both mated connectors

and the physical cable. No guard band is defined within the jitter budgets.

Note: The jitter budget distributions above are used to derive the eye diagram widths as described in Chapter TBD. Compliance measurements must be verified against the eye diagrams themselves as defined in Section TBD.

2.1.2.4.

Crosstalk

All add-in card designs must properly account for any crosstalk that may exist among the various pairs of differential signals and other signals alike. Crosstalk may be either near-end (NEXT) or far-end (FEXT). Each crosstalk component can have potential impact on a design and must be planned for accordingly.

Note that the total maximum crosstalk that a Receiver component in Electrical Idle is required to tolerate is < 65 mV as dictated by the Electrical Idle Detect Threshold in the PCI Express Base Specification. Additionally, crosstalk between differential pairs on the interconnect will influence and impact the data signals and any subsequent loss and jitter budgets as noted in Sections 2.1.2.2 and 2.1.2.3. Note that eye diagrams in Section TBD account for any and all crosstalk allowed.

2.1.2.5. Lane-to-Lane Skew

The skew at any point is measured using zero crossings of differential voltage of the compliance pattern, while simultaneously transmitting on all physical Lanes. The compliance pattern is defined in the PCI Express Base Specification.

Table 2-3: Allowable Interconnect Lane-to-Lane Skew

Skew Parameter Total Interconnect Skew

Symbol

Skew Values 1.6 ns

Comments

This does not include Transmitter output skew,

LTX-SKEW (specified in the PCI

Express Base Specification). The total skew at the Receiver (ST + LTX-SKEW ) smaller than LRX-SKEW (specified in the PCI Express Base Specification) to minimize latency for this interconnect topology.

Estimates about a 2-inch trace length delta on FR4 boards.

PCI Express Subsystem

0.35 ns

PCI EXPRESS EXTERNAL CABLING SPECIFICATION, REV. 0.3

Cable

1.25 ns

2.1.2.6. Equalization

To reduce ISI, 3.5 dB (+/-0.5 dB) below the first bit de-emphasis in the Transmitter is required as defined within Chapter 4 in the PCI Express Base Specification.

IMPLEMENTATION NOTE

Additional Equalization

For different interconnects 3.5dB de-emphasis might not be optimal. Implementation of passive or active equalization, although allowed, is beyond the scope of this specification. Note that any such implementation must meet any and all requirements provided within the PCI Express Base Specification and the ones set forth within this document.

2.1.2.7. Skew within the Differential Pair (intra-pair skew)

The skew within the differential pair gives rise to a common-mode signal component, which can, in turn, increase Electromagnetic Interference (EMI). The differential pair(s) on a Subsystem printed circuit board should be routed such that the skew within differential pairs is less than 5 mils. Intrapair skew of the cable assembly is more difficult to control and tight specifications result in increased cost. A maximum skew of 80psec is recommended for the cable assembly although it is left up to the application to make appropriate cost/performance tradeoffs. Generally speaking a skew less than the signal rise/fall time results in tolerable signal degradation whereas a skew greater than the signal rise/fall time can place serious limits on cable performance. No specific budgets have been provided for intrapair skew of the cable assembly as these are incorporated with the overall cable assembly budgets.

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2.1.3. Eye Diagrams Compliance Measurements

Eye diagrams are measured using an adapter specifically designed for such purpose. This adapter allows for easy probing and termination of the PCI Express signals, resulting in the device under test automatically entering its compliance mode as dictated by the PCI Express Base specification.

2.1.3.1. Transmitter Compliance Eye

Compliance testing of a subsystem transmitter output includes routing on the compliance adapter and, as a result, one mated connector. The transmitter path compliance eye requirements include 1dB loss budget, at 1.25GHz, for these additional components.

Table 2-4: Transmitter Path Compliance Eye Requirements

Parameter Value Notes VtxA VtxA_d TtxA

>= 600mV >= 432mV >= 260 ps 1 1 1, 2

1. All Links are assumed active while generating this eye diagram. Transition and non-Transition

bits must be distinguished in order to measure compliance against the de-emphasized voltage level (VtxA_d).

2. The eye diagram is defined and centered with respect to the jitter median. The jitter median

should be calculated across any 250 consecutive UIs as defined within the PCI Express Base specification.

Figure 2-3: External Cable Application Matrix

PCI EXPRESS EXTERNAL CABLING SPECIFICATION, REV. 0.3

2.1.3.2. Receiver Compliance Eye

Receiver compliance eye measurements are performed at the opposite end of the cable from the transmitter’s perspective. This creates the complexity that not all cables are created equal. Detailed cable assembly specifications are provided within this document in an effort to prevent potential compatibility issues.

Table 2-5: Receiver Path Compliance Eye Requirements

Parameter Value Notes VrxA VrxA_d TrxA

>= 214mV >= 197mV >= 220 ps 1 1 1, 2

1. All Links are assumed active while generating this eye diagram. Transition and non-Transition

bits must be distinguished in order to measure compliance against the de-emphasized voltage level (VrxA_d).

2. The eye diagram is defined and centered with respect to the jitter median. The jitter median

should be calculated across any 250 consecutive UIs as defined within the PCI Express Base specification.

3. Measurements taken at the cable connector point.

Figure 2-4: External Cable Application Matrix

2.2. Auxiliary Signals

Cabled PCI Express applications utilizing “generic” off-the-shelf silicon have a need for two auxiliary signals, a cable reference clock and presence detect mechanism. For the purposes of this specification power provisioning to any signal conditioning components that might be included within the cable connector receptacle is also considered an auxiliary signal. Following paragraphs provide the electrical requirements.

PCI EXPRESS EXTERNAL CABLING SPECIFICATION, REV. 0.3

2.2.1. Cable Reference Clock

To reduce jitter, control radiated emissions and crosstalk, and allow for future silicon fabrication process changes, a low voltage swing, differential clock is being used, as illustrated in Figure 2-5: Differential CREFCLK Waveform

Isolated power domains, between the two subsystems, are maintained through implementation of AC-Coupling capacitors at the source. Both source and load termination are implemented to reduce signal reflections and improve signal quality.

Hot insertion is supported through the “Present Detect” mechanism described within the following sections. Any Cable Reference Clock shall be disabled at the source unless both sides of the Link are powered and the cable is installed, preventing any glitches and excessive EMI that could result from unterminated signals. Also note that components might be sensitive, and damage can result, to providing a clock signal while power rails are not at their normal operating level.

IMPLEMENTATION NOTE

Use of System Reference Clock

This specification makes no assumptions on the clock signaling provided from a system clock

generator to a potential cable driver. It is the responsibility of the designer to provide any necessary signal translation based on the target implementation; i.e. Base board, PCI Express add-in cards, or any future form factors supported with PCI Express signaling. Only the cable reference clock is specified herein.

IMPLEMENTATION NOTE

Cable Reference Clock Termination

Double termination, at the source and load, will reduce the nominal swing and rise and fall times. The lower input swing and lower slew rates need to be validated against the clock receiver

requirements, provided within this document, as they can increase jitter in some clock input buffer designs.

2.2.1.1. Clocking Dependencies

The Ports on both ends of a Link must transmit data at a rate that is within 600 parts per million (ppm) of each other at all times. This is specified to allow bit rate clock sources with a +/- 300 ppm tolerance. 2.2.1.1.1.

Spread Spectrum Clock (SSC) Sources

The data rate can be modulated from +0% to -0.5% of the nominal data rate frequency, at a modulation rate in the range not exceeding 30 kHz – 33 kHz. The +/- 300 ppm requirement still holds, which requires the two communicating Ports be modulated such that they never exceed a

PCI EXPRESS EXTERNAL CABLING SPECIFICATION, REV. 0.3

total of 600 ppm difference. For most implementations this places the requirement that both Ports require the same bit rate clock source when the data is modulated with an SSC.

2.2.1.2. AC-Coupling

The Cable Reference Clock shall be AC-Coupled at the Subsystem sourcing the differential

clock. Generally this clock is sourced from the upstream subsystem. A recommended value is 0.1uF although other capacitor values are allowed within the signal integrity and rise/fall time

specifications provided within Section 2.2.1.3. The 100MHz cable reference clock can contain SSC frequency components that need to be taken into consideration when chosing a capacitor value for AC Coupling.

2.2.1.3. Cable Reference Clock Specification

Following tables provide the signaling requirements at the connectors for the clock source and the worst-case differential signalling a receiver should expect.

Table 2-6: Transmitter AC Timing Requirements

Rise Edge Rate Fall Edge Rate Vcross Vcross Delta Vrb Tstable Tperiod avg Tperiod abs Tccjitter Vmax Vmin

Duty Cycle Rise-Fall Matching ZC-DC

Rising Edge Rate Falling Edge Rate

Absolute crossing point voltage Variation of Vcross over all rising clock edges

Ring-back Voltage Margin Time before Vrb is allowed Average Clock Period Accuracy Absolute Period (including Jitter and Spread Spectrum) Cycle to Cycle jitter Absolute Max voltage Absolute Min voltage

Duty Cycle

Rising edge rate (Clock) to falling edge rate (Clock#) matching Clock DC impedance

2.0 5.0 V/ns 2, 3 2.0 5.0 V/ns 2, 3 +250

+550

1,4,5

+140 mV 1,4,9 -100 +100 mV 2,12 TBD500 ps 2,12 -300 +2800 ppm 2,10,13 9.847 10.203 ns 2,6

+1.15 V 1,7 - 0.3 V 1,8

40 60 % 2 20 % 1,14 40 60 Ω

1,11

PCI EXPRESS EXTERNAL CABLING SPECIFICATION, REV. 0.3

Table 2-7: Receiver AC Timing Requirements

Rise Edge Rate Fall Edge Rate Vih Vil Vcross Vcross Delta Vrb Tstable Tperiod avg Tperiod abs Tccjitter Vmax Vmin

Duty Cycle Rise-Fall Matching ZC-DC Notes:

1. Measurement taken from single ended waveform. 2. Measurement taken from differential waveform.

Rising Edge Rate Falling Edge Rate

Differential Input High Voltage Differential Input Low Voltage Absolute crossing point voltage Variation of Vcross over all rising clock edges

Duty Cycle

Rising edge rate (Clock) to falling edge rate (Clock#) matching Clock DC impedance

1.0 4.0 V/ns 2, 3 1.0 4.0 V/ns 2, 3 +150 mV 2 -150 mV 2 +250

+550

1,4,5

+140 mV 1,4,9 -100 +100 mV 2,12 TBD500 ps 2,12 -300 +2800 ppm 2,10,13 9.847 10.203 ns 2,6

60 +1.15 - 0.3

ps V V

2 1,7 1,8

40 60 % 2 20 % 1,14 40 60 Ω

1,11

3. Measured from -150 mV to +150 mV on the differential waveform (derived from Clock – Clock#). The signal

must be monotonic through the region for Trise and Tfall. The 300 mV measurement window is centered on the differential zero crossing. See Figure 2-8. . 4. Measured at crossing point where the instantaneous voltage value of the rising edge of CREFCLK equals

the falling edge of CREFCLK#. See Figure 2-4..

5. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is

crossing. Refers to all crossing points for this measurement. See Figure 2-4.. 6. Defines as the absolute min or maximum instantaneous period. This includes cycle to cycle jitter, relative

PPM tolerance and spread spectrum modulation. See Figure 2-7.. 7. Defined as the maximum instantaneous voltage including overshoot. See Figure 2-4..

15 8. Defined as the minimum instantaneous voltage including undershoot. See Figure 2-4..

9. Defined as the total variation of all crossing voltages of Rising CREFCLK and Falling CREFCLK#. This is

the maximum allowed variance in Vcross for any particular system. See Figure 2-5.. 10. Refer to Section 4.3.2.1 of the PCI Express Base Specification for information regarding PPM

considerations.

11. System board compliance measured at the connector using the circuit of Figure 2-10.. Clock and Clock#

are to be measured at the load capacitors Cl. Single ended probes must be used for measurements requiring single ended measurements. Either single ended probes with math or differential probe can be used for differential measurements. Test load Cl = 2pF.

PCI EXPRESS EXTERNAL CABLING SPECIFICATION, REV. 0.3

12. Tstable is the time the differential clock must maintain a minimum ±150 mV differential voltage after

rising/falling edges before it is allowed to droop back into the Vrb ±100 mV differential range. See Figure 2-9..

13. PPM refers to parts per million and is a DC absolute period accuracy specification. 1 PPM is 1/1,000,000th

of 100.000000 MHz exactly or 100 Hz. For 300PPM then we have a error budget of 100 Hz/PPM * 300PPM = 30KHz. The period is to be measured with a frequency counter with measurement window set to 100mS or greater. The ±300 PPM applies to systems that do not employ Spread Spectrum or that use common clock source. For systems employing Spread Spectrum there is an additional 2500 PPM nominal shift in maximum period resulting from the 0.5% down spread resulting in a maximum average period spec of +2800 PPM 14. Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a

±75mV window centered on the median cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. The Rise Edge Rate of Clock should be compared to the Fall Edge Rate of Clock#, the maximum allowed difference should not exceed 20% of the slowest edge rate. See Figure 2-6..

Clock#Vcross max = 550mVV max = 1.15VV max = 1.15VVcross max = 550mVVcross min = 250mVVcross min = 250mVClockV min = -0.30VV min = -0.30V Figure 2-5: Differential CREFCLK Waveform

Clock#Vcross delta = 140mVVcross delta = 140mVClock

Figure 2-6: Single-Ended Measurement Points for Delta Cross Point

Clock#Clock#Vcross median +75mVTriselalTfVcross medianVcross medianVcross median -75mV20

ClockClock Figure 2-7: Single-Ended Measurement Points for Rise and Fall Time Matching

PCI EXPRESS EXTERNAL CABLING SPECIFICATION, REV. 0.3

Clock Period (Differential)Positive Duty Cycle (Differential)Negative Duty Cycle (Differential)0.0V0.0V

Clock-Clock#

Figure 2-8: Differential Measurement Points for Duty Cycle and Period

RiseEdgeRateFallEdgeRateVih = +150mV0.0VVil = -150mVVih = +150mV

0.0VVil = -150mV

Clock-Clock#

Figure 2-9: Differential Measurement Points for Rise and Fall Time

TstableVrbVih = +150mVVrb = +100mV0.0VVrb = -100mV0.0VVrb = -100mV

Vil= -150mVTstableVrbVrb = +100mV

Clock-Clock#5

Figure 2-10: Differential Measurement Points for Ringback

Clock DriverRsL1L1'RsCl=2pfCl=2pfL3'RtL3L2L2'L4L4'PCI ExpressConnectorPCI Express Add CardTest LoadL5=1\"L5'=1\"ClockClock#Figure 2-11: Reference Clock System Measurement Point and Loading

In the case of a Subsystem containing multiple external cable interfaces, the reference clock pair is routed point-to-point to each cable connector. The phase relationships of the clocks to the connectors are not specified. The clocks must be routed according to best-known clock routing

PCI EXPRESS EXTERNAL CABLING SPECIFICATION, REV. 0.3

rules. The routing of each signal in any given clock pair between the clock source, or buffer, and the connector must be well matched in length (< 0.005 inch) and appropriately spaced away from other signals to avoid excessive crosstalk.

2.2.1.3.1. Impact of Jitter on Bit Error Rate (BER)

An increase in Bit Error Rate (BER) can result from the phase jitter content on the cable reference clock. The potential increase in eye closure can also be dependent on the round-trip delay of the cabled Link, rise/fall time degradation of the reference clock and implementation specific Clock Data Recovery circuits of PCI Express components in addition to the losses induced by the Link. Thorough system level jitter consideration and simulation is recommended.

2.2.2. Cable Presence Detect

An optional round-trip presence detect mechanism is provided for support of Hot Plug, to some extend control EMI, to allow for Power Good signaling between the two subsystems, and end-user diagnostics.

PCI Express components could potentially be damaged due to providing a cable reference clock while its power provisioning is not at normal operating levels. Gating of the cable reference clock, using the presence detect mechanism, is required by this specification to prevent reliability problems. Although AC-Coupling (DC-Blocking) is not implemented, power domain isolation between the upstream and downstream subsystems must be guaranteed by design.

Use Cases:

• Support Hot Plug • Power Good signaling • Cable reference clock control

• Dynamic power sequencing of downstream subsystem • End-user diagnostics

PCI EXPRESS EXTERNAL CABLING SPECIFICATION, REV. 0.3

IMPLEMENTATION NOTE

Presence Detect example

The figure below provides a functional diagram of a Presence Detect mechanism. This is by no means intended to specify the implementation, it is merely providing additional description. Note that this example circuit provides an indication to the upstream device that the downstream device is present and powered. It does not illustrate a mechanism to provide an indication to the downstream device that the upstream device is present and powered.

Figure 2-12: Present Detect Functional Diagram

2.2.2.1. +Vupstream

+Vupstream is sourced from the upstream device signaling that it is powered. During normal, non-Hot Plug power sequencing this does not necessarily indicate that a valid reference clock can be provided. This is dependent on host system (upstream subsystem) power and reset sequencing requirements and implementation.

+Vupstream has a timing relationship to the system Power Good indicator. Any necessary short circuit and ESD protection shall be implemented for safety and other application specific regulatory requirements.

2.2.2.2. +Presence

+Presence is a feedback path for the +Vupstream signal provided from the host system. This feedback path is enabled if the downstream subsystem is ready to accept a reference clock. During normal, non-Hot Plug power sequencing this does not necessarily indicate that a valid reference clock can be provided. This is dependent on host system (i.e. upstream subsystem) power and reset sequencing requirements. +Presence going active has a timing relationship with both the upstream, through the +Vupstream signal, and downstream subsystem Power Good status.

PCI EXPRESS EXTERNAL CABLING SPECIFICATION, REV. 0.3

2.2.2.3. DC Specifications

The +Vupstream and +Presence signals must meet the DC specifications listed in Table 2-6. All

parameters are specified at the pins of the cable connector on the upstream subsystem at an ambient temperature of 25°C.

Table 2-8: Cable Present Detect DC Specifications

Symbol Parameter Conditions Vout Vin

Output Voltage Input Voltage

10mA load Cable attached

Min Max Unit Notes V 1,3 V 2 mA 1,2 2.2 Vout – 2.0

Vout – 0.2

Icd Current

2.5 10

Notes:

1. Applies to +Vupstream

2. Applies to +Presence

3. Vout should be chosen such that there is a sufficient, detectable voltage difference (measured as Vin)

between an attached cable situation and a detached cable situation.

2.2.2.4. Power-up Timing of Cabled Slave Subsystem

A Cabled Slave Subsystem (CSS) is defined as any downstream device connecting via an external cable with a host (upstream subsystem) and relies on delivery of a reference clock via this cable. Such CSS devices can have separate power provisioning from the upstream subsystem, resulting in undeterministic power sequencing. This section describes sequencing requirements of the Cabled Slave Subsystem.

On power up, the de-assertion of PERST# (PCI Express Reset within the CSS) is delayed (by

TPVPERL) from the CSS power rails achieving specified operating limits to allow adequate time for the power to stabilize on the CSS and certain functions to start prior to the module starting up. PERST# is de-asserted if the following conditions have been met.

1. Power rails have been valid for a minimum of 100ms.

2. A valid cable reference clock has been available for a minimum of 100us.

Additionally, some CSS implementations may require detection of the presence and power up status of the upstream subsystem. In such implementations two additional requirements are placed on the de-assertion of PERST#:

1. +Vupstream has been active for a minimum of 50ms. 2. +Presence has been enabled for a minimum of 50ms.

PCI EXPRESS EXTERNAL CABLING SPECIFICATION, REV. 0.3

Figure 2-13: Power-up Timing Slave Device Table 2-9: Power-up Timing Slave Device

Symbol Parameter Min Max Units NotesTPVPERL TPERST#-CLK

Power stable to PERST# inactive CREFCLK stable before PERST# active

100 100

ms us

1 2

1. This value does not include any additional timing requirements due to the CSS sensing of the upstream subsystem’s presence and power up status.

2. The CREFCLK is stable when it meets the requirements specified for the cable reference clock.

IMPLEMENTATION NOTE

Cabled Slave Power-up Timing

Some timing relationships can be assumed dependent on the specifications of the target form factor. The subsystem designer needs to insure that the critical parameters, such as power rails and reference clock valid, are being met.

2.2.3.

Power

2.2.4.

ESD

All signal and power pins must withstand 2000 V of ESD using the human body model and 500 V using the charged device model without damage, Class 2 per JEDEC JESE22-A114-A.

PCI EXPRESS EXTERNAL CABLING SPECIFICATION, REV. 0.3

2.3. L2 Power State Transition

Note that the WAKE# sideband signal is not supported with cabled PCI Express. Any application requiring the downstream subsystem to enter and return, through a wakeup event, from the L2 power state must implement the in-band Beacon protocol via the cable.

IMPLEMENTATION NOTE

Beacon/WAKE# conversion

It may be necessary for the downstream subsystem to convert a local source of a WAKE# sideband signal (e.g. if there are PCI Express add-in card slots in that subsystem) to the in-band Beacon protocol for transmission across the PCI Express cable. Similarly, the upstream subsystem may be required to convert the in-band Beacon protocol to a WAKE# sideband signal depending upon the form factor and capabilities of that subsystem.

PCI EXPRESS EXTERNAL CABLING SPECIFICATION, REV. 0.3

3. Cable Connector Definition

This document defines four distinct connector link widths. These are: x1, x4 (includes x2), x8 and x16. One cable connector will be defined for each of these four link widths. The x4 version is a special case in that it includes support for a x2 link width. It is expected that implementers may choose to create an x2 cable that utilizes x4 connectors.

3.1. Signal Description

3.1.1. 3.1.2. 3.1.3.

PCI Express CREFCLK Presence Detect Power

3.1.4.

3.2. Board Connector

3.2.1. 3.2.2.

Description

Physical and Mechanical Performance

Table 3.1 lists the mechanical performance requirements for PCI Express board connectors.

Symbol Parameter minimum maximum Units Conditions/Comments N N Fi Insertion force Tw Withdrawal force 30

PCI EXPRESS EXTERNAL CABLING SPECIFICATION, REV. 0.3

Fr Retention force Fls Side load capability

N 75 N Fll Longitudinal load 100 N capability Frc Housing contact N retention force Table 3.1 Connector physical and mechanical performance requirements

Table 3.2 defines the durability (insertion and withdrawal) cycle requirements for PCI Express board connectors. It is recommended that the contacts be a plated with a minimum of 0.76 µm (30 microinches) of Gold over 1.27 µm of Nickel to achieve the required durability performance. Cable link width x2, x4

Durability cycles 250

Comment 5

x1 1500

x8 250 x16 500 Table 3.2 Connector durability requirements

3.2.3. Electrical Performance

Table 3.3 lists the electrical performance requirements for PCI Express mated board and cable connectors.

Symbol Parameter minimum maximum Units Conditions/Comments LLCR Low-level contact 80 mOhms resistance - initial ∆LLCR

Low-level contact 10 mOhms resistance - change

Imax Contact current A rating

PCI EXPRESS EXTERNAL CABLING SPECIFICATION, REV. 0.3

Table 3.3 Connector electrical performance requirements

3.2.4. Environmental Performance

It is recommended that board and cable connectors to be used in PCI Express systems be tested in accordance with EIA 364.1000-01, using the appropriate test sequences and the following field life conditions:

• 50 mating cycles preconditioning

• Unmated exposure, option 2 mixed flowing gas exposure • Five year product life

• Field operating temperature range up to 60 degrees C.

3.2.5. x1 Link

3.2.5.1. Description 3.2.5.2. Pinout

3.2.6.

x4 Link

3.2.6.1. Description 3.2.6.2. Pinout

3.2.7. x8 Link

3.2.7.1. Description

3.2.7.2. Pinout

PCI EXPRESS EXTERNAL CABLING SPECIFICATION, REV. 0.3

3.2.8. x16 Link

3.2.8.1. Description 3.2.8.2. Pinout

3.3. Shielding

3.4. Keying

3.5. Mechanical

PCI EXPRESS EXTERNAL CABLING SPECIFICATION, REV. 0.3

4. Cable Specification

4.1. Introduction 4.2. Requirements

4.2.1.

Physical and Mechanical Performance

Table 4.1 lists the mechanical performance requirements for PCI Express cables. [Note: rollup was typically 3-5X bulk cable diam. JCD suggests an absolute number is needed.]

Symbol Parameter Rb Bend radius, x1 Bend radius, x2, x4 Bend radius, x8 Bend radius, x16 minimummaximum Units Conditions/Comments mm mm mm mm Table 4.1 Cable physical and mechanical performance requirements

4.2.2.

Electrical Performance

minimum maximum UnitsConditions/Comments Table 4.2 lists the electrical performance requirements for Gen 1 PCI Express cables.

Symbol Parameter Lca RLc Return Loss -12 dB f<3.125 GHz Insertion loss, Gen. 1 8.15 dB f<563 MHz 0.267*√f dB +0.0035*f

f=563 MHz to 1.25 GHz 34

PCI EXPRESS EXTERNAL CABLING SPECIFICATION, REV. 0.3

NEXTc (x1, x2/x4) Near end crosstalk (x1, x2/x4 cables)

3 % All physically adjacent neighbors driven with maximum transition time of 0.25 UI

All physically adjacent neighbors driven with maximum transition time of 0.25 UI

Each pair measured relative to CREFCLK pair

All physically adjacent neighbors driven at the receive end with 2^7-1 PRBS at minimum rate of 0.6 link speed with 1.2 V unsigned differential amplitude and maximum transition time of 0.25 UI Measured at half bit time, with all physically adjacent neighbors driven at the receive end with 2^7-1 PRBS at minimum rate of 0.6 link speed with 1.2 V unsigned differential amplitude and maximum transition time of 0.25 UI

NEXTc ( x8, Near end crosstalk x16)

(x8, x16 cables) FEXTc Far end crosstalk 4 %

4 % S In-pair skew 100 ps Scal Jca Pair to pair skew Jitter 2 0.20 UI UI Vcout Eye height, Gen. 1 196 mV Table 4.2 Cable electrical performance requirements

4.2.3. Environmental Performance

4.3. Connector Description

4.3.1.

x1 Link

4.3.1.1. Description 4.3.1.2. Pinout

PCI EXPRESS EXTERNAL CABLING SPECIFICATION, REV. 0.3

4.3.2. x4 Link

4.3.2.1. Description 4.3.2.2. Pinout

4.3.3. x8 Link

4.3.3.1. Description 4.3.3.2. Pinout

4.3.4.

x16 Link

4.3.4.1. Description 4.3.4.2. Pinout

Measurement Upstream or A TX RX JCC Coupling reference point at Downstream UTDRDTUR the connector Subsystem surface mount pads. The pads are considered 4.4. Shielding part of the cable 4.5. Keying

4.6. Labeling 4.7. Mechanical

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