【例3-1】 2选1多路选择器程序。
（P31）
LIBRARY IEEE; --IEEE库使用说明语句 USE IEEE.STD_LOGIC_11.ALL;
ENTITY mux21 IS --实体说明部分 PORT( a,b : IN STD_LOGIC; s: IN STD_LOGIC; y: OUT STD_LOGIC );
END ENTITY mux21;
ARCHITECTURE mux21a OF mux21 IS --结构体说明部分 BEGIN PROCESS(a,b,s) BEGIN IF s='0' THEN y<=a; ELSE y<=b; END IF; END PROCESS; END ARCHITECTURE mux21a;
【例3-2】 有类属说明的2输入与非门的实体描述。
ENTITY nand2 IS
GENERIC ( t_rise : TIME := 2ns ; t_fall : TIME := 1ns ) PORT( a: IN BIT; b : IN BIT; s : OUT BIT); END ENTITY nand2;
（P33）
【例3-3】 n输入与非门的实体描述：
ENTITY nand_n IS
GENERIC ( n : INTEGER ) ;
PORT( a : IN STD_LOGIC_VECTOR(n-1 DOWNTO 0); s : OUT STD_LOGIC ); END ENTITY nand_n;
（P33）
例3-4】 半加器的完整VHDL描述，其中x、y为加数与被加数，s为和信号，c为进位信号。 （P36）
ENTITY half_adder IS PORT( x,y : IN BIT; s: IN BIT; c: OUT BIT); END ENTITY half_adder;
ARCHITECTURE dataflow OF half_adder IS BEGIN
s <= x XOR y; c <= x AND y;
END ARCHITECTURE dataflow;
【例3-5】 2选1多路选择器的行为描述程序。
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_11.ALL; ENTITY mux21 IS PORT( a,b : IN STD_LOGIC; s: IN STD_LOGIC; y: OUT STD_LOGIC );
END ENTITY mux21;
ARCHITECTURE behav OF mux21 IS BEGIN PROCESS(a,b,s) BEGIN IF s='0' THEN y<=a; ELSE y<=b; END IF; END PROCESS; END ARCHITECTURE behav;
【例3-6】 2选1多路选择器数据流描述程序。
LIBRARY IEEE; USE IEEE.STD_LOGIC_11.ALL;
ENTITY mux21 IS PORT( a,b : IN STD_LOGIC; s: IN STD_LOGIC; y: OUT STD_LOGIC );
END ENTITY mux21;
ARCHITECTURE dataflow OF mux21 IS BEGIN y<=(a AND (NOT s)) OR (b AND s); END ARCHITECTURE dataflow;
（P36）
【例3-7】 2选1多路选择器结构描述程序。
LIBRARY IEEE; USE IEEE.STD_LOGIC_11.ALL;
ENTITY and21 IS PORT(i0,i1 : IN STD_LOGIC; q: OUT STD_LOGIC ); END ENTITY and21;
ARCHITECTURE one OF and21 IS BEGIN
q<=i0 AND i1; END ARCHITECTURE one;
LIBRARY IEEE; USE IEEE.STD_LOGIC_11.ALL;
ENTITY or21 IS PORT(i0,i1 : IN STD_LOGIC; q: OUT STD_LOGIC ); END ENTITY or21;
ARCHITECTURE one OF or21 IS BEGIN .
（P37）
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q<=i0 OR i1; END ARCHITECTURE one;
LIBRARY IEEE; USE IEEE.STD_LOGIC_11.ALL;
ENTITY inv21 IS PORT(i0 : IN STD_LOGIC; q: OUT STD_LOGIC ); END ENTITY inv21;
ARCHITECTURE one OF inv21 IS BEGIN
q<= (NOT i0); END ARCHITECTURE one;
LIBRARY IEEE; USE IEEE.STD_LOGIC_11.ALL;
ENTITY mux21 IS PORT( a,b : IN STD_LOGIC; s: IN STD_LOGIC; y: OUT STD_LOGIC );
END ENTITY mux21;
ARCHITECTURE struct OF mux21 IS COMPONENT and21 PORT (i0,i1 : IN STD_LOGIC; q: OUT STD_LOGIC); END COMPONENT; COMPONENT or21 PORT (i0,i1 : IN STD_LOGIC; q: OUT STD_LOGIC); END COMPONENT; COMPONENT inv21 PORT (i0: IN STD_LOGIC;
q: OUT STD_LOGIC); END COMPONENT; SIGNAL tmp1,tmp2,tmp3:STD_LOGIC; BEGIN
u1: and21 PORT MAP (b, s,tmp1); u2: inv21 PORT MAP(s,tmp2); u3: and21 PORT MAP (a,tmp2,tmp3);
u4: or21 PORT MAP(tmp1,tmp3,y); END ARCHITECTURE struct;
【例3-8】 半加器的混合描述程序。
LIBRARY IEEE;
USE IEEE.STD_LOGIC_11.ALL; ENTITY xor21 IS
PORT(i0,i1:IN STD_LOGIC; q: OUT STD_LOGIC); END ENTITY xor21;
ARCHITECTURE behav OF xor21 IS BEGIN
q<=i0 XOR i1;
END ARCHITECTURE behav; LIBRARY IEEE;
USE IEEE.STD_LOGIC_11.ALL; ENTITY half_adder IS
（P37）
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PORT(a,b:IN STD_LOGIC; c,s: OUT STD_LOGIC); END ENTITY half_adder;
ARCHITECTURE mix OF half_adder IS COMPONENT xor21 IS
PORT(i0,i1:IN STD_LOGIC; q:OUT STD_LOGIC); END COMPONENT; BEGIN
c <= a AND b;
u1: xor21 PORT MAP(a,b,s); END ARCHITECTURE mix;
【例3-9】 打开一个字符文件，读出文件中的内容并关闭文件。
LIBRARY IEEE;
USE IEEE.STD_LOGIC_11.ALL; ENTITY readfile IS
PORT( cs:IN STD_LOGIC; c: OUT CHARACTER); END ENTITY readfile;
ARCHITECTURE read1 OF readfile IS BEGIN
PROCESS(cs)
TYPE char_file IS FILE OF CHARACTER; FILE cfile : char_file; VARIABLE i : INTEGER :=0; BEGIN
IF(cs='1') THEN
FILE_OPEN(cfile,\"f:/leifr/testfile.asc\ WHILE NOT ENDFILE(cfile) LOOP READ(cfile,c); i := i+1; END LOOP;
FILE_CLOSE(cfile); ELSE
c<= '- '; END IF;
END PROCESS;
END ARCHITECTURE read1;
（P51）
【例4-1】 WAIT语句示例程序。
cwait1 ： PROCESS BEGIN y <= ( a AND b ) OR ( m XOR t ) ; z <= c NAND d ; WAIT ; -- 无限等待 END PROCESS cwait1 ;
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【例4-2】 WAIT FOR语句示例程序。
cwait2 ： PROCESS BEGIN y <= ( a AND b ) OR ( m XOR t ) ; z <= c NAND d ; .
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WAIT FOR 10 * ( ct1 + ct2 ) ; -- 等待由该表达式计算的时间 END PROCESS cwait2 ;
【例4-3】 WAIT ON语句示例程序（二选一选择器）。
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; ENTITY mux2_1 IS PORT( data0, data1 : IN STD_LOGIC ; sel : IN STD_LOGIC ; q : OUT STD_LOGIC ) ; END mux2_1 ;
ARCHITECTURE behavioral OF mux2_1 IS
SIGNAL temp1, temp2, temp3 : STD_LOGIC ; BEGIN
cwait3 ： PROCESS BEGIN temp1 <= data0 AND sel ; temp2 <= data1 AND ( NOT sel ) ; temp3 <= temp1 OR temp2 ; q <= temp3 ;
WAIT ON data0, data1, q ; END PROCESS cwait3 ; END behavioral ;
（P66）
【例4-4】 WAIT ON语句和PROCESS语句中所使用的敏感信号列表的对比。 （P67）
ARCHITECTURE behavioral OF mux2_1 IS
SIGNAL temp1, temp2, temp3 : STD_LOGIC ; BEGIN
cwait4 ： PROCESS ( data0, data1, q ) BEGIN temp1 <= data0 AND sel ; temp2 <= data1 AND ( NOT sel ) ; temp3 <= temp1 OR temp2 ; q <= temp3 ; END PROCESS cwait4 ; END behavioral ;
【例4-5】 WAIT UNTIL语句示例程序。
ARCHITECTURE behavioral OF example_waituntil IS SIGNAL temp : INTEGER ; BEGIN
cwait5 ： PROCESS BEGIN
WAIT UNTIL ( ( temp + 5 ) >= 20 ) ; -- 该表达式是布尔表达式 END PROCESS cwait5 ;
END behavioral ;
（P67）
【例4-6】 多条件WAIT语句的示例程序。
cwait6 ： PROCESS BEGIN .
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-- 多条件WAIT语句
WAIT ON data0, data1,q UNTIL((temp + 5 ) >= 20) FOR 34 ns ; END PROCESS cwait6 ;
【例4-7】 信号代入语句示例程序。
ARCHITECTURE behavioral OF example_dairu IS SIGNAL a, b, c, d,e, f : STD_LOGIC ;
SIGNAL temp0, temp1, temp2, temp3, temp4, temp5 : STD_LOGIC ; BEGIN
cdairu ： PROCESS BEGIN temp0 <= a NAND b ; -- 与非 temp1 <= c NOR d ; -- 或非 temp2 <= e XOR f AFTER 5 ns ; -- 异或门延迟 temp3 <= ( a NAND b ) NOR ( c NAND d ) ; temp4 <= ( c OR d ) NAND ( e OR f ) ; temp5 <= a XOR b XOR c XOR d XOR e XOR f ; END PROCESS cdairu ; END behavioral ;
（P68）
【例4-8】 变量赋值语句示例程序。
ARCHITECTURE behavioral OF example_fuzhi IS CONSTANT cvolt : REAL : = 3.3 ; -- 定义常数 CONSTANT ccurrent : REAL : = 4.0 ;
VARIABLE temp0, temp1 : REAL ; -- 定义变量
VARIABLE temp2, temp3 : INTEGER RANGE 0 TO 255 : = 10 ; VARIABLE temp4 : STD_LOGIC_VECTOR ( 3 DOWNTO 0 ) ; VARIABLE temp5 : STD_LOGIC ;
SIGNAL a : STD_LOGIC ; -- 定义信号 SIGNAL b : REAL ; SIGNAL c : INTEGER ;
SIGNAL d : STD_LOGIC_VECTOR ( 3 DOWNTO 0 ) ; BEGIN
cfuzhi ： PROCESS BEGIN temp0 : = cvolt ; -- 变量直接赋值 temp1 : = ( cvolt + 1.8 ) * ccurrent ; -- 变量表达式赋值 temp2 : = c + 78 ; temp3 : = c / 5 ; -- 此时c必须是5的倍数 temp4 : = d ; temp5 : = temp4 ( 2 ) ; END PROCESS cfuzhi ; END behavioral ;
（P69）
【例4-9】 变量赋值和信号量代入的对比示例程序。
ARCHITECTURE behavioral OF example_duibi IS
SIGNAL d0, d1, d2, d3 : STD_LOGIC ; -- 定义信号 SIGNAL q0, q1 : STD_LOGIC ; BEGIN
cduibi_1 ：PROCESS (d0, d1, d2, d3 ) BEGIN d2 <= d0 ; -- 信号量代入 q0 <= d2 OR d3 ;
（P69）
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d2 <= d1 ; -- 信号量代入 q1 <= d2 OR d3 ; END PROCESS cduibi_1 ;
cduibi_2 ： PROCESS (d0, d1, d3 ) VARIABLE m2 : STD_LOGIC ; BEGIN m2 : = d0 ; -- 变量赋值 q0 <= m2 OR d3 ; m2 : = d1 ; -- 变量赋值 q1 <= m2 OR d3 ; END PROCESS cduibi_2 ; END behavioral ;
进程cduibi_1的运行结果：
q0 = d1 OR d3 并且 q1 = d1 OR d3 进程cduibi_2的运行结果：
q0 = d0 OR d3 而 q1 = d1 OR d3
【例4-10】 采用单IF语句来描述D触发器的示例程序。
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; ENTITY cdff1 IS PORT( d : IN STD_LOGIC ; clk : IN STD_LOGIC ; q : OUT STD_LOGIC ;
qnot : OUT STD_LOGIC ) ; END cdff1 ;
ARCHITECTURE dataflow OF cdff1 IS BEGIN
cdff_example : PROCESS ( clk ) BEGIN
IF ( clk'EVENT AND clk = '1' ) THEN -- 单IF语句 q <= d ;
qnot <= NOT d ; END IF ;
END PROCESS cdff_example ; END dataflow ;
（P71）
【例4-11】 采用二选择的IF语句来描述二选一选择器的示例程序。
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; ENTITY mux2_2 IS PORT( a0, a1 : IN BIT ; sel : IN BIT ; q : OUT BIT ) ; END mux2_2 ;
ARCHITECTURE rtl OF mux2_2 IS BEGIN
cmux2_2 : PROCESS (a0, a1, sel ) BEGIN IF ( sel = '1' ) THEN -- 二选择的IF语句 q <= a0 ; ELSE q <= a1 ;
（P72）
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END IF ; END PROCESS cmux2_2 ; END rtl ;
【例4-12】 采用多选择的IF语句来描述4选1选择电路的示例程序。
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; ENTITY mux4_1 IS PORT( a0, a1, a2, a3 : IN STD_LOGIC ;
sel : IN STD_LOGIC_VECTOR ( 1 DOWNTO 0 ) ; q : OUT STD_LOGIC ) ; END mux4_1 ;
ARCHITECTURE rtl OF mux4_1 IS BEGIN
cmux4_1 : PROCESS (a0, a1, a2, a3, sel ) BEGIN
IF ( sel = \"00\" ) THEN -- 多选择的IF语句 q <= a0 ;
ELSIF ( sel = \"01\" ) THEN q <= a1 ;
ELSIF ( sel = \"10\" ) THEN q <= a2 ; ELSE q <= a3 ; END IF ;
END PROCESS cmux4_1 ; END rtl ;
（P73）
【例4-13】 采用IF语句嵌套结构的带复位端的四选一选择器的示例程序。
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; ENTITY mux4_2 IS PORT( cdata : IN STD_LOGIC_VECTOR ( 3 DOWNTO 0 ) ; sel : IN STD_LOGIC_VECTOR ( 1 DOWNTO 0 ) ; creset : IN STD_LOGIC ; q : OUT STD_LOGIC ) ; END mux4_2 ;
ARCHITECTURE rtl OF mux4_2 IS BEGIN
cmux4_2 : PROCESS ( cdata, sel, creset ) BEGIN
IF ( creset = '1' ) THEN IF ( sel = \"00\" ) THEN -- 多选择的IF语句 q <= cdata (0) ; ELSIF ( sel = \"01\" ) THEN q <= cdata (1) ; ELSIF ( sel = \"10\" ) THEN q <= cdata (2) ; ELSE q <= cdata (3) ; END IF ; ELSE q <= '0' ; END IF ;
（P74）
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END PROCESS cmux4_2 ; END rtl ;
【例4-14】 采用CASE语句来描述4选1选择器的示例程序。
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; ENTITY mux4_3 IS
PORT( cdata : IN STD_LOGIC_VECTOR ( 3 DOWNTO 0 ) ;
sel : IN STD_LOGIC_VECTOR ( 1 DOWNTO 0 ) ; q : OUT STD_LOGIC ) ; END mux4_3 ;
ARCHITECTURE rtl_mux4 OF mux4_3 IS
SIGNAL temp_sel : INTEGER RANGE 0 TO 3 ; BEGIN
cmux4_3 : PROCESS ( cdata, sel ) BEGIN
temp_sel <= '0' ;
IF ( sel (0) = '1' ) THEN -- 选择控制信号的译码 temp_sel <= temp_sel + 1 ; END IF ;
IF ( sel (1) = '1' ) THEN -- 选择控制信号的译码 temp_sel <= temp_sel + 2 ; END IF ;
-- 采用CASE语句描述四选一电路的选择控制信号
CASE temp_sel IS -- CASE语句的控制表达式是 temp_sel WHEN 0 => q <= cdata (0) ; WHEN 1 => q <= cdata (1) ; WHEN 2 => q <= cdata (2) ; WHEN 3 => q <= cdata (3) ; WHEN OTHERS => q <= ‘0' ; END CASE ;
END PROCESS cmux4_3 ; END rtl_mux4 ;
（P76）
【例4-15】 采用CASE语句设计3-8译码器的示例程序。
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; ENTITY cdecoder_3_8 IS
PORT ( d : IN STD_LOGIC_VECTOR ( 2 DOWNTO 0 ) ; G1 : IN STD_LOGIC ; G2A, G2B : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR ( 7 DOWNTO 0 ) ) ; END ENTITY cdecoder_3_8 ; -- VHDL 1993版可以这么用
ARCHITECTURE rtl_cdecoder_3_8 OF cdecoder_3_8 IS BEGIN
PROCESS ( d, G1, G2A, G2B ) BEGIN
IF ( G1= '1' AND G2A= '0' AND G2B = '0' ) THEN -- 译码器的使能信号 -- 采用CASE语句描述3-8译码电路
CASE d IS -- CASE语句的控制表达式是位矢量 d WHEN \"000\" => q <= \"11111110\" ; WHEN \"001\" => q <= \"11111101\" ; WHEN \"010\" => q <= \"11111011\" ; WHEN \"011\" => q <= \"11110111\" ; WHEN \"100\" => q <= \"11101111\" ; WHEN \"101\" => q <= \"11011111\" ; .
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WHEN \"110\" => q <= \"10111111\" ; WHEN \"111\" => q <= \"01111111\" ; WHEN OTHERS => q <= \"XXXXXXXX\" ; END CASE ; ELSE
q <= \"11111111\" ; END IF ; END PROCESS ;
END ARCHITECTURE rtl_cdecoder_3_8 ; -- VHDL 1993版可以这么用
【例4-16】 采用FOR LOOP语句实现32位奇偶校验电路的示例程序。
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; ENTITY cparity1 IS
PORT( cdata : IN STD_LOGIC_VECTOR ( 31 DOWNTO 0 ) ; q : OUT STD_LOGIC ;
qnot : OUT STD_LOGIC ) ; END ENTITY cparity1 ;
ARCHITECTURE rtl_cparity OF cparity1 IS BEGIN
cparity_example : PROCESS ( cdata ) VARIABLE temp : STD_LOGIC ; BEGIN
temp : = '1' ;
FOR i IN 0 TO 31 LOOP -- FOR LOOP语句对32位逻辑值奇偶判断 temp : = temp XOR cdata ( i ) ; END LOOP ; q <= temp ;
qnot <= NOT temp ; END PROCESS cparity_example ; END ARCHITECTURE rtl_cparity ;
（P78）
【例4-17】 WHILE LOOP语句格式的示例程序。
VARIABLE sum_temp : INTEGER : = 0 ; VARIABLE i : INTEGER : = 0 ; BEGIN
sum_example : WHILE ( i < 100 ) LOOP
sum_temp : = sum_temp + i ; i : = i + 1 ; END LOOP sum_example ; END PROCESS ;
（79）
【例4-18】 采用WHILE LOOP语句实现32位奇偶校验电路的示例程序。 （80）
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; ENTITY cparity2 IS
PORT( cdata : IN STD_LOGIC_VECTOR ( 31 DOWNTO 0 ) ; q : OUT STD_LOGIC ;
qnot : OUT STD_LOGIC ) ; END ENTITY cparity2 ;
ARCHITECTURE behav_cparity1 OF cparity2 IS BEGIN
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cparity_example : PROCESS ( cdata ) VARIABLE temp : STD_LOGIC ;
VARIABLE i : INTEGER ; -- 必须要有,不能省略 BEGIN
temp : = '0' ; i : = 0 ;
-- WHILE LOOP语句对32位逻辑值进行奇偶判断 WHILE ( i < 32 ) LOOP
temp : = temp XOR cdata ( i ) ; i : = i + 1 ; END LOOP ; q <= temp ;
qnot <= NOT temp ; END PROCESS cparity_example ; END ARCHITECTURE behav_cparity1 ;
【例4-19】 采用外部信号控制的32位奇偶校验电路的示例程序。
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LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; ENTITY cparity3 IS
PORT( cdata : IN STD_LOGIC_VECTOR ( 31 DOWNTO 0 ) ; ccontrol : IN STD_LOGIC ; q : OUT STD_LOGIC ; qnot : OUT STD_LOGIC ) ; END ENTITY cparity3 ;
ARCHITECTURE rtl_cparity OF cparity3 IS BEGIN
cparity_example : PROCESS ( cdata, ccontrol ) VARIABLE temp : STD_LOGIC ; BEGIN
temp : = '0' ;
FOR i IN 0 TO 31 LOOP -- FOR LOOP语句对32位逻辑值奇偶判断
NEXT WHEN ccontrol = '0' ; -- 外部信号ccontrol为逻辑低电平 temp : = temp XOR cdata ( i ) ;
WAIT FOR 200 ms ; -- 使得程序等待200 ms END LOOP ; q <= temp ;
qnot <= NOT temp ;
END PROCESS cparity_example ; END ARCHITECTURE rtl_cparity ;
【例4-20】 NEXT语句嵌在两个循环中的示例程序。
CTEST1 : FOR m IN 0 TO 50 LOOP -- 外循环
CTEST2 : FOR n IN 1 TO 40 LOOP -- 内循环
NEXT CTEST1 WHEN m = n ; -- NEXT语句的执行条件
END LOOP CTEST2 ; END LOOP CTEST1 ;
（P81）
【例4-21】 采用EXIT语句的示例程序。
ARCHITECTURE behav_cexit OF cexit_inst IS
（P82）
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CONSTANT pi : REAL : = 3.1415926 ; BEGIN
cexit_example : PROCESS ( clk )
VARIABLE area_temp : REAL : = 1.0 ; BEGIN
FOR i IN 1 TO 20 LOOP
area_temp : = pi * REAL ( i ) * REAL ( i ) ; -- 数据类型转换 IF INTEGER ( area_temp ) > 150 THEN EXIT ; -- 当条件成立则提前退出循环 END IF ; END LOOP ;
END PROCESS cexit_example ; END ARCHITECTURE behav_cexit ;
【例4-22】 采用RETURN语句的示例程序。
FUNCTION cmax21 ( d1 : INTEGER ; d2 : INTEGER )
RETURN INTEGER IS
VARIABLE temp : INTEGER : = 1 ; BEGIN
IF d1 > d2 THEN temp : = d1 ; ELSE
temp : = d2 ; END IF ;
RETURN temp ; END cmax21 ;
（P83）
【例4-23】 采用REPORT语句的示例程序。
REPORT \" data0 is timed out at '0' \" -- data0在逻辑0上超时 SEVERITY ERROR ;
REPORT \" q is not at '1' \" -- q不在逻辑1电平上 SEVERITY WARNING ;
（P84）
【例4-24】 使用NULL语句的示例程序。
ARCHITECTURE dataflow OF cnull IS SIGNAL d, q : STD_LOGIC ;
SIGNAL sel : STD_LOGIC_VECTOR ( 2 DOWNTO 0 ) ; BEGIN
CASE sel IS
WHEN 0 | 7 => q <= NOT d ; WHEN OTHERS => NULL ; END CASE ; END dataflow ;
（P84）
【例4-25】 采用ASSERT语句的示例程序。
ARCHITECTURE behav_cassert OF cexit_inst IS SIGNAL data0, data1 : STD_LOGIC ; BEGIN
ctest_A : PROCESS BEGIN .
（P85）
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data0 <= '0' ;
WAIT UNTIL ( data1 = '1' ) FOR 2 us ;
ASSERT ( data1 = '1' ) -- 当条件不成立时执行ASSERT语句 REPORT \" data1 is timed out at data1 = '1' . \" SEVERITY WARNING ;
data0 <= '1' AFTER 30 ns ; WAIT UNTIL ( data1 = '0' ) FOR 3 us ; ASSERT ( data1 = '0' )
REPORT \" data1 is timed out at data1 = '0'. \" SEVERITY WARNING ;
data0 <= '0' AFTER 40 ns ; END PROCESS ctest_A ; ctest_B : PROCESS BEGIN
WAIT UNTIL ( data0 = '0' ) FOR 2 us ;
ASSERT ( data0 = '0' ) -- 当条件不成立时则执行ASSERT语句 REPORT \" data0 is timed out at data0 = '0'. \" SEVERITY WARNING ;
data1 <= '0' AFTER 30 ns ;
WAIT UNTIL ( data0 = '1' ) FOR 3 us ; ASSERT ( data0 = '1' )
REPORT \" data0 is timed out at data0 = '1'. \" SEVERITY WARNING ;
data1 <= '1' AFTER 40 ns ; END PROCESS ctest_B ;
END ARCHITECTURE behav_cassert ;
【例4-26】 采用条件信号代入语句描述异或门的示例程序。
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; ENTITY cxorgate IS
PORT ( d0, d1 : IN STD_LOGIC ; q : OUT STD_LOGIC ) ; END ENTITY cxorgate ;
ARCHITECTURE cxorgate_example OF cxorgate IS BEGIN q <='0' WHEN d0 ='0' AND d1 ='0' ELSE -- 用条件信号代入语句描述异或门 '1' WHEN d0 = '0' AND d1 = '1' ELSE '1' WHEN d0 = '1' AND d1 = '0' ELSE '0' WHEN d0 = '1' AND d1 = '1' ELSE '0' ; END ARCHITECTURE cxorgate_example ;
（P88）
【例4-27】 采用条件信号代入语句描述3-8译码器的示例程序。
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; ENTITY cdecoder_3_8 IS
PORT ( d : IN STD_LOGIC_VECTOR ( 2 DOWNTO 0 ) ; G1 : IN STD_LOGIC ; G2A, G2B : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR ( 7 DOWNTO 0 ) ) ; END ENTITY cdecoder_3_8 ;
ARCHITECTURE data_flow OF cdecoder_3_8 IS BEGIN .
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-- 用条件信号代入语句描述3-8译码器
q <=\"11111110\" WHEN(G1='1' AND G2A='0' AND G2B ='0' AND d = \"000\" ) ELSE \"11111101\" WHEN(G1='1' AND G2A='0' AND G2B ='0' AND d = \"001\" ) ELSE \"11111011\" WHEN(G1='1' AND G2A='0' AND G2B ='0' AND d = \"010\" ) ELSE \"11110111\" WHEN(G1='1' AND G2A='0' AND G2B ='0' AND d = \"011\" ) ELSE \"11101111\" WHEN(G1= '1' AND G2A='0' AND G2B ='0' AND d = \"100\" ) ELSE \"11011111\" WHEN(G1='1' AND G2A='0' AND G2B ='0' AND d = \"101\" ) ELSE \"10111111\" WHEN(G1='1' AND G2A='0' AND G2B ='0' AND d = \"110\" ) ELSE \"01111111\" WHEN(G1='1' AND G2A='0' AND G2B ='0' AND d = \"111\" ) ELSE \"11111111\" ; -- 其中G1、G2A、G2B是译码器的使能信号 END ARCHITECTURE data_flow ;
【例4-28】 采用条件信号代入语句来描述4选1选择器的示例程序。
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; ENTITY cselector_4_1 IS
PORT ( d : IN STD_LOGIC_VECTOR ( 3 DOWNTO 0 ) ; sel : IN STD_LOGIC_VECTOR ( 1 DOWNTO 0 ) ; q : OUT STD_LOGIC ) ; END ENTITY cselector_4_1 ;
ARCHITECTURE data_flow OF cselector_4_1 IS BEGIN
-- 用条件信号代入语句描述4选1选择器
q <= d(0) WHEN ( sel = \"00\" ) ELSE d(1) WHEN ( sel = \"01\" ) ELSE d(2) WHEN ( sel = \"10\" ) ELSE d(3) WHEN ( sel = \"11\" ) ELSE '0' ;
END ARCHITECTURE data_flow ;
（P）
【例4-29】 采用选择信号代入语句描述异或门的示例程序。
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; ENTITY cxorgate2 IS
PORT ( d0, d1 : IN STD_LOGIC ; q : OUT STD_LOGIC ) ; END ENTITY cxorgate2 ;
ARCHITECTURE cxorgate_example OF cxorgate2 IS
SIGNAL data_input : STD_LOGIC_VECTOR (1 DOWNTO 0) ; BEGIN
data_input <= d1 & d0 ;
WITH data_input SELECT -- 用选择信号代入语句描述异或门 q <= '0' AFTER 7 ns WHEN \"00\" , '1' AFTER 7 ns WHEN \"01\" , '1' AFTER 7 ns WHEN \"10\" , '0' AFTER 7 ns WHEN \"11\" ; END ARCHITECTURE cxorgate_example ;
（90）
【例4-30】 采用选择信号代入语句来描述4选1选择器的示例程序。
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; ENTITY cselector_41 IS
（P91）
.
.
PORT ( d : IN STD_LOGIC_VECTOR ( 3 DOWNTO 0 ) ; sel : IN STD_LOGIC_VECTOR ( 1 DOWNTO 0 ) ; q : OUT STD_LOGIC ) ; END ENTITY cselector_41 ;
ARCHITECTURE data_flow OF cselector_41 IS SIGNAL data_select : INTEGER RANGE 0 TO 4 ; BEGIN
-- 用选择信号代入语句描述4选1选择器 WITH data_select SELECT
q <= d(0) AFTER 7 ns WHEN 0 , d(1) AFTER 7 ns WHEN 1 , d(2) AFTER 7 ns WHEN 2 , d(3) AFTER 7 ns WHEN 3 , 'X' WHEN OTHERS ;
data_select <= 0 WHEN ( sel = \"00\" ) ELSE 1 WHEN ( sel = \"01\" ) ELSE 2 WHEN ( sel = \"10\" ) ELSE 3 WHEN ( sel = \"11\" ) ELSE 4 ;
END ARCHITECTURE data_flow ;
【例4-31】 利用进程语句设计半加器的示例程序。
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; ENTITY chalf_adder IS
PORT ( data1, data2 : IN STD_LOGIC ; sum : OUT STD_LOGIC ;
carry : OUT STD_LOGIC ) ; END ENTITY chalf_adder ;
ARCHITECTURE behav OF chalf_adder IS BEGIN
chalfadder_inst: PROCESS ( data1, data2 ) BEGIN
sum <= data1 XOR data2 AFTER 5 ns ; carry <= data1 AND data2 AFTER 5 ns ; END PROCESS chalfadder_inst ; END ARCHITECTURE behav ;
（P93）
【例4-32】 利用在一个构造体中有两个进程语句通信的示例程序。
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; ENTITY cprocess_comm IS
PORT ( inA : IN STD_LOGIC ;
outA, outB : OUT STD_LOGIC ) ; END ENTITY cprocess_comm ;
ARCHITECTURE data_flow OF cprocess_comm IS SIGNAL comm_A, comm_B : STD_LOGIC : = '0' ; BEGIN
-- 进程A的进程名是communication_A
communication_A : PROCESS ( inA, comm_A ) BEGIN
IF ( inA'EVENT AND inA = '1' )
OR ( comm_A'EVENT AND comm_A = '1' ) THEN
（P93）
.
.
comm_B <= '1' AFTER 25 ns ; '0' AFTER 50 ns ; outA <= '1' AFTER 20 ns ; '0' AFTER 20 ns ; END IF ;
END PROCESS communication_A -- 进程B的进程名是communication_B
communication_B : PROCESS ( comm_B ) BEGIN
IF ( comm_B'EVENT AND comm_B = '1' ) THEN comm_A <= '1' AFTER 25 ns ; '0' AFTER 50 ns ; outB <= '1' AFTER 20 ns ; '0' AFTER 20 ns ; END IF ;
END PROCESS communication_B ; END ARCHITECTURE data_flow ;
【例4-33】 利用COMPONENT语句的2选1选择器的示例程序。
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; ENTITY cmux_21 IS
PORT ( data1, data2 : IN STD_LOGIC ; sel : IN STD_LOGIC ; q : OUT STD_LOGIC ) ; END ENTITY cmux_21 ;
ARCHITECTURE struct OF cmux_21 IS COMPONENT inv -- 反相器元件 PORT ( a : IN STD_LOGIC ; c : OUT STD_LOGIC ) ; END COMPONENT ;
COMPONENT and2 -- 二输入与门元件 PORT ( a, b : IN STD_LOGIC ; c : OUT STD_LOGIC ) ; END COMPONENT ;
COMPONENT or2 -- 二输入或门元件 PORT ( a, b : IN STD_LOGIC ; c : OUT STD_LOGIC ) ; END COMPONENT ;
SIGNAL temp1, temp2, not_sel : STD_LOGIC ; BEGIN
cunit1 : inv PORT MAP ( sel, not_sel ) ;
cunit2 : and2 PORT MAP ( not_sel, data2, temp2 ) ; cunit3 : and2 PORT MAP ( sel, data1, temp1 ) ; cunit4 : or2 PORT MAP (temp1, temp2, q ) ; END ARCHITECTURE struct ;
（P95）
【例4-34】 利用GENERIC语句定义二输入或非门的上升沿和下降沿参数的示例程序。 （P98）
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; ENTITY or2 IS
GENERIC ( rise, fall : TIME ) ; -- 类属参数说明 .
.
PORT ( a , b : IN STD_LOGIC ; c : OUT STD_LOGIC ) ; END ENTITY or2 ;
ARCHITECTURE behav OF or2 IS SIGNAL ctemp : STD_LOGIC ; BEGIN
ctemp <= a AND b ;
c <= ctemp AFTER ( rise ) WHEN ( ctemp = '1' ) ELSE ctemp AFTER ( fall ) ; END ARCHITECTURE struct ;
【例4-35】 和图4-4相对应的利用GENERIC语句的示例程序。
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; ENTITY cexample_nor2 IS
GENERIC ( rise, fall : TIME ) ; PORT ( in1, in2 : IN STD_LOGIC ; in3, in4 : IN STD_LOGIC ; q : OUT STD_LOGIC ) ; END ENTITY cexample_nor2 ;
ARCHITECTURE behav OF cexample_nor2 IS COMPONENT nor2 -- 二输入或门元件 GENERIC ( rise, fall : TIME ) ; PORT ( a, b : IN STD_LOGIC ; c : OUT STD_LOGIC ) ; END COMPONENT ;
SIGNAL temp1, temp2 : STD_LOGIC ; BEGIN
cunit1 : nor2 GENERIC MAP ( 6 ns, 7 ns ) PORT MAP ( in1, in2, temp1 ) ; cunit2 : nor2 GENERIC MAP ( 8 ns, 9 ns ) PORT MAP ( in3, in4, temp2 ) ; cunit3 : nor2 GENERIC MAP ( 10 ns, 11 ns ) PORT MAP ( temp1, temp2, q ) ; END ARCHITECTURE behav ;
（P99）
【例4-36】 利用BLOCK语句设计2选1选择器的示例程序。
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; ENTITY cmux_21 IS
PORT ( data1, data2 : IN STD_LOGIC ; sel : IN STD_LOGIC ; q : OUT STD_LOGIC ) ; END ENTITY cmux_21 ;
ARCHITECTURE behav OF cmux_21 IS
SIGNAL temp1, temp2, temp3 : STD_LOGIC ; BEGIN
cblock_inst: BLOCK BEGIN
temp1 <= data1 AND sel ;
temp2 <= data2 AND ( NOT sel ) ; temp3 <= temp1 OR temp2 ; q <= temp3 AFTER 5 ns ;
（P100）
.
.
END BLOCK cblock_inst ; END ARCHITECTURE behav ;
【例4-37】 利用BLOCK语句和PROCESS语句嵌套设计一个半加器的示例程序。 （P101）
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ;
ENTITY chalf_adder IS -- 实体的名字是chalf_adder PORT ( data1, data2 : IN STD_LOGIC ; sum : OUT STD_LOGIC ;
carry : OUT STD_LOGIC ) ; END ENTITY chalf_adder ;
ARCHITECTURE behav_hadder1 OF chalf_adder IS -- 构造体1的名字是behav_hadder1 BEGIN
sum <= data1 XOR data2 AFTER 6 ns ; carry <= data1 AND data2 AFTER 6 ns ; END ARCHITECTURE behav_hadder1 ;
ARCHITECTURE behav_hadder2 OF chalf_adder IS -- 构造体2的名字是behav_hadder2 BEGIN
chalfadder_example: BLOCK -- 块chalfadder_example开始 PORT ( d1, d2 : IN STD_LOGIC ; -- 端口接口表,参数定义 s, c : OUT STD_LOGIC ) ;
PORT MAP ( d1, d2, s, c ) ; -- 端口信号映射 BEGIN
cpro_1 : PROCESS ( d1, d2 ) -- 第一个进程cpro_1 BEGIN
s <= d1 XOR d2 AFTER 8 ns ; END PROCESS cpro_1 ;
cpro_2 : PROCESS ( d1, d2 ) -- 第二个进程cpro_2 BEGIN
c <= d1 AND d2 AFTER 8 ns ; END PROCESS cpro_2 ;
END BLOCK chalfadder_example ; END ARCHITECTURE behav_hadder2 ;
【例4-38】 利用BLOCK语句的CPU芯片设计的示例程序。
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; PACKAGE CPUBIT32 IS
TYPE tw32 IS ARRAY ( 31 DOWNTO 0 ) OF STD_LOGIC ; END CPUBIT32 ;
USE IEEE.STD_LOGIC_11.ALL ; USE WORK.CPUBIT32.ALL ; ENTITY cpu_inst IS
PORT ( clk, interrupt : IN STD_LOGIC ; address_bus : OUT tw32 ; data_bus : INOUT tw32 ) ; END ENTITY cpu_inst ;
ARCHITECTURE cpu_inst_block OF cpu_inst IS .
（P102）
.
SIGNAL temp1_bus, temp2_bus : tw32 ; BEGIN
ALU_inst : BLOCK
SIGNAL temp3_bus : tw32 ; BEGIN
-- ALU模块的行为描述语句 END BLOCK ALU_inst ;
REGESTER8_inst : BLOCK -- 8个寄存器组模块的行为描述语句 SIGNAL temp4_bus, temp5_bus : tw32 ; BEGIN
REG_one : BLOCK
SIGNAL temp4_bus, temp6_bus : tw32 ; BEGIN
-- 第一个寄存器模块的行为描述语句 END BLOCK REG_one ;
-- 其他各个寄存器模块的行为描述语句 END BLOCK REGESTER8_inst ; END ARCHITECTURE cpu_inst_block ;
【例4-39】 利用卫式BLOCK语句设计D触发器的示例程序。
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; ENTITY cdff2 IS PORT ( d : IN STD_LOGIC ; clk : IN STD_LOGIC ; q : OUT STD_LOGIC ; qnot : OUT STD_LOGIC ) ; END cdff2 ;
ARCHITECTURE cdff2_guarded OF cdff2 IS BEGIN
cguarded_example : BLOCK ( clk = '1' ) BEGIN
q <= GUARDED d AFTER 5 ns ;
qnot <= GUARDED NOT ( d ) AFTER 10 ns ; END BLOCK cguarded_example ; END cdff2_guarded ;
（P104）
【例4-40】 利用PROCEDURE语句结构把位矢量转换成整数的示例程序。（P106）
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ;
PROCEDURE bitvector_to_integer -- 过程名 ( cvectors : IN STD_LOGIC_VECTOR ; cflag : OUT BOOLEAN ; cinteger : INOUT INTEGER ) IS BEGIN
cinteger : = 0 ; cflag : = FALSE ; FOR i IN cvectors'RANGE LOOP cinteger : = cinteger * 2 ; IF ( cvectors ( i ) = '1' ) THEN cinteger : = cinteger + 1 ; ELSIF ( cvectors ( i ) /= '0' ) THEN cflag : = TRUE ; .
.
END IF ; END LOOP ;
END bitvector_to_integer ;
【例4-41】 在主程序中调用过程“bitvector_to_integer”的示例程序。 （P107）
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; LIBRARY WORK ;
USE WORK.mypackage1.ALL ; ENTITY cdiaoyong_inst IS PORT ( d : IN STD_LOGIC_VECTOR ( 7 DOWNTO 0 ) ; -- 待转换的8位位矢量 clk : IN STD_LOGIC ; q : OUT STD_LOGIC ) ; END cdiaoyong_inst ;
ARCHITECTURE behav OF cdiaoyong_inst IS BEGIN
PROCESS ( clk )
VARIABLE num_d : INTEGER RANGE 0 TO 128 ; -- 转换后的结果 BEGIN
bitvector_to_integer(d,num_d); -- 调用过程\"bitvector_to_integer\"
END PROCESS ; END behav ;
【例4-42】 利用FUNCTION语句结构把位矢量转换成整数的示例程序。 （109）
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; PACKAGE mypackage2 IS
FUNCTION vector2int ( cvect : STD_LOGIC_VECTOR ) -- 函数说明 RETURN INTEGER ; END mypackage2 ;
PACKAGE BODY mypackage2 IS
FUNCTION vector2int ( cvect : STD_LOGIC_VECTOR ) -- 函数定义开始 RETURN INTEGER IS
VARIABLE cresult : INTEGER : = 0 ; BEGIN
FOR i IN cvect'RANGE LOOP
cresult : = cresult * 2 ; -- 左移1位 IF ( cvect ( i ) = '1' ) THEN
cresult : = cresult + 1 ; END IF ; END LOOP ;
RETURN cresult ; END vector2int ; END mypackage2 ;
【例4-43】 利用FUNCTION语句结构实现取最大值的示例程序。
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; .
（P110）
.
PACKAGE mypackage3 IS
FUNCTION getmax ( data1 : STD_LOGIC_VECTOR ; data2 : STD_LOGIC_VECTOR ) RETURN STD_LOGIC_VECTOR ; END mypackage3 ;
PACKAGE BODY mypackage3 IS
FUNCTION getmax ( data1 : STD_LOGIC_VECTOR ; data2 : STD_LOGIC_VECTOR ) RETURN STD_LOGIC_VECTOR IS
VARIABLE temp : STD_LOGIC_VECTOR ( data1'RANGE ) ; BEGIN
IF ( data1 > data2 ) THEN temp : = data1 ; ELSE
temp : = data2 ; END IF ; RETURN temp ; END getmax ; END mypackage3 ;
【例4-44】 调用函数getmax( )实现最大值检出的示例程序。
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; LIBRARY WORK ;
USE WORK.mypackage1.ALL ; -- 包含函数getmax( )的包集合 PACKAGE mypackage3 IS
FUNCTION getmax ( data1 : STD_LOGIC_VECTOR ; data2 : STD_LOGIC_VECTOR ) RETURN STD_LOGIC_VECTOR ; END mypackage3 ;
ENTITY cdetectpeak IS PORT ( datain1 : IN STD_LOGIC_VECTOR ( 7 DOWNTO 0 ) ; datain2 : IN STD_LOGIC_VECTOR ( 7 DOWNTO 0 ) ; clk, set : IN STD_LOGIC ;
dataout : OUT STD_LOGIC_VECTOR ( 7 DOWNTO 0 ) ) ; END cdetectpeak ;
ARCHITECTURE behav OF cdetectpeak IS
SIGNAL cpeak : STD_LOGIC_VECTOR ( 7 DOWNTO 0 ) ; BEGIN
dataout <= cpeak ; PROCESS ( clk ) BEGIN
IF ( clk'EVENT AND clk = '1' ) THEN IF ( set = '1' ) THEN
cpeak <= \"11111111\" ; ELSE
cpeak <= getmax ( datain1, datain2 ) ; -- 调用函数\"getmax( )\" END IF ; END IF ; END PROCESS ; END behav ;
（P110）
【例4-45】 用FOR-GENERATE语句设计4位移位寄存器的示例程序。
.
（P112）
.
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; ENTITY shift4 IS PORT ( shiftin : IN STD_LOGIC ; clk : IN STD_LOGIC ; shiftout : OUT STD_LOGIC ) ; END shift4 ;
ARCHITECTURE behavioral OF shift4 IS COMPONENT dff PORT ( d, clk : IN STD_LOGIC ; q : OUT STD_LOGIC ) ; END COMPONENT ; SIGNAL data : STD_LOGIC_VECTOR ( 4 DOWNTO 0 ) ; BEGIN data(0) <= shiftin ; generate_inst : FOR i IN 0 TO 3 GENERATE dffn_x : dff PORT MAP (data(i), clk, data(i+1) ) ; END GENERATE ;
shiftout <= data(4) ; END behavioral ;
【例4-46】 用一般的方法设计4位移位寄存器的示例程序（用来和例4-45对比）。 （P113）
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; ENTITY cshift_common IS PORT ( shiftin : IN STD_LOGIC ; clk : IN STD_LOGIC ; shiftout : OUT STD_LOGIC ) ; END cshift_common ;
ARCHITECTURE behavioral OF cshift_common IS COMPONENT dff PORT ( d, clk : IN STD_LOGIC ; q : OUT STD_LOGIC ) ; END COMPONENT ; SIGNAL data : STD_LOGIC_VECTOR ( 0 TO 4 ) ; BEGIN data(0) <= shiftin ; dffn_0 : dff PORT MAP ( data (0), clk, data (1) ) ; dffn_1 : dff PORT MAP ( data (1), clk, data (2) ) ; dffn_2 : dff PORT MAP ( data (2), clk, data (3) ) ; dffn_3 : dff PORT MAP ( data (3), clk, data (4) ) ; shiftout <= data (4) ; END behavioral ;
【例4-47】 利用IF-GENERATE语句设计n位移位寄存器的示例程序。
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; ENTITY shift_n IS
GENERIC ( clength : INTEGER ) ; PORT ( shiftin : IN STD_LOGIC ; .
（P114）
.
clk : IN STD_LOGIC ; shiftout : OUT STD_LOGIC ) ; END shift_n ;
ARCHITECTURE behavioral OF shift_n IS COMPONENT dff PORT ( d, clk : IN STD_LOGIC ; q : OUT STD_LOGIC ) ; END COMPONENT ; SIGNAL data : STD_LOGIC_VECTOR ( ( clength－1 ) DOWNTO 0 ) ; BEGIN for_generate_inst : FOR i IN 0 TO ( clength－1 ) GENERATE IF i = 0 GENERATE dff PORT MAP ( shiftin, clk, data (i+1) ) ; END GENERATE ;
IF i = ( clength－1 ) GENERATE dff PORT MAP ( data (i), clk, shiftout ) ; END GENERATE ;
IF ( ( i /= 0 ) AND (i /= ( clength－1 ) ) ) GENERATE dff PORT MAP ( data (i), clk, data (i+1) ) ; END GENERATE ; END GENERATE ; END behavioral ;
【例4-48】 获取数值型枚举类型的数值属性的示例程序。
-- 定义数值型枚举类型 cynumber
TYPE cynumber IS 3 TO 999 ; -- 在结构体中使用该数据类型的数值属性
ARCHITECTURE behavioral OF cyattribute IS BEGIN PROCESS ( clk ) VARIABLE d0, d1, d2, d3 : cynumber ; BEGIN d0 := cynumber'LEFT ; -- d0 = 3, 枚举类型cynumber的最左端值 d1 := cynumber'RIGHT ; -- d1 = 999, 枚举类型cynumber的最右端值 d2 := cynumber'HIGH ; -- d2 = 999, 枚举类型cynumber的最大值 d3 := cynumber'LOW ; -- d3 = 3, 枚举类型cynumber的最小值 END PROCESS ; END behavioral ;
（P118）
【例4-49】 用DOWNTO来排列数据时，获取该数据的数值属性的示例程序。（P119）
-- 自定义整数类型 cyinteger
TYPE cyinteger IS INTEGER RANGE 999 DOWNTO 3 ; -- 在结构体中使用该数据类型的数值属性
ARCHITECTURE behavioral OF cyattribute IS BEGIN PROCESS ( clk ) VARIABLE d0, d1, d2, d3 : INTEGER ; -- 也可以用cyinteger BEGIN d0 := cyinteger'LEFT ; -- d0 = 999, 整数类型cyinteger的最左端值 d1 := cyinteger'RIGHT ; -- d1 = 3, 整数类型cyinteger的最右端值 d2 := cyinteger'HIGH ; -- d2 = 999, 整数类型cyinteger的最大值 d3 := cyinteger'LOW ; -- d3 = 3, 整数类型cyinteger的最小值 END PROCESS ; .
.
END behavioral ;
【例4-50】 利用数据的数值属性检测数据总线宽度的示例程序。
-- 自定义数组类型 DATA_BUS
TYPE DATA_BUS IS ARRAY ( 31 DOWNTO 0 ) OF STD_LOGIC ; -- 在结构体中使用该数据类型的数值属性
ARCHITECTURE behavioral OF cyattribute IS BEGIN PROCESS ( clk ) VARIABLE d0, d1, d2, d3 : INTEGER ; BEGIN d0 := DATA_BUS'LEFT ; -- d0 = 31 d1 := DATA_BUS'RIGHT ; -- d1 = 0 d2 := DATA_BUS'HIGH ; -- d2 = 31 d3 := DATA_BUS'LOW ; -- d3 = 0 END PROCESS ; END behavioral ;
（P119）
【例4-51】 获取字符型枚举类型的数值属性的示例程序。
-- 定义字符型枚举类型 cytime
TYPE cytime IS ( sec, min, hour, day, month, year ) ; -- 定义字符型枚举子类型 reverse_cytime
SUBTYPE reverse_cytime IS cytime RANGE ( month DOWNTO min ) ; -- 在结构体中使用该数据类型的数值属性
ARCHITECTURE behavioral OF cyattribute IS SIGNAL temp1, temp2, temp3, temp4 : cytime ; SIGNAL temp5, temp6, temp7, temp8 : cytime ; BEGIN PROCESS ( clk ) BEGIN temp1 <= cytime'LEFT; -- temp1中代入sec,枚举类型cytime的最左端值 temp2 <= cytime'RIGHT; -- temp2中代入year, 枚举类型cytime的最右端值 temp3 <= cytime'HIGH; -- temp3中代入year, 枚举类型cytime的最大值 temp4 <= cytime'LOW; -- temp4中代入sec, 枚举类型cytime的最小值 temp5 <= reverse_cytime'LEFT ; -- temp5中代入month, 枚举子类型reverse_cytime的最左端值 temp6 <= reverse_cytime'RIGHT ; -- temp6中代入min, 枚举子类型reverse_cytime的最右端值 temp7 <= reverse_cytime'HIGH ; -- temp7中代入month, 枚举子类型reverse_cytime的最大值 temp8 <= reverse_cytime'LOW ; -- temp8中代入min, 枚举子类型reverse_cytime的最小值 END PROCESS ;
END ARCHITECTURE behavioral ;
（P120）
【例4-52】 利用'LENGTH属性来获取数组的范围长度的示例程序。 （P120）
-- 定义数组类型。
TYPE array_bit IS ARRAY ( 0 TO 31 ) OF BIT ;
TYPE array_integer IS ARRAY ( 0 TO 63 ) OF INTEGER ; -- 在结构体中使用该数组的数值属性'LENGTH
ARCHITECTURE behavioral OF cyattribute IS
.
.
BEGIN PROCESS ( clk ) VARIABLE temp1_length, temp2_length : INTEGER ; BEGIN temp1_length := array_bit'LENGTH ; -- temp1_length = 32 temp2_length := array_integer'LENGTH ; -- temp2_length = END PROCESS ; END behavioral ;
【例4-53】 利用'LENGTH属性来获取枚举类型的数组范围长度的示例程序。（P121）
-- 定义数组类型
TYPE cynumber IS ( 'X', 'Z', '1', '0' ) ;
TYPE cyarray1 IS ARRAY (cynumber'LOW TO cynumber'HIGH ) OF cynumber ; TYPE cyarray2 IS ARRAY (cyarray1'LOW TO cyarray1'HIGH ) OF cyarray1 ; TYPE cyarray3 IS ARRAY ( cynumber'LOW TO cynumber'HIGH , cynumber'LOW TO cynumber'HIGH ) OF cynumber ; CONSTANT single_array_and : cyarray2 := ( ( 'X' , -- X and X = X 'X' , -- X and Z = X 'X' , -- X and 1 = X '0' ) , -- X and 0 = 0 ( 'X' , -- Z and X = X 'X' , -- Z and Z = X 'X' , -- Z and 1 = X '0' ) , -- Z and 0 = 0 ( 'X' , -- 1 and X = X 'X' , -- 1 and Z = X '1' , -- 1 and 1 = 1 '0' ) , -- 1 and 0 = 0 ( '0' , -- 0 and X = 0 '0' , -- 0 and Z = 0 '0' , -- 0 and 1 = 0 '0' ) -- 0 and 0 = 0
) ; -- 该常数的数据类型是一维数组类型cyarray2 -- 但其每个元素却是数组类型cyarray1,所以实际也是二维数组 CONSTANT double_array_and : cyarray3 := ( ( 'X' , -- X and X = X 'X' , -- X and Z = X 'X' , -- X and 1 = X '0' ) , -- X and 0 = 0 ( 'X' , -- Z and X = X 'X' , -- Z and Z = X 'X' , -- Z and 1 = X '0' ) , -- Z and 0 = 0 ( 'X' , -- 1 and X = X 'X' , -- 1 and Z = X '1' , -- 1 and 1 = 1 '0' ) , -- 1 and 0 = 0 ( '0' , -- 0 and X = 0 '0' , -- 0 and Z = 0 '0' , -- 0 and 1 = 0 '0' ) -- 0 and 0 = 0
) ; -- 该常数的数据类型是二维数组类型cyarray3
-- 其每个元素是枚举类型数据cynumber,所以实际也是二维数组 -- 在结构体中使用以上定义的数组的数值属性'LENGTH ARCHITECTURE behavioral OF cyattribute IS .
.
BEGIN PROCESS ( clk ) VARIABLE temp1_length, temp2_length, temp3_length : INTEGER ; VARIABLE temp4_length, temp5_length, temp6_length : INTEGER ; BEGIN temp1_length := cyarray1'LENGTH ; -- temp1_length = 4 temp2_length := cyarray2'LENGTH ; -- temp2_length = 4 temp3_length := cyarray3'LENGTH (1) ; -- temp3_length = 4 temp4_length := cyarray3'LENGTH (2) ; -- temp4_length = 4 temp5_length := single_array_and'LENGTH ; -- temp5_length = 4 temp6_length := double_array_and'LENGTH(2); -- temp6_length = 4 END PROCESS ; END behavioral ;
【例4-】 说明块的数值属性'STRUCTURE和'BEHAVIOR的示例程序。 （P123）
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; ENTITY cmux_21 IS
PORT ( data1, data2 : IN STD_LOGIC ; sel : IN STD_LOGIC ; q : OUT STD_LOGIC ) ; END ENTITY cmux_21 ;
ARCHITECTURE struct OF cmux_21 IS COMPONENT inv -- 反相器元件 PORT ( a : IN STD_LOGIC ; c : OUT STD_LOGIC ) ; END COMPONENT ;
COMPONENT and2 -- 二输入与门元件 PORT ( a, b : IN STD_LOGIC ; c : OUT STD_LOGIC ) ; END COMPONENT ;
COMPONENT or2 -- 二输入或门元件 PORT ( a, b : IN STD_LOGIC ; c : OUT STD_LOGIC ) ; END COMPONENT ;
SIGNAL temp1, temp2, not_sel : STD_LOGIC ; BEGIN cunit1 : inv PORT MAP ( sel, not_sel ) ; cunit2 : and2 PORT MAP ( not_sel, data2, temp2 ) ; cunit3 : and2 PORT MAP ( sel, data1, temp1 ) ; cunit4 : or2 PORT MAP (temp1, temp2, q ) ; cyinstance : PROCESS ( clk ) -- 这是一个示意性的进程 VARIABLE temp : STD_LOGIC ; BEGIN
temp := data1 AND data2 AND sel ; END PROCESS cyinstance ; END ARCHITECTURE struct ;
【例4-55】 利用数据类型的属性函数解析欧姆定律的示例程序。
-- 自定义物理类型数据 PACKAGE ohms_law IS
TYPE voltage IS RANGE 0 TO 1000000 ; -- 定义电压的物理类型数据 UNITS
（P125）
.
.
uV ; -- 基本单位是微伏 mV = 1000 uV ; -- 毫伏 V = 1000 mV ; -- 伏特 END UNITS ;
TYPE current IS RANGE 0 TO 1000000 ; -- 定义电流的物理类型数据 UNITS uA ; -- 基本单位是微安 mA = 1000 uA ; -- 毫安 A = 1000 mA ; -- 安培 END UNITS ;
TYPE resistance IS RANGE 0 TO 1000000 ; -- 定义电阻的物理类型数据 UNITS ohm ; -- 基本单位是欧姆 kohm = 1000 ohm ; -- 千欧 mohm = 1000 kohm ; -- 兆欧 END UNITS ; END ohms_law ;
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; LIBRARY WORK ;
USE WORK.ohms_law.ALL ;
ENTITY calculate_ohm IS
PORT ( I_data : IN current ; U_data : IN voltage ;
R_data : OUT resistance ) ; END ENTITY calculate_ohm ;
ARCHITECTURE behavioral OF calculate_ohm IS BEGIN calculate_ohms : PROCESS ( I_data, U_data ) VARIABLE temp_i, temp_v, temp_r : INTEGER ;
-- 整数类型的暂存变量,它们分别对应这些物理量的标量,两者在数值上是相等的 BEGIN temp_v := voltage'POS ( U_data ); -- 得到物理量电压的标量值 temp_i := current'POS ( I_data ); -- 得到物理量电流的标量值 temp_r := temp_v / temp_i ; -- 得到物理量电阻的位置序号,也即标量值 R_data <= resistance'VAL(temp_r); -- 由电阻的标量值转换为电阻物理量 END PROCESS calculate_ohms ; END behavioral ;
【例4-56】 说明'SUCC、'PRED、'LEFTOF、'RIGHTOF属性使用方法的示例程序。 （P127）
-- 自定义数据类型
PACKAGE cyweek_package IS
TYPE cyweek IS ( sunday, monday, tuesday, wednesday, thursday, friday, saturday ) ;
-- 用枚举类型表示一个星期中的7天
TYPE reverse_cyweek IS cyweek RANGE saturday DOWNTO sunday ; -- 对一个星期的7天用逆序表示 END cyweek_package ;
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; LIBRARY WORK ;
USE WORK.cyweek_package.ALL ; .
.
ARCHITECTURE behavioral OF calculate_cyweek IS BEGIN PROCESS ( clk ) VARIABLE temp1,temp2,temp3,temp4 : INTEGER ; -- 整数类型的暂存变量 VARIABLE temp5, temp6, temp7, temp8 : INTEGER ; BEGIN temp1 := cyweek'SUCC (wednesday);-- 得到wednesday的后面的值thursday temp2 := cyweek'PRED(friday );-- 得到friday的前面的值thursday temp3 := cyweek'LEFTOF(wednesday ); -- 得到wednesday的左邻值tuesday temp4 := cyweek'RIGHTOF ( sunday ); -- 得到sunday的右邻值monday temp5 := reverse_cyweek'SUCC ( wednesday ) ; -- 此时为逆序表示,得到wednesday的后面的值tuesday temp6 := reverse_cyweek'PRED ( friday ) ; -- 此时为逆序表示,得到friday的前面的值saturday temp7 := reverse_cyweek'LEFTOF ( wednesday ) ; -- 此时为逆序表示,得到wednesday的左邻值thursday temp8 := reverse_cyweek'RIGHTOF ( monday ) ; -- 此时为逆序表示,得到sunday的右邻值sunday END PROCESS ; END behavioral ;
【例4-57】 利用数组的属性函数的示例程序。
-- 自定义数据类型
TYPE cydata_base IS ARRAY ( 0 TO 1023 ) OF INTEGER ; -- 在结构体中使用该数组
ARCHITECTURE behavioral OF calculate_cyweek IS
CONSTANT cyinitial_value : INTEGER := 0 ; -- 定义一个初始化常数 BEGIN PROCESS ( clk ) BEGIN FOR i IN cydata_base'LOW (1) TO cydata_base'HIGH (1) LOOP cydata_base ( i ) := cyinitial_value ; END LOOP ; END PROCESS ; END behavioral ;
（P128）
【例4-58】 属性函数'EVENT和'LAST_VALUE的使用方法的示例程序。 （P129）
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; ENTITY cydff IS PORT( d : IN STD_LOGIC ; clk : IN STD_LOGIC ; q : OUT STD_LOGIC ;
qnot : OUT STD_LOGIC ) ; END ENTITY cydff ;
ARCHITECTURE dataflow OF cydff IS BEGIN
cdff_example : PROCESS ( clk ) BEGIN
IF ( clk'EVENT AND clk = '1' ) THEN q <= d ;
qnot <= NOT d ; END IF ; END PROCESS cdff_example ; END ARCHITECTURE dataflow ; .
.
【例4-59】 利用信号的属性函数'LAST_EVENT检查建立时间的示例程序。（P131）
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; ENTITY cydff2 IS GENERIC ( setup_time : TIME ) ; PORT( d : IN STD_LOGIC ; clk : IN STD_LOGIC ; q : OUT STD_LOGIC ;
qnot : OUT STD_LOGIC ) ; BEGIN
check_setuptime : PROCESS ( clk ) BEGIN
IF ( clk'EVENT AND clk'LAST_VALUE = '0' AND clk = '1' ) THEN ASSERT ( d'LAST_EVENT >= setup_time ) -- 当条件不成立时（d'LAST_EVENT < setup_time）,执行ASSERT语句 REPORT \" Setup Time is violated . \" -- 建立时间违规 SEVERITY ERROR ; END IF ;
END PROCESS check_setuptime ; END ENTITY cydff2 ;
ARCHITECTURE dataflow OF cydff2 IS BEGIN
cdff_example : PROCESS ( clk ) BEGIN IF ( clk'EVENT AND clk'LAST_VALUE = '0' AND clk = '1' ) THEN q <= d ; qnot <= NOT d ; END IF ;
END PROCESS cdff_example ; END ARCHITECTURE dataflow ;
【例4-60】 利用属性'DELAYED（time）描述三输入或门的示例程序。 （P134）
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; ENTITY cyor3 IS GENERIC ( ipd1_time, ipd2_time, ipd3_time, opd_time : TIME ) ; PORT( datain_1, datain_2, datain_3 : IN STD_LOGIC ; dataout : OUT STD_LOGIC ) ; END ENTITY cyor3 ;
ARCHITECTURE behavioral_1 OF cyor3 IS
SIGNAL in_tipd1, in_tipd2, in_tipd3, out_topd : STD_LOGIC ; BEGIN in_tipd1 <= TRANSPORT datain_1 AFTER ipd1_time ; in_tipd2 <= TRANSPORT datain_2 AFTER ipd2_time ; in_tipd3 <= TRANSPORT datain_3 AFTER ipd3_time ; out_topd <= TRANSPORT ( datain_1 OR datain_2 OR datain_3 ) AFTER opd_time ; dataout <= out_topd ; END ARCHITECTURE behavioral_1 ;
ARCHITECTURE behavioral_2 OF cyor3 IS SIGNAL out_topd : STD_LOGIC ; .
.
BEGIN out_topd <= datain_1'DELAYED ( ipd1_time ) OR datain_2'DELAYED ( ipd2_time ) OR datain_3'DELAYED ( ipd3_time ) ; dataout <= out_topd'DELAYED ( opd_time ) ; END ARCHITECTURE behavioral_2 ;
【例4-61】 利用信号类属性'DELAYED检查保持时间的示例程序。 （P134）
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; ENTITY cydff3 IS GENERIC ( hold_time : TIME ) ; PORT( d : IN STD_LOGIC ; clk : IN STD_LOGIC ; q : OUT STD_LOGIC ; qnot : OUT STD_LOGIC ) ; BEGIN
check_holdtime : PROCESS ( clk'DELAYED ( hold_time ) ) BEGIN
IF ( clk'DELAYED ( hold_time )'EVENT AND clk'DELAYED ( hold_time ) = '1' ) THEN
ASSERT ( d'LAST_EVENT >= hold_time ) -- 当条件不成立时（d'LAST_EVENT < hold_time）,执行ASSERT语句 REPORT \" Hold Time is violated . \" – 保持时间违规 SEVERITY ERROR ; END IF ;
END PROCESS check_holdtime ; END ENTITY cydff3 ;
ARCHITECTURE dataflow OF cydff3 IS BEGIN
cdff_example : PROCESS ( clk ) BEGIN IF ( clk'EVENT AND clk'LAST_VALUE = '0' AND clk = '1' ) THEN q <= d ; qnot <= NOT d ; END IF ;
END PROCESS cdff_example ; END ARCHITECTURE dataflow ;
【例4-62】 利用属性'STABLE（time）的示例程序。
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; ENTITY cystable IS PORT ( datain : IN STD_LOGIC ; dataout1, dataout2 : OUT STD_LOGIC ) ; END ENTITY cystable ;
ARCHITECTURE behavioral OF cystable IS BEGIN dataout2 <= datain'STABLE ; dataout1 <= datain'STABLE ( 10 ns ) ; END ARCHITECTURE behavioral ;
（P136）
.
.
【例4-63】 利用属性'QUIET（time）描述具有优先级的中断机制的示例程序。（136）
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; ENTITY cyinterrupt IS PORT ( extrig1, extrig2, extrig3 : IN STD_LOGIC ) ; END ENTITY cyinterrupt ;
ARCHITECTURE behavioral OF cyinterrupt IS
TYPE number_interrupt IS ( interrupt1, interrupt2, interrupt3, interrupt4 ) ;
SIGNAL intp, intp_sig1, intp_sig2, intp_sig3 : number_interrupt ; SIGNAL lock_out : BOOLEAN := FALSE ; BEGIN
-- 第一级中断权的判断
interrupt1_proc : PROCESS BEGIN
-- 其他处理程序
WAIT ON extrig1 ; -- 第一级外部硬件中断信号到来 WAIT UNTIL clk = '1' ; IF NOT ( lock_out ) THEN
intp_sig1 <= interrupt1 ; END IF ;
END PROCESS interrupt1_proc ; -- 第二级中断权的判断
interrupt2_proc : PROCESS BEGIN
-- 其他处理程序
WAIT ON extrig2 ; -- 第二级外部硬件中断信号到来 WAIT UNTIL clk = '1' ; IF NOT ( lock_out ) THEN
intp_sig2 <= interrupt2 ; END IF ;
END PROCESS interrupt2_proc ; -- 第三级中断权的判断
interrupt3_proc : PROCESS BEGIN
-- 其他处理程序
WAIT ON extrig3 ; -- 第三级外部硬件中断信号到来 WAIT UNTIL clk = '1' ; IF NOT ( lock_out ) THEN
intp_sig3 <= interrupt3 ; END IF ;
END PROCESS interrupt3_proc ;
-- 根据中断优先级把外部硬件中断信号到来的信息代入intp中 -- 用属性'QUIET来检出中断信号的电平是否发生变化 intp <= intp_sig1 WHEN NOT ( intp_sig1'QUIET (10 ns ) ) ELSE intp_sig2 WHEN NOT ( intp_sig2'QUIET (10 ns ) ) ELSE intp_sig3 WHEN NOT ( intp_sig3'QUIET (10 ns ) ) ELSE intp ;
-- 以下是根据中断优先级对中断进行响应和处理 interrupt_handle : PROCESS BEGIN
WAIT ON intp'TRANSACTION ; -- 用来启动中断处理进程,后面详细讨论 lock_out <= TRUE ; WAIT FOR 20 ns ; CASE intp IS
WHEN interrupt1 =>
.
.
-- 第一级中断处理程序 WHEN interrupt2 =>
-- 第二级中断处理程序 WHEN interrupt3 =>
-- 第三级中断处理程序 WHEN interrupt4 =>
-- 第四级中断处理程序 END CASE ;
lock_out <= FALSE ;
END PROCESS interrupt_handle ; END ARCHITECTURE behavioral ;
【例4-】 利用属性'BASE的示例程序。
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; ENTITY base_attribute IS
END ENTITY base_attribute ;
ARCHITECTURE behavioral OF base_attribute IS -- 定义枚举数据类型cycolour
TYPE cycolour IS ( red, blue, green, yellow, brown, black ) ; -- 定义基于枚举数据类型cycolour的子类型sub_cycolour
SUBTYPE sub_cycolour IS cycolour RANGE blue TO brown ; VARIABLE temp1, temp2, temp3, temp4 : cycolour ; VARIABLE temp5, temp6, temp7, temp8 : cycolour ; VARIABLE temp9, temp10, temp11, temp12 : cycolour ; VARIABLE temp13, temp14, temp15, temp16 : cycolour ; BEGIN
PROCESS ( clk ) BEGIN
temp1 := sub_cycolour'BASE'RIGHT ; -- temp1= black temp2 := sub_cycolour'BASE'LEFT ; -- temp2= red temp3 := sub_cycolour'BASE'HIGH ; -- temp3= black temp4 := sub_cycolour'BASE'LOW ; -- temp4= red temp5 := cycolour'BASE'RIGHT ; -- temp5= black temp6 := cycolour'BASE'LEFT ; -- temp6= red temp7 := cycolour'BASE'HIGH ; -- temp7= black temp8 := cycolour'BASE'LOW ; -- temp8= red
temp9 := sub_cycolour'BASE'SUCC ( yellow ) ; -- temp9= brown temp10 := sub_cycolour'BASE'PRED ( yellow ) ; -- temp10= green temp11 := sub_cycolour'BASE'LEFTOF ( yellow ) ; -- temp11= green temp12 := sub_cycolour'BASE'RIGHTOF ( yellow ); -- temp12= brown temp13 := cycolour'BASE'SUCC ( yellow ) ; -- temp13= brown temp14 := cycolour'BASE'PRED ( yellow ) ; -- temp14= green temp15 := cycolour'BASE'LEFTOF ( yellow ) ; -- temp15= green temp16 := cycolour'BASE'RIGHTOF ( yellow ) ; -- temp16= brown END PROCESS ;
END ARCHITECTURE behavioral ;
（139）
【例4-65】 使用数据区间类属性描述语句——属性'RANGE和属性'REVERSE_ RANGE的示例程序。它们常用于循环语句，作为循环变量的范围使用。 （P140）
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; PACKAGE mypackage2 IS
FUNCTION vector2int ( cvect : STD_LOGIC_VECTOR ) -- 函数说明 .
.
RETURN INTEGER ; END mypackage2 ;
PACKAGE BODY mypackage2 IS
FUNCTION vector2int ( cvect : STD_LOGIC_VECTOR ) -- 函数定义 RETURN INTEGER IS
VARIABLE cresult : INTEGER : = 0 ; BEGIN
FOR i IN cvect'RANGE LOOP
cresult : = cresult * 2 ; -- 左移1位 IF ( cvect ( i ) = '1' ) THEN cresult : = cresult + 1 ; END IF ; END LOOP ;
RETURN cresult ; END vector2int ; END mypackage2 ;
【例4-66】 使用用户自定义属性语句ATTRIBUTE的示例程序。
PACKAGE attribute_inst IS
TYPE number_attri IS ( in_pin, out_pin, inout_pin ) ; ATTRIBUTE user_attribute : number_attri ;
ATTRIBUTE user_attribute_position : INTEGER ; END attribute_inst ; LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; LIBRARY WORK ;
USE WORK.attribute_inst.ALL ; ENTITY cyattribute IS PORT ( datain : IN STD_LOGIC ; dataout1, dataout2 : OUT STD_LOGIC ) ; END ENTITY cyattribute ;
ARCHITECTURE behavioral OF cyattribute IS COMPONENT mcu8086 GENERIC …… PORT ……
END COMPONENT ;
SIGNAL temp1 : INTEGER ;
SIGNAL temp2 : number_attri ;
ATTRIBUTE user_attribute_position OF mcu8086 : COMPONENT IS 20 ; BEGIN temp1 <= mcu8086'user_attribute ; -- 根据模块要求可以返回枚举类型in_pin、out_pin或inout_pin之一 temp2 <= mcu8086'user_attribute_position ; -- 根据模块要求可以返回元件mcu8086的位置 -- 此处由user_attribute_position决定,其值为20 END ARCHITECTURE behavioral ;
（142）
【例5-1】 一般2输入与非门电路设计的示例程序1。
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; ENTITY cynand2 IS
PORT ( datain1, datain2 : IN STD_LOGIC ; dataout : OUT STD_LOGIC ) ; END ENTITY cynand2 ;
（P146）
.
.
ARCHITECTURE behavioral OF cynand2 IS BEGIN
dataout <= datain1 NAND datain2 ; END ARCHITECTURE behavioral ;
【例5-2】 一般2输入与非门电路设计的示例程序2。
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; ENTITY cynand2 IS
PORT ( datain1, datain2 : IN STD_LOGIC ; dataout : OUT STD_LOGIC ) ; END ENTITY cynand2 ;
ARCHITECTURE behavioral_2 OF cynand2 IS BEGIN
PROCESS ( datain1, datain2 )
VARIABLE comb : STD_LOGIC_VECTOR ( 1 DOWNTO 0 ) ; BEGIN
comb := datain1 & datain2 ; CASE comb IS
WHEN \"00\" => dataout <= '1' ; WHEN \"01\" => dataout <= '1' ; WHEN \"10\" => dataout <= '1' ; WHEN \"11\" => dataout <= '0' ; WHEN OTHERS => dataout <= 'X' ; END CASE ; END PROCESS ;
END ARCHITECTURE behavioral_2 ;
（P146）
【例5-3】 调用集电极开路的2输入与非门电路的示例程序。
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; -- 一般的2输入与非门电路元件调用 LIBRARY STD ;
USE STD.STD_LOGIC.ALL ; USE STD.STD_TTL.ALL ; ENTITY cynand2 IS
PORT ( datain1, datain2 : IN STD_LOGIC ; dataout : OUT STD_LOGIC ) ; END ENTITY cynand2 ;
-- 集电极开路的2输入与非门电路元件调用 LIBRARY STD ;
USE STD.STD_LOGIC.ALL ; USE STD.STD_TTLOC.ALL ; ENTITY cynand2oc IS
PORT ( datain1, datain2 : IN STD_LOGIC ; dataout : OUT STD_LOGIC ) ; END ENTITY cynand2oc ;
（P147）
【例5-4】 2输入或非门电路设计的示例程序1。
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; ENTITY cynor2 IS
PORT ( datain1, datain2 : IN STD_LOGIC ; .
（P148）
.
dataout : OUT STD_LOGIC ) ; END ENTITY cynor2 ;
ARCHITECTURE behavioral OF cynor2 IS BEGIN
dataout <= datain1 NOR datain2 ; END ARCHITECTURE behavioral ;
【例5-5】 2输入或非门电路设计的示例程序2。
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; ENTITY cynor2 IS
PORT ( datain1, datain2 : IN STD_LOGIC ; dataout : OUT STD_LOGIC ) ; END ENTITY cynor2 ;
ARCHITECTURE behavioral_2 OF cynor2 IS BEGIN
PROCESS ( datain1, datain2 )
VARIABLE comb : STD_LOGIC_VECTOR ( 1 DOWNTO 0 ) ; BEGIN
comb := datain1 & datain2 ; CASE comb IS
WHEN \"00\" => dataout <= '1' ; WHEN \"01\" => dataout <= '0' ; WHEN \"10\" => dataout <= '0' ; WHEN \"11\" => dataout <= '0' ; WHEN OTHERS => dataout <= 'X' ; END CASE ; END PROCESS ;
END ARCHITECTURE behavioral_2 ;
（P148）
【例5-6】 反相器电路设计的行为描述方式的示例程序。
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; ENTITY cynot IS
PORT ( datain : IN STD_LOGIC ;
dataout : OUT STD_LOGIC ) ; END ENTITY cynot ;
ARCHITECTURE behavioral OF cynot IS BEGIN
dataout <= NOT datain ; END ARCHITECTURE behavioral ;
（P149）
【例5-7】 反相器电路设计的RTL描述方式的示例程序。
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; ENTITY cynot IS
PORT ( datain : IN STD_LOGIC ;
dataout : OUT STD_LOGIC ) ; END ENTITY cynot ;
ARCHITECTURE behavioral_2 OF cynot IS BEGIN
（P149）
.
.
PROCESS ( datain ) BEGIN
IF ( datain = '1' ) THEN dataout <= '0' ; ELSE
dataout <= '1' ; END IF ; END PROCESS ;
END ARCHITECTURE behavioral_2 ;
【例5-8】 2输入异或门电路设计的行为描述方式的示例程序。
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; ENTITY cyxor2 IS
PORT ( datain1, datain2 : IN STD_LOGIC ; dataout : OUT STD_LOGIC ) ; END ENTITY cyxor2 ;
ARCHITECTURE behavioral OF cyxor2 IS BEGIN
dataout <= datain1 XOR datain2 ; END ARCHITECTURE behavioral ;
（P150）
【例5-9】 2输入异或门电路设计的结构描述方式的示例程序。
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; ENTITY cyxor2 IS
PORT ( datain1, datain2 : IN STD_LOGIC ; dataout : OUT STD_LOGIC ) ; END ENTITY cyxor2 ;
ARCHITECTURE behavioral_2 OF cyxor2 IS BEGIN
PROCESS ( datain1, datain2 )
VARIABLE comb : STD_LOGIC_VECTOR ( 1 DOWNTO 0 ) ; BEGIN
comb := datain1 & datain2 ; CASE comb IS
WHEN \"00\" => dataout <= '0' ; WHEN \"01\" => dataout <= '1' ; WHEN \"10\" => dataout <= '1' ; WHEN \"11\" => dataout <= '0' ; WHEN OTHERS => dataout <= 'X' ; END CASE ; END PROCESS ;
END ARCHITECTURE behavioral_2 ;
（P150）
【例5-10】 2输入同或门电路设计的行为描述方式的示例程序。
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; ENTITY cynxor2 IS
PORT ( datain1, datain2 : IN STD_LOGIC ; dataout : OUT STD_LOGIC ) ; END ENTITY cynxor2 ; .
（P151）
.
ARCHITECTURE behavioral OF cynxor2 IS BEGIN
dataout <= NOT ( datain1 XOR datain2 ) ; END ARCHITECTURE behavioral ;
【例5-11】 2输入同或门电路设计的结构描述方式的示例程序。
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; ENTITY cynxor2 IS
PORT ( datain1, datain2 : IN STD_LOGIC ; dataout : OUT STD_LOGIC ) ; END ENTITY cynxor2 ;
ARCHITECTURE behavioral_2 OF cynxor2 IS BEGIN
PROCESS ( datain1, datain2 )
VARIABLE comb : STD_LOGIC_VECTOR ( 1 DOWNTO 0 ) ; BEGIN
comb := datain1 & datain2 ; CASE comb IS
WHEN \"00\" => dataout <= '1' ; WHEN \"01\" => dataout <= '0' ; WHEN \"10\" => dataout <= '0' ; WHEN \"11\" => dataout <= '1' ; WHEN OTHERS => dataout <= 'X' ; END CASE ; END PROCESS ;
END ARCHITECTURE behavioral_2 ;
（P152）
【例5-12】 3输入或门电路设计的行为描述方式的示例程序。
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; ENTITY cyor3 IS
PORT ( datain1, datain2, datain3 : IN STD_LOGIC ; dataout : OUT STD_LOGIC ) ; END ENTITY cyor3 ;
ARCHITECTURE behavioral OF cyor3 IS BEGIN
dataout <= datain1 OR datain2 OR datain3 ; END ARCHITECTURE behavioral ;
（P153）
【例5-13】 3输入或门电路设计的结构描述方式的示例程序。
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; ENTITY cyor3 IS
PORT ( datain1, datain2, datain3 : IN STD_LOGIC ; dataout : OUT STD_LOGIC ) ; END ENTITY cyor3 ;
ARCHITECTURE behavioral_2 OF cyor3 IS BEGIN
PROCESS ( datain1, datain2, datain3 )
VARIABLE comb : STD_LOGIC_VECTOR ( 2 DOWNTO 0 ) ; BEGIN
（P153）
.
.
comb := datain1 & datain2 & datain3 ; CASE comb IS
WHEN \"000\" => dataout <= '0' ; WHEN \"001\" => dataout <= '1' ; WHEN \"010\" => dataout <= '1' ; WHEN \"011\" => dataout <= '1' ; WHEN \"100\" => dataout <= '1' ; WHEN \"101\" => dataout <= '1' ; WHEN \"110\" => dataout <= '1' ; WHEN \"111” => dataout <= '1' ; WHEN OTHERS => dataout <= 'X' ; END CASE ; END PROCESS ;
END ARCHITECTURE behavioral_2 ;
【例5-14】 4输入与非门电路设计的行为描述方式的示例程序。
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; ENTITY cynand4 IS
PORT ( datain1, datain2 : IN STD_LOGIC ; datain3, datain4 : IN STD_LOGIC ; dataout : OUT STD_LOGIC ) ; END ENTITY cynand4 ;
ARCHITECTURE behavioral OF cynand4 IS BEGIN
dataout <= NOT ( datain1 AND datain2 AND datain3 AND datain4 ) ; END ARCHITECTURE behavioral ;
（P1）
【例5-15】 4输入与非门电路设计的结构描述方式的示例程序。
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; ENTITY cynand4 IS
PORT ( datain1, datain2 : IN STD_LOGIC ; datain3, datain4 : IN STD_LOGIC ; dataout : OUT STD_LOGIC ) ; END ENTITY cynand4 ;
ARCHITECTURE behavioral_2 OF cynand4 IS BEGIN
PROCESS ( datain1, datain2, datain3, datain4 )
VARIABLE comb : STD_LOGIC_VECTOR ( 3 DOWNTO 0 ) ; BEGIN
comb := datain1 & datain2 & datain3 & datain4 ; CASE comb IS
WHEN \"0000\" => dataout <= '1' ; WHEN \"0001\" => dataout <= '1' ; WHEN \"0010\" => dataout <= '1' ; WHEN \"0011\" => dataout <= '1' ; WHEN \"0100\" => dataout <= '1' ; WHEN \"0101\" => dataout <= '1' ; WHEN \"0110\" => dataout <= '1' ; WHEN \"0111\" => dataout <= '1' ; WHEN \"1000\" => dataout <= '1' ; WHEN \"1001\" => dataout <= '1' ; WHEN \"1010\" => dataout <= '1' ; WHEN \"1011\" => dataout <= '1' ; .
（P1）
.
WHEN \"1100\" => dataout <= '1' ; WHEN \"1101\" => dataout <= '1' ; WHEN \"1110\" => dataout <= '1' ; WHEN \"1111\" => dataout <= '0' ; WHEN OTHERS => dataout <= 'X' ; END CASE ; END PROCESS ;
END ARCHITECTURE behavioral_2 ;
【例5-16】 采用IF-ELSE语句实现2选1选择器的示例程序。
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; ENTITY cy2_1mux IS PORT ( datain1, datain2 : IN STD_LOGIC ; sel : IN STD_LOGIC ;
dataout : OUT STD_LOGIC ) ; END ENTITY cy2_1mux ;
ARCHITECTURE rtl OF cy2_1mux IS BEGIN
cy21mux_inst : PROCESS ( datain1, datain2, sel ) BEGIN
-- 采用IF-ELSE语句描述2选1电路的选通控制信号
IF ( sel = '1' ) THEN -- 2选择的IF-ELSE语句 dataout <= datain1 ; ELSE
dataout <= datain2 ; END IF ;
END PROCESS cy21mux_inst ; END ARCHITECTURE rtl ;
（P156）
【例5-17】 采用CASE语句实现2选1选择器的示例程序。
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; ENTITY cy2_1mux IS PORT ( datain1, datain2 : IN STD_LOGIC ; sel : IN STD_LOGIC ;
dataout : OUT STD_LOGIC ) ; END ENTITY cy2_1mux ;
ARCHITECTURE rtl OF cy2_1mux IS BEGIN
cy21mux_inst : PROCESS ( datain1, datain2, sel ) BEGIN
-- 采用CASE语句描述2选1电路的选通控制信号
CASE sel IS -- CASE语句的控制表达式是 sel WHEN '0' => dataout <= datain2 ; WHEN '1' => dataout <= datain1 ; WHEN OTHERS => dataout <= '0' ; END CASE ;
END PROCESS cy21mux_inst ; END ARCHITECTURE rtl ;
（P157）
【例5-18】 采用IF-ELSIF-ELSE语句实现16选1选择器的示例程序。 （P158）
LIBRARY IEEE ; .
.
USE IEEE.STD_LOGIC_11.ALL ; ENTITY cy16_1mux IS
PORT ( gn : IN STD_LOGIC ;
datain : IN STD_LOGIC_VECTOR ( 15 DOWNTO 0 ) ; sel : IN STD_LOGIC_VECTOR ( 3 DOWNTO 0 ) ; dataout : OUT STD_LOGIC ) ; END ENTITY cy16_1mux ;
ARCHITECTURE rtl OF cy16_1mux IS BEGIN
c161mux_inst : PROCESS ( gn, datain, sel ) BEGIN
IF ( gn = '0' ) THEN -- 全局控制信号gn
IF ( sel = \"0000\" ) THEN -- 选通控制信号sel dataout <= datain ( 0 ) ; ELSIF ( sel = \"0001\" ) THEN dataout <= datain ( 1 ) ; ELSIF ( sel = \"0010\" ) THEN dataout <= datain ( 2 ) ; ELSIF ( sel = \"0011\" ) THEN dataout <= datain ( 3 ) ; ELSIF ( sel = \"0100\" ) THEN dataout <= datain ( 4 ) ; ELSIF ( sel = \"0101\" ) THEN dataout <= datain ( 5 ) ; ELSIF ( sel = \"0110\" ) THEN dataout <= datain ( 6 ) ; ELSIF ( sel = \"0111\" ) THEN dataout <= datain ( 7 ) ; ELSIF ( sel = \"1000\" ) THEN dataout <= datain ( 8 ) ; ELSIF ( sel = \"1001\" ) THEN dataout <= datain ( 9 ) ; ELSIF ( sel = \"1010\" ) THEN dataout <= datain ( 10 ) ; ELSIF ( sel = \"1011\" ) THEN dataout <= datain ( 11 ) ; ELSIF ( sel = \"1100\" ) THEN dataout <= datain ( 12 ) ; ELSIF ( sel = \"1101\" ) THEN dataout <= datain ( 13 ) ; ELSIF ( sel = \"1110\" ) THEN dataout <= datain ( 14 ) ; ELSE
dataout <= datain ( 15 ) ; END IF ; ELSE
dataout <= '0' ; END IF ;
END PROCESS c161mux_inst ; END ARCHITECTURE rtl ;
【例5-19】 采用IF-ELSE语句实现BCD输出的10线-4线优先级编码器电路的示例程序。（P160）
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; ENTITY cypriority_encoder IS PORT ( datain : IN STD_LOGIC_VECTOR ( 1 TO 9 ) ; dataout : OUT STD_LOGIC_VECTOR ( 3 DOWNTO 0 ) .
.
) ;
END ENTITY cypriority_encoder ;
ARCHITECTURE rtl OF cypriority_encoder IS BEGIN
PROCESS ( datain ) BEGIN IF ( datain = \"111111111\" ) THEN dataout <= \"1111\" ; ELSE IF ( datain (9) = '0' ) THEN dataout <= \"0110\" ; ELSIF ( datain (8) = '0' ) THEN dataout <= \"0111\" ; ELSIF ( datain (7) = '0' ) THEN dataout <= \"1000\" ; ELSIF ( datain (6) = '0' ) THEN dataout <= \"1001\" ; ELSIF ( datain (5) = '0' ) THEN dataout <= \"1010\" ; ELSIF ( datain (4) = '0' ) THEN dataout <= \"1011\" ; ELSIF ( datain (3) = '0' ) THEN dataout <= \"1100\" ; ELSIF ( datain (2) = '0' ) THEN dataout <= \"1101\" ; ELSIF ( datain (1) = '0' ) THEN dataout <= \"1110\" ; ELSE
dataout <= \"1111\" ; END IF ; END IF ; END PROCESS ;
END ARCHITECTURE rtl ;
【例5-20】 4线-16线译码器电路的示例程序。
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; ENTITY cydecoder_4_16 IS
PORT ( D, C, B, A : IN STD_LOGIC ; G1N, G2N : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR ( 15 DOWNTO 0 ) ) ; END ENTITY cydecoder_4_16 ;
ARCHITECTURE rtl OF cydecoder_4_16 IS
SIGNAL temp_datain : STD_LOGIC_VECTOR ( 3 DOWNTO 0 ) ; BEGIN
temp_datain <= D & C & B & A ; PROCESS ( D, C, B, A, G1N, G2N ) BEGIN IF ( G1N = '0' AND G2N ='0') THEN -- 译码器的选通信号低电平有效 -- 采用CASE语句描述4-16译码电路 CASE temp_datain IS -- CASE语句的条件表达式是位矢量 temp_datain WHEN \"0000\" => q <= \"1111111111111110\" ; WHEN \"0001\" => q <= \"1111111111111101\" ; WHEN \"0010\" => q <= \"1111111111111011\" ; WHEN \"0011\" => q <= \"1111111111110111\" ; WHEN \"0100\" => q <= \"1111111111101111\" ; WHEN \"0101\" => q <= \"1111111111011111\" ; WHEN \"0110\" => q <= \"1111111110111111\" ; WHEN \"0111\" => q <= \"1111111101111111\" ; .
（P162）
.
WHEN \"1000\" => q <= \"1111111011111111\" ; WHEN \"1001\" => q <= \"1111110111111111\" ; WHEN \"1010\" => q <= \"1111101111111111\" ; WHEN \"1011\" => q <= \"1111011111111111\" ; WHEN \"1100\" => q <= \"1110111111111111\" ; WHEN \"1101\" => q <= \"1101111111111111\" ; WHEN \"1110\" => q <= \"1011111111111111\" ; WHEN \"1111\" => q <= \"0111111111111111\" ; WHEN OTHERS => q <= \"XXXXXXXXXXXXXXXX\" ; END CASE ; ELSE q <= \"1111111111111111\" ; END IF ;
END PROCESS ;
END ARCHITECTURE rtl ;
【例5-21】 BCD码输入的4线-10线译码器电路的示例程序。
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; ENTITY cybcddecoder_4_10 IS
PORT ( D, C, B, A : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR ( 0 TO 9 ) ) ; END ENTITY cybcddecoder_4_10 ;
ARCHITECTURE rtl OF cybcddecoder_4_10 IS
SIGNAL temp_datain : STD_LOGIC_VECTOR ( 3 DOWNTO 0 ) ; BEGIN
temp_datain <= D & C & B & A ; PROCESS ( temp_datain ) BEGIN
-- 采用CASE语句描述BCD码输入的4线-10线译码电路
CASE temp_datain IS -- CASE语句的条件表达式是位矢量 temp_datain WHEN \"0000\" => q <= \"1111111110\" ; WHEN \"0001\" => q <= \"1111111101\" ; WHEN \"0010\" => q <= \"\"1111111011\" ; WHEN \"0011\" => q <= \"1111110111\" ; WHEN \"0100\" => q <= \"1111101111\" ; WHEN \"0101\" => q <= \"1111011111\" ; WHEN \"0110\" => q <= \"1110111111\" ; WHEN \"0111\" => q <= \"1101111111\" ; WHEN \"1000\" => q <= \"1011111111\" ; WHEN \"1001\" => q <= \"0111111111\" ; WHEN OTHERS => q <= \"1111111111\" ; END CASE ; END PROCESS ;
END ARCHITECTURE rtl ;
（P1）
【例5-22】 多种方法实现三态门电路的示例程序。
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; ENTITY triple_buffer IS
GENERIC ( cydelay_1, cydelay_2 : TIME ) ; PORT ( datain, en : IN STD_LOGIC ; dataout : OUT STD_LOGIC ) ; END ENTITY triple_buffer ;
-- 第一种方法用进程里的IF语句来实现
ARCHITECTURE tri_method1 OF triple_buffer IS
（P166）
.
.
BEGIN
triple_method1 : PROCESS ( datain, en ) BEGIN
IF ( en = '1' ) THEN
dataout <= datain AFTER cydelay_1 ; ELSE
dataout <= 'Z' AFTER cydelay_2 ; END IF ;
END PROCESS triple_method1 ; END ARCHITECTURE tri_method1 ;
-- 第二种方法用Guarded BLOCK语句来实现
ARCHITECTURE tri_method2 OF triple_buffer IS BEGIN
triple_method2 : BLOCK ( en = '1' ) BEGIN
dataout <= GUARDED datain ; END BLOCK triple_method2 ; END ARCHITECTURE tri_method2 ; -- 第三种方法用进程里的CASE语句来实现
ARCHITECTURE tri_method3 OF triple_buffer IS BEGIN
triple_method3 : PROCESS ( datain, en ) BEGIN
CASE en IS
WHEN '1' => dataout <= datain ; WHEN OTHERS => dataout <= 'Z' ; END CASE ;
END PROCESS triple_method3 ; END ARCHITECTURE tri_method3 ;
【例5-23】 两种方法实现74244形式的单向总线缓冲器的示例程序。
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; ENTITY single_buffer_74244 IS
PORT ( en_1, en_2 : IN STD_LOGIC ; datain_1, datain_2 : IN STD_LOGIC_VECTOR ( 3 DOWNTO 0 ) ;
dataout_1, dataout_2 : OUT STD_LOGIC_VECTOR ( 3 DOWNTO 0 ) ) ; END ENTITY single_buffer_74244 ; -- 第一种方法用两个进程语句来实现
ARCHITECTURE buffer_74244_method1 OF single_buffer_74244 IS BEGIN method1_1 : PROCESS ( datain_1, en_1 ) BEGIN IF ( en_1 = '0' ) THEN -- 选通信号是低电平有效的 dataout_1 <= datain_1 ; ELSE dataout_1 <= \"ZZZZ\" ; END IF ; END PROCESS method1_1 ; method1_2 : PROCESS ( datain_2, en_2 ) BEGIN IF ( en_2 = '0' ) THEN dataout_2 <= datain_2 ; ELSE dataout_2 <= \"ZZZZ\" ; END IF ; END PROCESS method1_2 ;
END ARCHITECTURE buffer_74244_method1 ;
-- 第二种方法用Guarded BLOCK语句和进程语句并行实现
（P168）
.
.
ARCHITECTURE buffer_74244_method2 OF single_buffer_74244 IS BEGIN method2_block : BLOCK ( en_1 = '0' ) BEGIN dataout_1 <= GUARDED datain_1 ; END BLOCK method2_block ; method2_process : PROCESS ( datain_2, en_2 ) BEGIN IF ( en_2 = '0' ) THEN -- 选通信号是低电平有效的 dataout_2 <= datain_2 ; ELSE dataout_2 <= \"ZZZZ\" ; END IF ; END PROCESS method2_process ;
END ARCHITECTURE buffer_74244_method2 ;
【例5-24】 实现74245形式的双向总线缓冲器电路的VHDL示例程序。
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; ENTITY double_buffer_74245 IS
PORT ( oe, dir : IN STD_LOGIC ; dataA, dataB : INOUT STD_LOGIC_VECTOR ( 7 DOWNTO 0 ) ) ; END ENTITY double_buffer_74245 ;
ARCHITECTURE behavioral OF double_buffer_74245 IS SIGNAL outA, outB : STD_LOGIC_VECTOR ( 7 DOWNTO 0 ) ; BEGIN instA_74245 : PROCESS ( oe, dir, dataA ) -- 数据从A流向B BEGIN IF ( ( oe = '0' ) AND ( dir = '1' ) ) THEN -- 输出使能信号oe是低电平有效的 outB <= dataA ; ELSE outB <= \"ZZZZZZZZ\" ; END IF ; dataB <= outB ; END PROCESS instA_74245 ; instB_74245 : PROCESS ( oe, dir, dataB ) -- 数据从B流向A BEGIN IF ( ( oe = '0' ) AND ( dir = '0' ) ) THEN -- 输出使能信号oe是低电平有效的 outA <= dataB ; ELSE outA <= \"ZZZZZZZZ\" ; END IF ; dataA <= outA ; END PROCESS instB_74245 ; END ARCHITECTURE behavioral ;
（P169）
【例5-25】 半加器电路的VHDL示例程序。
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; ENTITY half_adder IS
PORT( dataA, dataB : IN STD_LOGIC ; sum : OUT STD_LOGIC ;
（P171）
.
.
carry : OUT STD_LOGIC ) ; END ENTITY half_adder ;
ARCHITECTURE dataflow OF half_adder IS BEGIN
sum <= dataA XOR dataB ; -- 和数满足逻辑异或关系 carry <= dataA AND dataB ; -- 进位位满足逻辑与关系 END ARCHITECTURE dataflow ;
【例5-26】 直接根据真值表设计的全加器电路的VHDL示例程序。 （P172）
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; ENTITY full_adder IS
PORT ( dataA, dataB, carryin : IN STD_LOGIC ; sum : OUT STD_LOGIC ;
carryout : OUT STD_LOGIC ) ; END ENTITY full_adder ;
ARCHITECTURE rtl OF full_adder IS BEGIN
sum <= dataA XOR dataB XOR carryin ; -- 和数满足逻辑异或关系
carryout <= ( dataA AND dataB ) OR ( dataA AND carryin ) OR ( dataB AND carryin ) ;
END ARCHITECTURE rtl ;
【例5-27】 由两个半加器元件和一个或门构成的全加器电路的VHDL示例程序。（P173）
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; ENTITY full_adder IS
PORT ( dataA, dataB, carryin : IN STD_LOGIC ; sum : OUT STD_LOGIC ;
carryout : OUT STD_LOGIC ) ; END ENTITY full_adder ;
ARCHITECTURE struct OF full_adder IS COMPONENT half_adder
PORT( a, b : IN STD_LOGIC ; s : OUT STD_LOGIC ; ca : OUT STD_LOGIC ) ; END COMPONENT ;
SIGNAL u1sum, u1carry, u2carry : STD_LOGIC ; BEGIN
u1 : half_adder PORT MAP ( dataA, dataB, u1sum, u1carry ) ; u2 : half_adder PORT MAP ( u1sum, carryin, sum, u2carry ) ; carryout <= u2carry OR u1carry ; END ARCHITECTURE struct ;
【例5-28】 采用行波进位的4位加法器电路的VHDL示例程序。
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; ENTITY ripple_full_adder IS
PORT ( dataA, dataB : IN STD_LOGIC_VECTOR ( 3 DOWNTO 0 ) ; carryin : IN STD_LOGIC ; .
（P173）
.
sum : OUT STD_LOGIC_VECTOR ( 3 DOWNTO 0 ) ; carryout : OUT STD_LOGIC ) ; END ENTITY ripple_full_adder ;
ARCHITECTURE rtl_ripple_fulladder OF ripple_full_adder IS
SIGNAL temp1, temp2, temp3 : STD_LOGIC_VECTOR ( 3 DOWNTO 0 ) ; BEGIN
inst_ripple_full_adder : PROCESS (dataA, dataB, carryin ) BEGIN
temp1 ( 0 ) <= dataA ( 0 ) XOR dataB ( 0 ) ; temp1 ( 1 ) <= dataA ( 1 ) XOR dataB ( 1 ) ; temp1 ( 2 ) <= dataA ( 2 ) XOR dataB ( 2 ) ; temp1 ( 3 ) <= dataA ( 3 ) XOR dataB ( 3 ) ;
temp2 ( 0 ) <= dataA ( 0 ) AND dataB ( 0 ) ; temp2 ( 1 ) <= dataA ( 1 ) AND dataB ( 1 ) ; temp2 ( 2 ) <= dataA ( 2 ) AND dataB ( 2 ) ; temp2 ( 3 ) <= dataA ( 3 ) AND dataB ( 3 ) ;
temp3 ( 0 ) <= temp2 ( 0 ) OR ( temp1 ( 0 ) AND carryin ) ; temp3 ( 1 ) <= temp2 ( 1 ) OR ( temp1 ( 1 ) AND temp2 ( 0 ) ) OR ( temp1 ( 1 ) AND temp1 ( 0 ) AND carryin ) ; temp3 ( 2 ) <= temp2 ( 2 ) OR ( temp1 ( 2 ) AND temp2 ( 1 ) ) OR ( temp1 ( 2 ) AND temp1 ( 1 ) AND temp2 ( 0 ) )
OR ( temp1 ( 2 ) AND temp1 ( 1 ) AND temp1 ( 0 ) AND carryin ) ;
temp3 ( 3 ) <= temp2 ( 3 ) OR ( temp1 ( 3 ) AND temp2 ( 2 ) ) OR ( temp1 ( 3 ) AND temp1 ( 2 ) AND temp2 ( 1 ) ) OR ( temp1 ( 3 ) AND temp1 ( 2 ) AND temp1 ( 1 ) AND temp2 ( 0 ) ) OR ( temp1 ( 3 ) AND temp1 ( 2 ) AND temp1 ( 1 ) AND temp1 ( 0 ) AND carryin ) ; carryout <= temp3 ( 3 ) ; -- 进位位信号
sum ( 0 ) <= dataA ( 0 ) XOR dataB ( 0 ) XOR temp3 ( 0 ) ; -- 和数最低位 sum ( 1 ) <= dataA ( 1 ) XOR dataB ( 1 ) XOR temp3 ( 1 ) ; -- 和数次低位 sum ( 2 ) <= dataA ( 2 ) XOR dataB ( 2 ) XOR temp3 ( 2 ) ; -- 和数次高位 sum ( 3 ) <= dataA ( 3 ) XOR dataB ( 3 ) XOR temp3 ( 3 ) ; -- 和数最高位 END PROCESS inst_ripple_full_adder ; END ARCHITECTURE rtl_ripple_fulladder ;
【例5-29】 基于兆函数LPM_ADD_SUB模块生成的自定制加/减法电路的VHDL示例程序。 （P176）
LIBRARY ieee ;
USE ieee.std_logic_11.all ; LIBRARY lpm ;
USE lpm.lpm_components.all ; ENTITY cystudy1 IS PORT ( add_sub : IN STD_LOGIC ; dataa : IN STD_LOGIC_VECTOR ( 9 DOWNTO 0 ) ; datab : IN STD_LOGIC_VECTOR ( 9 DOWNTO 0 ) ; cin : IN STD_LOGIC ; result : OUT STD_LOGIC_VECTOR ( 9 DOWNTO 0 ) ; cout : OUT STD_LOGIC ; overflow : OUT STD_LOGIC ); END cystudy1 ; .
.
ARCHITECTURE SYN OF cystudy1 IS SIGNAL sub_wire0 : STD_LOGIC ; SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC_VECTOR ( 9 DOWNTO 0 ) ; COMPONENT lpm_add_sub GENERIC ( lpm_width : NATURAL ; lpm_direction : STRING ; lpm_type : STRING ; lpm_hint : STRING ) ;
PORT ( dataa : IN STD_LOGIC_VECTOR ( 9 DOWNTO 0 ) ; add_sub : IN STD_LOGIC ; datab : IN STD_LOGIC_VECTOR ( 9 DOWNTO 0 ) ; overflow : OUT STD_LOGIC ; cin : IN STD_LOGIC ; cout : OUT STD_LOGIC ; result : OUT STD_LOGIC_VECTOR ( 9 DOWNTO 0 ) ) ; END COMPONENT ; BEGIN overflow <= sub_wire0 ; cout <= sub_wire1 ; result <= sub_wire2 ( 9 DOWNTO 0 ) ; lpm_add_sub_component : lpm_add_sub GENERIC MAP ( lpm_width => 10 , lpm_direction => \"UNUSED\" , lpm_type => \"LPM_ADD_SUB\" , lpm_hint => \"ONE_INPUT_IS_CONSTANT = NO, CIN_USED=YES\" ) PORT MAP ( dataa => dataa , add_sub => add_sub , datab => datab , cin => cin , overflow => sub_wire0 , cout => sub_wire1 , result => sub_wire2 ) ; END ARCHITECTURE SYN ;
【例5-30】 采用行为描述方法的16位求补器电路的示例程序。
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; ENTITY complement IS
PORT ( datain : IN STD_LOGIC_VECTOR ( 15 DOWNTO 0 ) ;
dataout : OUT STD_LOGIC_VECTOR ( 15 DOWNTO 0 ) ) ; END ENTITY complement ;
ARCHITECTURE behavioral OF complement IS
SIGNAL temp : STD_LOGIC_VECTOR ( 15 DOWNTO 0 ) ; BEGIN
temp <= NOT datain ; -- 对输入数据取反
dataout <= temp + \"0000000000000001\" ; -- 对反码加1 END ARCHITECTURE behavioral ;
（P178）
【例5-31】 4位×4位原码移位的乘法器电路的示例程序。
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; USE WORK.STD_ARITH.ALL ; .
（P179）
.
ENTITY multiplier_4_4 IS -- 表示4位×4位乘法器
PORT ( dataA, dataB : IN STD_LOGIC_VECTOR ( 3 DOWNTO 0 ) ; product : OUT STD_LOGIC_VECTOR ( 7 DOWNTO 0 ) ; cydone : OUT STD_LOGIC ) ; END ENTITY multiplier_4_4 ;
ARCHITECTURE behavioral OF multiplier_4_4 IS BEGIN
inst_multiplier : PROCESS ( dataA, dataB ) VARIABLE dataA_temp, dataB_temp, temp : STD_LOGIC_VECTOR ( 3 DOWNTO 0 ) ; VARIABLE temp_count : INTEGER ; BEGIN
dataA_temp := dataA ; dataB_temp := dataB ; temp := \"0000\" ; temp_count := 0 ; cydone <= '0' ;
WHILE temp_count < 4 LOOP -- 采用WHILE-LOOP循环进行移位相加 IF ( dataA ( temp_count ) = '1' ) THEN temp := temp + dataB_temp ; END IF ;
dataA_temp := temp ( 0 ) & dataA_temp ( 3 DOWNTO 1 ) ; temp := '0' & temp ( 3 DOWNTO 1 ) ; temp_count := temp_count + 1 ; END LOOP ;
product <= temp & dataA_temp ; -- 并置运算构成8位乘法结果 cydone <= '1' ;
END PROCESS inst_multiplier ; END ARCHITECTURE behavioral ;
【例5-32】 基于兆函数LPM_MULT模块生成的自定制8位×8位无符号乘法器电路的VHDL示例程序。 （P180）
-- megafunction wizard : % LPM_MULT % -- Megafunction Name (s) : lpm_mult LIBRARY ieee ;
USE ieee.std_logic_11.all ; LIBRARY lpm ;
USE lpm.lpm_components.all ; ENTITY lpm_mult0 IS
PORT ( dataa : IN STD_LOGIC_VECTOR ( 7 DOWNTO 0 ) ; datab : IN STD_LOGIC_VECTOR ( 7 DOWNTO 0 ) ; result : OUT STD_LOGIC_VECTOR ( 15 DOWNTO 0 ) ) ; END ENTITY lpm_mult0 ;
ARCHITECTURE SYN OF lpm_mult0 IS SIGNAL sub_wire0 : STD_LOGIC_VECTOR ( 15 DOWNTO 0 ) ; COMPONENT lpm_mult
GENERIC ( lpm_widtha : NATURAL ; lpm_widthb : NATURAL ; lpm_widthp : NATURAL ; lpm_widths : NATURAL ; lpm_type : STRING ; lpm_representation : STRING ; lpm_hint : STRING ) ; PORT ( dataa : IN STD_LOGIC_VECTOR ( 7 DOWNTO 0 ); datab : IN STD_LOGIC_VECTOR ( 7 DOWNTO 0 ); result : OUT STD_LOGIC_VECTOR ( 15 DOWNTO 0 ) END COMPONENT ; .
) ;
.
BEGIN result <= sub_wire0 ( 15 DOWNTO 0 ) ; lpm_mult_component : lpm_mult GENERIC MAP ( lpm_widtha => 8 , lpm_widthb => 8 , lpm_widthp => 16 , lpm_widths => 1 , lpm_type => \"LPM_MULT\" , lpm_representation => \"UNSIGNED\" , lpm_hint => \"MAXIMIZE_SPEED=5\" ) PORT MAP ( dataa => dataa , datab => datab , result => sub_wire0 ) ; END ARCHITECTURE SYN ;
【例5-33】 4位输入数据的一般数值比较器的VHDL示例程序。
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ;
ENTITY comparator_4 IS -- 表示4位数值比较器
PORT ( dataA, dataB : IN STD_LOGIC_VECTOR ( 3 DOWNTO 0 ) ; greater_bit : OUT STD_LOGIC ; -- A大于B的标志输出信号 equal_bit : OUT STD_LOGIC ; -- A等于B的标志输出信号 less_bit : OUT STD_LOGIC ) ; -- A小于B的标志输出信号 END ENTITY comparator_4 ;
ARCHITECTURE behavioral OF comparator_4 IS BEGIN
inst_comparator : PROCESS ( dataA, dataB ) BEGIN
FOR i IN 3 DOWNTO 0 LOOP IF ( dataA ( i ) = '1' AND dataB ( i ) = '0' ) THEN greater_bit <= '1' ; equal_bit <= '0' ; less_bit <= '0' ; EXIT ; -- 已经判断出dataA> dataB,则跳出循环 ELSIF ( dataA ( i ) = '0' AND dataB ( i ) = '1' ) THEN greater_bit <= '0' ; equal_bit <= '0' ; less_bit <= '1' ; EXIT ; -- 已经判断出dataA< dataB,则跳出循环 ELSE greater_bit <= '0' ; equal_bit <= '1' ; less_bit <= '0' ; -- 此时判断出dataA=dataB END IF ; END LOOP ;
END PROCESS inst_comparator ; END ARCHITECTURE behavioral ;
（P182）
【例5-34】 基于兆函数LPM_COMPARE模块生成的自定制8位与8位无符号数据比较器电路的VHDL示例程序。 （P184）
-- megafunction wizard : % LPM_COMPARE % -- Megafunction Name (s) : lpm_compare LIBRARY ieee ;
USE ieee.std_logic_11.all ; .
.
LIBRARY lpm ;
USE lpm.lpm_components.all ; ENTITY lpm_compare_inst IS PORT ( dataa : IN STD_LOGIC_VECTOR ( 7 DOWNTO 0 ) ; datab : IN STD_LOGIC_VECTOR ( 7 DOWNTO 0 ) ; AeB : OUT STD_LOGIC ; AgB : OUT STD_LOGIC ; AgeB : OUT STD_LOGIC ; AlB : OUT STD_LOGIC ; AleB : OUT STD_LOGIC ) ; END ENTITY lpm_compare_inst ;
ARCHITECTURE SYN OF lpm_compare_inst IS SIGNAL sub_wire0 : STD_LOGIC ; SIGNAL sub_wire1 : STD_LOGIC ; SIGNAL sub_wire2 : STD_LOGIC ; SIGNAL sub_wire3 : STD_LOGIC ; SIGNAL sub_wire4 : STD_LOGIC ; COMPONENT lpm_compare GENERIC ( lpm_width : NATURAL ; lpm_type : STRING ; lpm_representation : STRING ) ; PORT ( dataa : IN STD_LOGIC_VECTOR ( 7 DOWNTO 0 ) ; datab : IN STD_LOGIC_VECTOR ( 7 DOWNTO 0 ) ; AgeB : OUT STD_LOGIC ; AlB : OUT STD_LOGIC ; AleB : OUT STD_LOGIC ; AgB : OUT STD_LOGIC ; AeB : OUT STD_LOGIC ) ; END COMPONENT ; BEGIN AgeB <= sub_wire0 ; AlB <= sub_wire1 ; AleB <= sub_wire2 ; AgB <= sub_wire3 ; AeB <= sub_wire4 ; lpm_compare_component : lpm_compare GENERIC MAP ( lpm_width => 8 , lpm_type => \"LPM_COMPARE\" , lpm_representation => \"UNSIGNED\" ) PORT MAP ( dataa => dataa , datab => datab , AgeB => sub_wire0 , AlB => sub_wire1 , AleB => sub_wire2 , AgB => sub_wire3 , AeB => sub_wire4 ) ; END ARCHITECTURE SYN ;
【例5-35】 对8位输入数据进行移位的VHDL示例程序。
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ;
ENTITY shifter_8 IS -- 表示8位移位器电路
PORT ( datain : IN STD_LOGIC_VECTOR ( 7 DOWNTO 0 ) ; -- 8位输入数据 shift_left, shift_right : IN STD_LOGIC ; -- 左移、右移控制位 in_left, in_right : IN STD_LOGIC ; -- 左移、右移后的代入值 .
（P185）
.
dataout : OUT STD_LOGIC_VECTOR ( 7 DOWNTO 0 ) ); -- 8位输出数据 END ENTITY shifter_8 ;
ARCHITECTURE behavioral OF shifter_8 IS BEGIN
inst_shifter : PROCESS ( datain, shift_left, shift_right, in_left, in_right ) VARIABLE temp : STD_LOGIC_VECTOR ( 1 DOWNTO 0 ) ; BEGIN
temp := shift_right & shift_left ; CASE temp IS
WHEN \"00\" => dataout <= datain ; -- 不变
WHEN \"01\" => dataout <= datain ( 6 DOWNTO 0 ) & in_left ; --左移
WHEN \"10\" => dataout <= in_right & datain ( 7 DOWNTO 1 ) ; --右移 WHEN \"11\" => dataout <= datain ; -- 不变 WHEN OTHERS => NULL ; -- 空操作 END CASE ;
END PROCESS inst_shifter ; END ARCHITECTURE behavioral ;
【例6-1】 显式表示时钟敏感信号（上升沿）的示例程序。
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; ENTITY clock_inst IS
END ENTITY clock_inst ;
PROCESS ( clock_signal ) -- 显式表示 BEGIN
IF ( clock_signal = '1' ) THEN 其他处理语句; END IF ; END PROCESS ;
(P191)
【例6-2】 隐式表示时钟敏感信号（下降沿）的示例程序。
(P192)
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; ENTITY clock_inst IS
END ENTITY clock_inst ; PROCESS BEGIN
WAIT ON ( clock_signal ) UNTIL ( clock_signal = '0' ) ; -- 隐式表示
其他处理语句；
END PROCESS ;
【例6-3】 VHDL程序中描述时序电路同步复位的示例程序。
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ;
(P193)
.
.
ENTITY clock_inst IS
END ENTITY clock_inst ;
xianshi : PROCESS ( clock_signal ) -- 显式表示 BEGIN
IF ( clock_signal_condition ) THEN
IF ( synchronization_reset_condition ) THEN signal_n <= reset_value_n ; temp_n := reset_value_temp ; ELSE
其他处理语句； END IF ; END IF ;
END PROCESS xianshi ;
yinshi : PROCESS BEGIN
WAIT ON ( clock_signal ) UNTIL ( clock_signal_condition ) ; -- 隐式表示 IF ( reset_condition ) THEN
signal_n <= reset_value_n ; temp_n := reset_value_temp ; ELSE
其他处理语句； END IF ;
END PROCESS yinshi ;
【例6-4】 VHDL程序中描述时序电路异步复位的示例程序。
(P194)
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; ENTITY clock_inst IS
END ENTITY clock_inst ;
xianshi : PROCESS ( clock_signal, asynchronous_reset_signal ) -- 显式表示 BEGIN
IF ( asynchronous_reset_condition ) THEN signal_n <= reset_value_n ; temp_n := reset_value_temp ;
ELSIF ( clock_signal_condition ) THEN
其他处理语句； -- 复位条件不成立时执行时序电路的正常行为 ELSE
其他处理语句； END IF ;
END PROCESS xianshi ;
yinshi : PROCESS BEGIN
WAIT ON ( clock_signal, asynchronous_reset_signal ) UNTIL ( clock_signal_condition, ) ; -- 隐式表示 IF ( asynchronous_reset_condition ) THEN signal_n <= reset_value_n ; temp_n := reset_value_temp ; ELSIF ( clock_signal_condition ) THEN 其他处理语句； ELSE
其他处理语句； END IF ; .
.
END PROCESS yinshi ;
【例6-5】 单输入电平锁存器的VHDL模型的示例程序。
(P195)
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; ENTITY single_latch IS
PORT ( reset : IN STD_LOGIC ; datain : IN STD_LOGIC ; lock : IN STD_LOGIC ;
dataout : OUT STD_LOGIC ) ; END ENTITY single_latch ;
ARCHITECTURE rtl OF single_latch IS BEGIN
single_latch_inst : PROCESS ( reset, datain, lock ) BEGIN
IF ( reset = '1' ) THEN -- 复位信号 dataout <= '0' ;
ELSIF ( lock = '1' ) THEN -- 锁存信号 dataout <= datain ; END IF ;
END PROCESS single_latch_inst ; END ARCHITECTURE rtl ;
【例6-6】 多输入电平锁存器的VHDL模型的示例程序。
(P196)
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; ENTITY multi_latch IS
PORT ( reset : IN STD_LOGIC ;
datain1, datain2, datain3 : IN STD_LOGIC ; lock1, lock2, lock3 : IN STD_LOGIC ; dataout : OUT STD_LOGIC ) ; END ENTITY multi_latch ;
ARCHITECTURE behavioral OF multi_latch IS BEGIN
multi_latch_inst : PROCESS ( reset, datain1, datain2, datain3, lock1, lock2, lock3 ) BEGIN
IF ( reset = '1' ) THEN -- 复位信号 dataout <= '0' ;
ELSIF ( lock1 = '1' ) THEN -- 锁存信号 dataout <= datain1 ; ELSIF ( lock2 = '1' ) THEN dataout <= datain2 ; ELSIF ( lock3 = '1' ) THEN dataout <= datain3 ; END IF ;
END PROCESS multi_latch_inst ; END ARCHITECTURE behavioral ;
【例6-7】 同步锁存器的VHDL模型的示例程序。
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; ENTITY synch_latch IS
PORT ( reset, clk : IN STD_LOGIC ; datain : IN STD_LOGIC ; .
(P197)
.
lock : IN STD_LOGIC ;
dataout : OUT STD_LOGIC ) ; END ENTITY synch_latch ;
ARCHITECTURE behave OF synch_latch IS BEGIN
synch_latch_inst : PROCESS ( clk ) BEGIN
IF ( clk='1' AND clk'LAST_VALUE='0' AND clk'EVENT ) THEN -- 时钟上升沿 IF ( reset = '1' ) THEN -- 复位信号 dataout <= '0' ;
ELSIF ( lock = '1' ) THEN -- 锁存信号 dataout <= datain ; END IF ; END IF ;
END PROCESS synch_latch_inst ; END ARCHITECTURE behave ;
【例6-8】 异步锁存器的VHDL模型的示例程序。
(P197)
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; ENTITY asynch_latch IS
PORT ( reset, clk : IN STD_LOGIC ; datain : IN STD_LOGIC ; lock : IN STD_LOGIC ;
dataout : OUT STD_LOGIC ) ; END ENTITY asynch_latch ;
ARCHITECTURE behave OF asynch_latch IS BEGIN
asynch_latch_inst : PROCESS ( clk, reset, datain, lock ) BEGIN
IF ( reset = '1' ) THEN -- 复位信号 dataout <= '0' ;
ELSIF ( clk='1' AND clk'LAST_VALUE='0' AND clk'EVENT)THEN-- 时钟上升沿 IF ( lock = '1' ) THEN dataout <= datain ; END IF ; END IF ;
END PROCESS asynch_latch_inst ; END ARCHITECTURE behave ;
【例6-9】 基于兆函数LPM_LATCH模块生成的自定制的带有异步置位端和异步清零端的8位锁存器电路的VHDL示例程序。 (P199)
-- megafunction wizard : % LPM_LATCH % -- Megafunction Name (s) : lpm_latch LIBRARY ieee ;
USE ieee.std_logic_11.all ; LIBRARY lpm;
USE lpm.lpm_components.all ; ENTITY lpm_latch_inst IS PORT ( data : IN STD_LOGIC_VECTOR ( 7 DOWNTO 0 ) ; gate : IN STD_LOGIC ; aclr : IN STD_LOGIC ; aset : IN STD_LOGIC ; q : OUT STD_LOGIC_VECTOR ( 7 DOWNTO 0 ) ) ; END lpm_latch_inst ;
.
.
ARCHITECTURE SYN OF lpm_latch_inst IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR ( 7 DOWNTO 0 ) ; COMPONENT lpm_latch GENERIC ( lpm_width : NATURAL ; lpm_type : STRING ) ; PORT ( aclr : IN STD_LOGIC ; q : OUT STD_LOGIC_VECTOR ( 7 DOWNTO 0 ) ; data : IN STD_LOGIC_VECTOR ( 7 DOWNTO 0 ) ; gate : IN STD_LOGIC ; aset : IN STD_LOGIC ) ; END COMPONENT ; BEGIN q <= sub_wire0( 7 DOWNTO 0 ) ; lpm_latch_component : lpm_latch GENERIC MAP ( lpm_width => 8 , lpm_type => \"LPM_LATCH\" ) PORT MAP ( aclr => aclr , data => data , gate => gate , aset => aset , q => sub_wire0 ) ; END SYN ;
【例6-10】 上升沿触发的D触发器的示例程序。
(P201)
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; ENTITY cydff IS
PORT ( clk : IN STD_LOGIC ; datain : IN STD_LOGIC ;
dataout : OUT STD_LOGIC ) ; END ENTITY cydff ;
ARCHITECTURE behave OF cydff IS BEGIN
cydff_inst : PROCESS ( clk ) BEGIN
IF ( clk='1' AND clk'LAST_VALUE='0' AND clk'EVENT ) THEN -- 时钟上升沿 dataout <= datain ; END IF ;
END PROCESS cydff_inst ; END ARCHITECTURE behave ;
【例6-11】 异步复位的D触发器的示例程序。
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; ENTITY cydffa IS
PORT ( clk, clr : IN STD_LOGIC ; datain : IN STD_LOGIC ;
dataout : OUT STD_LOGIC ) ; END ENTITY cydffa ;
ARCHITECTURE behave OF cydffa IS BEGIN
cydffa_inst : PROCESS ( clk, clr ) BEGIN
(P201
.
.
IF ( clr = '1' ) THEN
dataout <= '0' ; -- 异步复位,清0
ELSIF ( clk='1' AND clk'LAST_VALUE='0' AND clk'EVENT)THEN -- 时钟上升沿 dataout <= datain ; END IF ;
END PROCESS cydffa_inst ; END ARCHITECTURE behave ;
【例6-12】 异步复位/置位的D触发器的示例程序。
(P202)
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; ENTITY cydffas IS
PORT ( clk, clr, pset : IN STD_LOGIC ; datain : IN STD_LOGIC ;
dataout : OUT STD_LOGIC ) ; END ENTITY cydffas ;
ARCHITECTURE behave OF cydffas IS BEGIN
cydffas_inst : PROCESS ( clk, clr, pset ) BEGIN
IF ( pset = '1' ) THEN
dataout <= '1' ; -- 异步置位,置1 ELSIF ( clr = '1' ) THEN
dataout <= '0' ; -- 异步复位,清0
ELSIF ( clk='1' AND clk'LAST_VALUE='0' AND clk'EVENT)THEN -- 时钟上升沿 dataout <= datain ; END IF ;
END PROCESS cydffas_inst ; END ARCHITECTURE behave ;
【例6-13】 同步复位的D触发器的示例程序。
(P203)
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; ENTITY cydff_synch IS
PORT ( clk, clr : IN STD_LOGIC ; datain : IN STD_LOGIC ;
dataout : OUT STD_LOGIC ) ; END ENTITY cydff_synch ;
ARCHITECTURE behave OF cydff_synch IS BEGIN
cydff_synch_inst : PROCESS ( clk ) BEGIN
IF ( clk='1' AND clk'LAST_VALUE='0' AND clk'EVENT ) THEN -- 时钟上升沿 IF ( clr = '1' ) THEN dataout <= '0' ; ELSE
dataout <= datain ; END IF ; END IF ;
END PROCESS cydff_synch_inst ; END ARCHITECTURE behave ;
【例6-14】 基于兆函数LPM_DFF模块生成的自定制的带有异步置位端（aset）和异步
.
.
清零端（aclr）的16位D触发器电路的VHDL示例程序。
(P204)
-- megafunction wizard : % LPM_FF % -- Megafunction Name (s) : lpm_ff LIBRARY ieee ;
USE ieee.std_logic_11.all ; LIBRARY lpm;
USE lpm.lpm_components.all ; ENTITY lpm_dff_inst IS PORT ( clock : IN STD_LOGIC ; enable : IN STD_LOGIC ; aclr : IN STD_LOGIC ; aset : IN STD_LOGIC ; data : IN STD_LOGIC_VECTOR ( 15 DOWNTO 0 ); q : OUT STD_LOGIC_VECTOR ( 15 DOWNTO 0 ) ) ; END lpm_dff_inst ;
ARCHITECTURE SYN OF lpm_dff_inst IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR ( 15 DOWNTO 0 ) ; COMPONENT lpm_ff
GENERIC ( lpm_width : NATURAL ; lpm_type : STRING ; lpm_fftype : STRING ) ; PORT ( enable : IN STD_LOGIC ; aclr : IN STD_LOGIC ; clock : IN STD_LOGIC ; q : OUT STD_LOGIC_VECTOR ( 15 DOWNTO 0 ) ; data : IN STD_LOGIC_VECTOR ( 15 DOWNTO 0 ) ; aset : IN STD_LOGIC ) ; END COMPONENT ; BEGIN q <= sub_wire0 ( 15 DOWNTO 0 ) ; lpm_ff_component : lpm_ff GENERIC MAP ( lpm_width => 16 , lpm_type => \"LPM_FF\" , lpm_fftype => \"DFF\" ) PORT MAP ( enable => enable , aclr => aclr , clock => clock , data => data , aset => aset , q => sub_wire0 ) ; END ARCHITECTURE SYN ;
【例6-15】 下降沿触发的T触发器的示例程序。
(P206)
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; ENTITY cytff IS
PORT ( clk : IN STD_LOGIC ; t : IN STD_LOGIC ; q : OUT STD_LOGIC ) ; END ENTITY cytff ;
ARCHITECTURE behave OF cytff IS BEGIN
cytff_inst : PROCESS ( clk ) BEGIN
IF ( clk='0' AND clk'EVENT ) THEN -- 时钟下降沿 .
.
IF ( t = '1' ) THEN q <= NOT q ; ELSE
q <= q ; END IF ; END IF ;
END PROCESS cytff_inst ; END ARCHITECTURE behave ;
【例6-16】 基于兆函数LPM_TFF模块生成的自定制的带有同步置位端（sset）、同步清零端（sclr）和同步加载端（sload）的24位T触发器电路的VHDL示例程序。 (P208)
-- megafunction wizard : % LPM_FF % -- Megafunction Name (s) : lpm_ff LIBRARY ieee ;
USE ieee.std_logic_11.all ; LIBRARY lpm;
USE lpm.lpm_components.all ; ENTITY lpm_tff_inst IS PORT ( clock : IN STD_LOGIC ; enable : IN STD_LOGIC ; sclr : IN STD_LOGIC ; sload : IN STD_LOGIC ; sset : IN STD_LOGIC ; data : IN STD_LOGIC_VECTOR ( 23 DOWNTO 0 ) ; q : OUT STD_LOGIC_VECTOR ( 23 DOWNTO 0 ) ) ; END lpm_tff_inst ;
ARCHITECTURE SYN OF lpm_tff_inst IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR ( 23 DOWNTO 0 ) ; COMPONENT lpm_ff GENERIC ( lpm_width : NATURAL ; lpm_type : STRING ; lpm_fftype : STRING ) ; PORT ( sload : IN STD_LOGIC ; enable : IN STD_LOGIC ; sclr : IN STD_LOGIC ; clock : IN STD_LOGIC ; q : OUT STD_LOGIC_VECTOR ( 23 DOWNTO 0 ) ; data : IN STD_LOGIC_VECTOR ( 23 DOWNTO 0 ) ; sset : IN STD_LOGIC ) ; END COMPONENT ; BEGIN q <= sub_wire0 ( 23 DOWNTO 0 ) ; lpm_ff_component : lpm_ff GENERIC MAP ( lpm_width => 24 , lpm_type => \"LPM_FF\" , lpm_fftype => \"TFF\" ) PORT MAP ( sload => sload , enable => enable , sclr => sclr , clock => clock , data => data , sset => sset , q => sub_wire0 ) ; END SYN ;
【例6-17】 带有异步置位/复位端的上升沿触发的JK触发器的示例程序。 (P210)
LIBRARY IEEE ; .
.
USE IEEE.STD_LOGIC_11.ALL ; ENTITY cyjkff IS
PORT ( aset, aclr, clk : IN STD_LOGIC ; j, k : IN STD_LOGIC ;
q, qb : OUT STD_LOGIC ) ; END ENTITY cyjkff ;
ARCHITECTURE behave OF cyjkff IS
SIGNAL q_temp, qb_temp : STD_LOGIC ; BEGIN
cyjkff_inst : PROCESS ( aset, aclr, clk, j, k ) BEGIN
q <= q_temp ; qb <= qb_temp ;
IF ( aset = '1' AND aclr = '0' ) THEN -- 置位信号aset高电平有效 q_temp <= '1' ; -- JK触发器置位 qb_temp <= '0' ;
ELSIF ( aset = '0' AND aclr = '1' ) THEN -- 复位信号aclr高电平有效 q_temp <= '0' ; -- JK触发器复位 qb_temp <= '1' ;
ELSIF ( clk='1' AND clk'EVENT ) THEN -- 时钟上升沿到来 IF ( j = '0' AND k = '1' ) THEN q_temp <= '0' ; qb_temp <= '1' ;
ELSIF ( j = '1' AND k = '0' ) THEN q_temp <= '1' ; qb_temp <= '0' ;
ELSIF ( j = '1' AND k = '1' ) THEN -- JK触发器输出翻转 q_temp <= NOT q ; qb_temp <= NOT qb ; ELSE
q_temp <= q ; qb_temp <= qb ; END IF ; END IF ;
END PROCESS cyjkff_inst ; END ARCHITECTURE behave ;
【例6-18】 用VHDL语言描述的10位通用寄存器的示例程序。
(P211)
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; ENTITY cyregister IS
PORT ( clk : IN STD_LOGIC ;
datain : IN STD_LOGIC_VECTOR ( 9 DOWNTO 0 ) ;
dataout : OUT STD_LOGIC_VECTOR ( 9 DOWNTO 0 ) ) ; END ENTITY cyregister ;
ARCHITECTURE behave OF cyregister IS BEGIN
cyregister_inst : PROCESS ( clk ) BEGIN
IF ( clk='1' AND clk'LAST_VALUE='0' AND clk'EVENT ) THEN dataout <= datain ; END IF ;
END PROCESS cyregister_inst ; END ARCHITECTURE behave ;
.
.
【例6-19】 用VHDL语言描述的8位串入-串出移位寄存器的示例程序。
(P212)
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; ENTITY shift8 IS PORT ( shiftin : IN STD_LOGIC ; clk : IN STD_LOGIC ; shiftout : OUT STD_LOGIC ) ; END shift8 ;
ARCHITECTURE rtl OF shift8 IS COMPONENT dff PORT ( d, clk : IN STD_LOGIC ; q : OUT STD_LOGIC ) ; END COMPONENT ; SIGNAL data : STD_LOGIC_VECTOR ( 8 DOWNTO 0 ) ; BEGIN data ( 0 ) <= shiftin ; generate_inst : FOR i IN 0 TO 7 GENERATE dffn_x : dff PORT MAP ( data ( i ), clk, data ( i+1 ) ) ; END GENERATE ;
shiftout <= data ( 8 ) ; END rtl ;
【例6-20】 直接采用信号代入的方法实现串入-串出移位寄存器的示例程序。 (P213)
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; ENTITY shift8 IS PORT ( shiftin : IN STD_LOGIC ; clk : IN STD_LOGIC ; shiftout : OUT STD_LOGIC ) ; END ENTITY shift8 ;
ARCHITECTURE behavioral OF shift8 IS
SIGNAL data : STD_LOGIC_VECTOR ( 8 DOWNTO 0 ) ; BEGIN
PROCESS ( clk ) BEGIN
IF ( clk='1' AND clk'LAST_VALUE='0' AND clk'EVENT ) THEN -- 时钟上升沿 data ( 1 ) <= shiftin ; data ( 2 ) <= data ( 1 ) ; data ( 3 ) <= data ( 2 ) ; data ( 4 ) <= data ( 3 ) ; data ( 5 ) <= data ( 4 ) ; data ( 6 ) <= data ( 5 ) ; data ( 7 ) <= data ( 6 ) ; data ( 8 ) <= data ( 7 ) ; shiftout <= data ( 8 ) ; END IF ;
END PROCESS ;
END ARCHITECTURE behavioral ;
【例6-21】 用VHDL语言描述的8位串入-并出移位寄存器的示例程序。
.
(P215)
.
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; ENTITY s_p_shift8 IS
PORT ( shiftin : IN STD_LOGIC ; clk_pulse : IN STD_LOGIC ; Q : OUT STD_LOGIC_VECTOR ( 7 DOWNTO 0 ) shiftout : OUT STD_LOGIC ) ; END ENTITY s_p_shift8 ;
ARCHITECTURE dataflow OF s_p_shift8 IS COMPONENT dff PORT ( d, clk : IN STD_LOGIC ; q : OUT STD_LOGIC ) ; END COMPONENT ; SIGNAL data_temp : STD_LOGIC_VECTOR ( 8 DOWNTO 0 ) ; BEGIN data_temp ( 0 ) <= shiftin ; generate_inst : FOR i IN 0 TO 7 GENERATE dffn_x : dff PORT MAP ( data_temp ( i ), clk_pulse, Q ( i ) ) ; END GENERATE ;
shiftout <= data (8) ; END ARCHITECTURE dataflow ;
【例6-22】 用VHDL语言描述如图6-15所示的8位循环左移位寄存器的示例程序。
(P217)
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; USE IEEE.STD_LOGIC_ARITH.ALL ; USE IEEE.STD_LOGIC_UNSIGNED.ALL ; ENTITY circle_left_shift8 IS
PORT ( D : IN STD_LOGIC_VECTOR ( 7 DOWNTO 0 ) ; s : IN STD_LOGIC_VECTOR ( 2 DOWNTO 0 ) ; clk, load : IN STD_LOGIC ;
Q : OUT STD_LOGIC_VECTOR ( 7 DOWNTO 0 ) ) ; END ENTITY circle_left_shift8 ;
ARCHITECTURE rtl OF circle_left_shift8 IS
SIGNAL temp : STD_LOGIC_VECTOR ( 7 DOWNTO 0 ) ; BEGIN
Q <= temp ;
circle_shift8_inst : PROCESS ( clk )
VARIABLE num : INTEGER RANGE 0 TO 7 ; BEGIN
num := CONV_INTEGER ( s ) ;
IF ( clk ='1' AND clk'LAST_VALUE='0' AND clk'EVENT ) THEN IF ( load = '0' ) THEN
temp <= D ; -- 直接加载输入数据,不进行循环左移位操作 ELSE
CASE num IS
-- 保持原值,不循环左移
WHEN 0 => FOR i IN 7 DOWNTO 0 LOOP
temp ( i ) <= temp ( i – 0 ) ; END LOOP ; -- 循环左移1位
WHEN 1 => FOR i IN 7 DOWNTO 1 LOOP
temp ( i ) <= temp ( i – 1 ) ; END LOOP ;
temp ( 0 ) <= temp ( 7 ) ; -- 循环左移2位 .
.
WHEN 2 => FOR i IN 7 DOWNTO 2 LOOP
temp ( i ) <= temp ( i – 2 ) ; END LOOP ;
FOR i IN 1 DOWNTO 0 LOOP
temp ( i ) <= temp ( i + 6 ) ; END LOOP ; -- 循环左移3位
WHEN 3 => FOR i IN 7 DOWNTO 3 LOOP
temp ( i ) <= temp ( i – 3 ) ; END LOOP ;
FOR i IN 2 DOWNTO 0 LOOP
temp ( i ) <= temp ( i + 5 ) ; END LOOP ; -- 循环左移4位
WHEN 4 => FOR i IN 7 DOWNTO 4 LOOP
temp ( i ) <= temp ( i – 4 ) ; END LOOP ;
FOR i IN 3 DOWNTO 0 LOOP
temp ( i ) <= temp ( i + 4 ) ; END LOOP ; -- 循环左移5位
WHEN 5 => FOR i IN 7 DOWNTO 5 LOOP
temp ( i ) <= temp ( i – 5 ) ; END LOOP ;
FOR i IN 4 DOWNTO 0 LOOP
temp ( i ) <= temp ( i + 3 ) ; END LOOP ; -- 循环左移6位
WHEN 6 => FOR i IN 7 DOWNTO 6 LOOP
temp ( i ) <= temp ( i – 6 ) ; END LOOP ;
FOR i IN 5 DOWNTO 0 LOOP
temp ( i ) <= temp ( i + 2 ) ; END LOOP ; -- 循环左移7位
WHEN 7 => temp ( 7 ) <= temp ( 0 ) ; FOR i IN 6 DOWNTO 0 LOOP
temp ( i ) <= temp ( i + 1 ) ; END LOOP ;
WHEN OTHERS => FOR i IN 7 DOWNTO 0 LOOP
temp ( i ) <= temp ( i – 0 ) ; END LOOP ; END CASE ; END IF ; END IF ;
END PROCESS circle_shift8_inst ; END ARCHITECTURE rtl ;
【例6-23】 调用包集合CYPAC中的循环左移过程的8位循环左移位寄存器示例程序。
(P218)
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; USE IEEE.STD_LOGIC_ARITH.ALL ; USE IEEE.STD_LOGIC_UNSIGNED.ALL ; PACKAGE CYPAC IS
PROCEDURE shift_left ( din, select : IN STD_LOGIC_VECTOR ; SIGNAL dout : OUT STD_LOGIC_VECTOR ) ; END CYPAC ; .
.
PACKAGE BODY CYPAC IS
PROCEDURE shift_left ( din, select : IN STD_LOGIC_VECTOR ; SIGNAL dout : OUT STD_LOGIC_VECTOR ) IS VARIABLE sc : INTEGER ; BEGIN
sc := CONV_INTEGER ( select ) ; FOR i IN din'RANGE LOOP
IF ( ( i + sc ) <= din'LEFT ) THEN dout ( i + sc ) <= din ( i ) ; ELSE
dout ( i + sc – din'LEFT ) <= din ( i ) ; END IF ; END LOOP ; END shift_left ; END CYPAC ;
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; USE WORK.CYPAC.ALL ;
ENTITY circle_left_shift8 IS
PORT ( datain : IN STD_LOGIC_VECTOR ( 7 DOWNTO 0 ) ; sel : IN STD_LOGIC_VECTOR ( 2 DOWNTO 0 ) ; clk_pulse, enb : IN STD_LOGIC ;
dataout : OUT STD_LOGIC_VECTOR ( 7 DOWNTO 0 ) ) ; END ENTITY circle_left_shift8 ;
ARCHITECTURE dataflow OF circle_left_shift8 IS BEGIN
circle_shift8_inst : PROCESS ( clk_pulse ) BEGIN
IF ( clk_pulse ='1' AND clk_pulse'LAST_VALUE='0' AND clk_pulse'EVENT ) THEN
IF ( enb = '0' ) THEN
dataout <= datain ; -- 直接加载输入数据,不进行移位操作 ELSE
shift_left ( datain, sel, dataout ) ; -- 此处调用过程,进行循环左移操作 END IF ; END IF ;
END PROCESS circle_shift8_inst ; END ARCHITECTURE dataflow ;
【例6-24】 用VHDL语言描述的8位双向移位寄存器的示例程序。
(P221)
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; USE IEEE.STD_LOGIC_ARITH.ALL ; USE IEEE.STD_LOGIC_UNSIGNED.ALL ; ENTITY double_dir_shifter8 IS
PORT ( D : IN STD_LOGIC_VECTOR ( 7 DOWNTO 0 ) ; clk, clr, load, dir, sl, sr : IN STD_LOGIC ; Q : OUT STD_LOGIC_VECTOR ( 7 DOWNTO 0 ) ) ; END ENTITY double_dir_shifter8 ;
ARCHITECTURE dataflow OF double_dir_shifter8 IS SIGNAL temp : STD_LOGIC_VECTOR ( 7 DOWNTO 0 ) ; BEGIN
Q <= temp ;
double_dir_shifter8_inst : PROCESS ( clk, clr ) BEGIN
IF ( clr = '0' ) THEN temp <= \"00000000\" ;
ELSIF ( clk ='1' AND clk'LAST_VALUE='0' AND clk'EVENT ) THEN .
.
IF ( load = '0' ) THEN
temp <= D ; -- 直接加载输入数据
ELSIF ( load = '1' AND dir = '0' ) THEN -- 进行左移操作 FOR i IN 7 DOWNTO 1 LOOP
temp ( i ) <= temp ( i - 1 ) ; END LOOP ;
temp ( 0 ) <= sl ; -- 左移后,空缺位补充sl
ELSIF ( load = '1' AND dir = '1' ) THEN -- 进行右移操作 FOR i IN 0 TO 6 LOOP
temp ( i ) <= temp ( i + 1 ) ; END LOOP ;
temp ( 7 ) <= sr ; -- 右移后,空缺位补充sr END IF ; END IF ;
END PROCESS double_dir_shifter8_inst ; END ARCHITECTURE dataflow ;
【例6-25】 用VHDL语言描述的8位串/并入-串出移位寄存器74166的示例程序。
(223)
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; USE IEEE.STD_LOGIC_ARITH.ALL ; USE IEEE.STD_LOGIC_UNSIGNED.ALL ; ENTITY shifter_74LS166 IS
PORT ( A, B, C, D, E, F, G, H : IN STD_LOGIC ; SER : IN STD_LOGIC ; CLRN, CLK, CLKIH, STLD : IN STD_LOGIC ; QH : OUT STD_LOGIC ) ;
END ENTITY shifter_74LS166 ;
ARCHITECTURE dataflow OF shifter_74LS166 IS
SIGNAL temp : STD_LOGIC_VECTOR ( 7 DOWNTO 0 ) ; BEGIN
QH <= temp ( 7 ) ;
shifter_74LS166_inst : PROCESS ( CLRN, CLK, CLKIH, STLD, SER ) BEGIN
IF ( CLRN = '0' ) THEN -- 器件复位,输出端清0 temp <= \"00000000\" ; ELSIF ( CLKIH = '1' ) THEN
NULL ; -- temp <= temp ; 即输出保持不变
ELSIF (CLK = '1' AND CLK'LAST_VALUE='0' AND CLK'EVENT ) THEN IF ( STLD = '0' ) THEN
temp ( 0 ) <= A ; -- 并行加载8位输入数据 temp ( 1 ) <= B ; temp ( 2 ) <= C ; temp ( 3 ) <= D ; temp ( 4 ) <= E ; temp ( 5 ) <= F ; temp ( 6 ) <= G ; temp ( 7 ) <= H ;
ELSIF ( STLD = '1' ) THEN -- 进行串行输入右移操作 FOR i IN temp'LOW TO ( temp'HIGH – 1 ) LOOP temp ( i ) <= temp ( i + 1 ) ; END LOOP ;
temp ( 7 ) <= SER ; -- 右移后,空缺位补充SER END IF ; END IF ;
END PROCESS shifter_74LS166_inst ; END ARCHITECTURE dataflow ;
.
.
【例6-26】 用VHDL语言描述的带使能端的十二进制计数器的示例程序。
(P226)
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; USE IEEE.STD_LOGIC_ARITH.ALL ; USE IEEE.STD_LOGIC_UNSIGNED.ALL ; ENTITY cnten_counter12 IS
PORT ( clr, clk, cnt_en : IN STD_LOGIC ; qa, qb, qc, qd : OUT STD_LOGIC ) ; END ENTITY cnten_counter12 ;
ARCHITECTURE rtl OF cnten_counter12 IS
SIGNAL temp : STD_LOGIC_VECTOR ( 3 DOWNTO 0 ) ; BEGIN
qd <= temp ( 3 ) ; -- 4个输出数据信号 qc <= temp ( 2 ) ; qb <= temp ( 1 ) ; qa <= temp ( 0 ) ;
cnten_counter12_inst : PROCESS ( clr, clk ) BEGIN
IF ( clr = '1' ) THEN -- 器件复位,输出端清0 temp <= \"0000\" ;
ELSIF ( clk = '1' AND clk'LAST_VALUE='0' AND clk'EVENT ) THEN IF ( cnt_en = '1' ) THEN -- 计数使能信号有效
IF ( temp = \"1011\" ) THEN -- 当temp是11时,已经计到最大了 temp <= \"0000\" ; ELSE
temp <= temp + '1' ; -- 递增计数 END IF ; END IF ; END IF ;
END PROCESS cnten_counter12_inst ; END ARCHITECTURE rtl ;
【例6-27】 利用两个4位二进制计数器构成一个六十进制计数器的示例程序。 (P227)
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; USE IEEE.STD_LOGIC_ARITH.ALL ; USE IEEE.STD_LOGIC_UNSIGNED.ALL ; ENTITY bcd2_counter60 IS
PORT ( clk, bcd1wr, bcd10wr, cin : IN STD_LOGIC ;
datain : IN STD_LOGIC_VECTOR ( 3 DOWNTO 0 ) ; bcd1out : OUT STD_LOGIC_VECTOR ( 3 DOWNTO 0 ) ; bcd10out : OUT STD_LOGIC_VECTOR ( 2 DOWNTO 0 ) ; co : OUT STD_LOGIC ) ; END ENTITY bcd2_counter60 ; -- 六十进制计数器的结构体
ARCHITECTURE rtl OF bcd2_counter60 IS
SIGNAL temp_bcd1 : STD_LOGIC_VECTOR ( 3 DOWNTO 0 ) ; SIGNAL temp_bcd10 : STD_LOGIC_VECTOR ( 2 DOWNTO 0 ) ; BEGIN
bcd1out <= temp_bcd1 ; -- 六十进制计数器的个位数输出 bcd10out <= temp_bcd10 ; -- 六十进制计数器的十位数输出 -- 处理六十进制计数器的个位数计数的进程
bcd2_counter60_1inst : PROCESS ( bcd1wr, clk ) BEGIN
.
.
IF ( bcd1wr = '1' ) THEN -- 此时个位数置位有效 temp_bcd1 <= datain ;
ELSIF ( clk = '1' AND clk'LAST_VALUE='0' AND clk'EVENT ) THEN IF ( cin = '1' ) THEN -- 输入进位位有效
IF ( temp_bcd1 = \"1001\" ) THEN -- 个位数的十进制计数 temp_bcd1 <= \"0000\" ; ELSE
temp_bcd1 <= temp_bcd1 + '1' ; -- 递增计数 END IF ; END IF ; END IF ;
END PROCESS bcd2_counter60_1inst ; -- 处理六十进制计数器的十位数计数的进程
bcd2_counter60_10inst : PROCESS ( bcd10wr, clk ) BEGIN
IF ( bcd10wr = '1' ) THEN -- 此时十位数置位有效 temp_bcd10 <= datain ( 2 DOWNTO 0 ) ;
ELSIF ( clk = '1' AND clk'LAST_VALUE='0' AND clk'EVENT ) THEN IF ( cin = '1' AND temp_bcd1 = \"1001\" ) THEN -- 输入进位位有效 IF ( temp_bcd10 = \"101\" ) THEN -- 十位数的十进制计数 temp_bcd10 <= \"000\" ; ELSE
temp_bcd10 <= temp_bcd10 + '1' ; -- 递增计数 END IF ; END IF ; END IF ;
END PROCESS bcd2_counter60_10inst ; -- 处理六十进制计数器的输出进位位的进程
bcd2_counter60_carry : PROCESS ( temp_bcd1, temp_bcd10, cin ) BEGIN
IF ( cin = '1' AND temp_bcd1 = \"1001\" AND temp_bcd10 = \"101\" ) THEN co <= '1' ; ELSE
co <= '0' ; END IF ;
END PROCESS bcd2_counter60_carry ; END ARCHITECTURE rtl ;
【例6-28】 用VHDL语言描述的8位二进制加/减计数器的示例程序。
(P229)
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ;
USE IEEE.STD_LOGIC_UNSIGNED.ALL ; ENTITY updown_counter8 IS
PORT ( clk, clr, updown : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR ( 7 DOWNTO 0 ) ) ; END ENTITY updown_counter8 ;
ARCHITECTURE rtl OF updown_counter8 IS
SIGNAL temp_count : STD_LOGIC_VECTOR ( 7 DOWNTO 0 ) ; BEGIN
q <= temp_count ;
updown_counter8_inst : PROCESS ( clr, clk ) BEGIN
IF ( clr = '1' ) THEN -- 对加/减计数器复位 temp_count <= \"00000000\" ;
ELSIF ( clk = '1' AND clk'LAST_VALUE='0' AND clk'EVENT ) THEN IF ( updown = '1' ) THEN
temp_count <= temp_count + '1' ; -- 加计数 .
.
ELSE
temp_count <= temp_count － '1' ; -- 减计数 END IF ; END IF ;
END PROCESS updown_counter8_inst ; END ARCHITECTURE rtl ;
【例6-29】 用VHDL语言描述的4位行波型异步计数器电路的示例程序。 (P230)
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; ENTITY cydffb IS
PORT ( clk, clr, d : IN STD_LOGIC ; q, qb : OUT STD_LOGIC ) ; END ENTITY cydffb ;
ARCHITECTURE rtl OF cydffb IS SIGNAL temp_q : STD_LOGIC ; BEGIN
q <= temp_q ;
qb <= NOT temp_q ; PROCESS ( clr, clk ) BEGIN
IF ( clr = '0' ) THEN -- 复位 temp_q <= '0' ;
ELSIF ( clk = '1' AND clk'LAST_VALUE='0' AND clk'EVENT ) THEN temp_q <= d ; END IF ; END PROCESS ;
END ARCHITECTURE rtl ;
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; ENTITY ripple_counter4 IS
PORT ( clk, clr : IN STD_LOGIC ;
out_counter : OUT STD_LOGIC_VECTOR ( 3 DOWNTO 0 ) ) ; END ENTITY ripple_counter4 ;
ARCHITECTURE rtl OF ripple_counter4 IS COMPONENT cydffb
PORT ( clk, clr, d : IN STD_LOGIC ; q, qb : OUT STD_LOGIC ) ; END COMPONENT ;
SIGNAL temp : STD_LOGIC_VECTOR ( 4 DOWNTO 0 ) ; BEGIN
temp ( 0 ) <= clk ;
counter4gen : FOR i IN 0 TO 3 GENERATE
counter4_x : cydffb PORT MAP ( clk => temp ( i ) , clr => clr ,
d => temp ( i + 1 ) , q => out_counter ( i ) , qb => temp ( i + 1 ) ) ; END GENERATE counter4gen ; END ARCHITECTURE rtl ;
【例6-30】 基于兆函数LPM_COUNTER模块生成的自定制的带有时钟使能端（clk_en）、计数使能端（cnt_en）、异步置位端（aset）、异步加载端（aload）和异步清零端（aclr）的12位模30加/减（updown）计数器电路的VHDL示例程序。 (P232)
.
.
-- megafunction wizard : % LPM_COUNTER % -- Megafunction Name (s) : lpm_counter LIBRARY ieee ;
USE ieee.std_logic_11.all ; LIBRARY lpm;
USE lpm.lpm_components.all ; ENTITY lpm_counter_inst IS PORT ( clock : IN STD_LOGIC ; updown : IN STD_LOGIC ; clk_en : IN STD_LOGIC ; cnt_en : IN STD_LOGIC ; aclr : IN STD_LOGIC ; aload : IN STD_LOGIC ; aset : IN STD_LOGIC ; data : IN STD_LOGIC_VECTOR ( 11 DOWNTO 0 ) ; q : OUT STD_LOGIC_VECTOR ( 11 DOWNTO 0 ) ) ; END ENTITY lpm_counter_inst ;
ARCHITECTURE SYN OF lpm_counter_inst IS SIGNAL sub_wire0 : STD_LOGIC_VECTOR ( 11 DOWNTO 0 ) ; COMPONENT lpm_counter GENERIC ( lpm_width : NATURAL ; lpm_type : STRING ; lpm_direction : STRING ; lpm_modulus : NATURAL ) ; PORT ( aload : IN STD_LOGIC ; clk_en : IN STD_LOGIC ; aclr : IN STD_LOGIC ; clock : IN STD_LOGIC ; q : OUT STD_LOGIC_VECTOR (11 DOWNTO 0); data : IN STD_LOGIC_VECTOR (11 DOWNTO 0); updown : IN STD_LOGIC ; aset : IN STD_LOGIC ; cnt_en : IN STD_LOGIC ) ; END COMPONENT ; BEGIN q <= sub_wire0 ( 11 DOWNTO 0 ) ; lpm_counter_component : lpm_counter GENERIC MAP ( lpm_width => 12 , lpm_type => \"LPM_COUNTER\" , lpm_direction => \"UNUSED\" , lpm_modulus => 30 ) PORT MAP ( aload => aload , clk_en => clk_en , aclr => aclr , clock => clock , data => data , updown => updown , aset => aset , cnt_en => cnt_en , q => sub_wire0 ) ; END ARCHITECTURE SYN ;
【例7-1】 交通灯控制系统的VHDL有限状态机实现。
LIBRARY IEEE;
USE IEEE.STD_LOGIC_11.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; .
（P241）
.
ENTITY traffic_ctrl IS
PORT(reset,clk:IN STD_LOGIC; sensor: IN STD_LOGIC;
light1_red: OUT STD_LOGIC; light1_yellow: OUT STD_LOGIC; light1_green: OUT STD_LOGIC; light2_red: OUT STD_LOGIC; light2_yellow: OUT STD_LOGIC; light2_green: OUT STD_LOGIC); END ENTITY traffic_ctrl;
ARCHITECTURE mysta OF traffic_ctrl IS
TYPE states IS (st0,st1,st2); SIGNAL current_state : states; SIGNAL next_state : states;
SIGNAL cout0,cout1,cout2:STD_LOGIC;
SIGNAL m1: STD_LOGIC_VECTOR(1 DOWNTO 0):=\"00\"; SIGNAL m2: STD_LOGIC_VECTOR(1 DOWNTO 0):=\"00\"; SIGNAL m3: STD_LOGIC_VECTOR(1 DOWNTO 0):=\"00\";
BEGIN
PROCESS(current_state) BEGIN
CASE current_state IS WHEN st0 =>
IF reset='1' THEN
next_state<=st0;
ELSIF sensor ='1' AND cout0='1' THEN next_state<=st1; ELSE next_state<=st0; END IF; WHEN st1 =>
IF reset='1' THEN
next_state<=st0; ELSIF cout1='1' THEN IF sensor='1' THEN next_state<=st2;
ELSE next_state<=st0; END IF; ELSE
next_state<=st1; END IF;
WHEN st2 =>
IF reset='1' THEN
next_state<=st0; ELSIF sensor ='0' THEN
next_state<=st1;
ELSIF sensor ='1' AND cout2='1' THEN next_state<=st0; ELSE
next_statE<=st2; END IF;
WHEN OTHERS => next_state<=st0;
END CASE; END PROCESS; .
.
PROCESS (clk) BEGIN
IF clk'event AND clk='1' THEN current_state<= next_state; END IF; END PROCESS;
PROCESS (current_state) BEGIN
CASE current_state IS WHEN st0=>
light1_red<='0';light1_yellow<='0';light1_green<='1';
light2_red<='1';light2_yellow<='0';light2_green<='0';
WHEN st1=>
light1_red<='0';light1_yellow<='1';light1_green<='0';
light2_red<='0';light2_yellow<='1';light2_green<='0';
WHEN st2=>
light1_red<='1';light1_yellow<='0';light1_green<='0';
light2_red<='0';light2_yellow<='0';light2_green<='1';
WHEN OTHERS =>
light1_red<='0';light1_yellow<='0';light1_green<='1';
light2_red<='1';light2_yellow<='0';light2_green<='0';
END CASE; END PROCESS;
PROCESS(clk) BEGIN
IF clk'EVENT AND clk='1' THEN IF current_state=st0 THEN IF m1 =\"11\" THEN m1<=\"00\"; ELSE m1<=m1+1;
END IF; END IF; END IF;
cout0<=m1(1) AND m1(0); END PROCESS;
PROCESS(clk) BEGIN
IF clk'EVENT AND clk='1' THEN
IF current_state=st2 THEN IF m2 =\"11\" THEN m2<=\"00\"; ELSE m2<=m2+1; END IF; END IF; .
.
END IF;
cout2<=m2(1) AND m2(0); END PROCESS;
PROCESS(clk)
BEGIN
IF clk'EVENT AND clk='1' THEN IF current_state=st1 THEN IF m3 =\"01\" THEN m3<=\"00\"; ELSE m3<=m3+1; END IF; END IF; END IF;
cout1<=m3(0); END PROCESS; END ARCHITECTURE mysta;
【例7-2】 交通灯控制器采用单进程描述的有限状态机实现。
(P243)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_11.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY traffic_ctrl IS
PORT(reset,clk:IN STD_LOGIC; sensor: IN STD_LOGIC;
light1_red: OUT STD_LOGIC; light1_yellow: OUT STD_LOGIC; light1_green: OUT STD_LOGIC; light2_red: OUT STD_LOGIC; light2_yellow: OUT STD_LOGIC; light2_green: OUT STD_LOGIC); END ENTITY traffic_ctrl;
ARCHITECTURE mysta OF traffic_ctrl IS
TYPE states IS (st0,st1,st2); SIGNAL current_state : states;
SIGNAL cout0,cout1,cout2:STD_LOGIC;
SIGNAL m1: STD_LOGIC_VECTOR(1 DOWNTO 0):=\"00\"; SIGNAL m2: STD_LOGIC_VECTOR(1 DOWNTO 0):=\"00\"; SIGNAL m3: STD_LOGIC_VECTOR(1 DOWNTO 0):=\"00\";
BEGIN
PROCESS(clk) BEGIN
IF clk'EVENT AND clk='1' THEN CASE current_state IS WHEN st0 =>
IF reset='1' THEN
current_state<=st0;
light1_red<='0';light1_yellow<='0';light1_green<='1';
light2_red<='1';light2_yellow<='0';light2_green<='0';
ELSIF sensor ='1' AND cout0='1' THEN current_state<=st1;
light1_red<='0';light1_yellow<='1';light1_green<='0';
.
.
light2_red<='0';light2_yellow<='1';light2_green<='0'; ELSE current_state<=st0;
light1_red<='0';light1_yellow<='0';light1_green<='1'; light2_red<='1';light2_yellow<='0';light2_green<='0'; END IF; WHEN st1 =>
IF reset='1' THEN
current_state<=st0;
light1_red<='0';light1_yellow<='0';light1_green<='1'; light2_red<='1';light2_yellow<='0';light2_green<='0'; ELSIF cout1='1' THEN IF sensor='1' THEN current_state<=st2;
light1_red<='1';light1_yellow<='0';light1_green<='0'; light2_red<='0';light2_yellow<='0';light2_green<='1'; ELSE current_state<=st0;
light1_red<='0';light1_yellow<='0';light1_green<='1';
light2_red<='1';light2_yellow<='0';light2_green<='0'; END IF; ELSE
current_state<=st1;
light1_red<='0';light1_yellow<='1';light1_green<='0'; light2_red<='0';light2_yellow<='1';light2_green<='0'; END IF;
WHEN st2 =>
IF reset='1' THEN
current_state<=st0;
light1_red<='0';light1_yellow<='0';light1_green<='1'; light2_red<='1';light2_yellow<='0';light2_green<='0'; ELSIF sensor ='0' THEN current_state<=st1;
light1_red<='0';light1_yellow<='1';light1_green<='0';
light2_red<='0';light2_yellow<='1';light2_green<='0'; ELSIF sensor ='1' AND cout2='1' THEN current_state<=st0;
light1_red<='0';light1_yellow<='0';light1_green<='1'; light2_red<='1';light2_yellow<='0';light2_green<='0'; ELSE
current_state<=st2;
light1_red<='1';light1_yellow<='0';light1_green<='0'; light2_red<='0';light2_yellow<='0';light2_green<='1'; END IF;
WHEN OTHERS => current_state<=st0;
light1_red<='0';light1_yellow<='0';light1_green<='1'; light2_red<='1';light2_yellow<='0';light2_green<='0'; END CASE; END IF;
END PROCESS;
PROCESS(clk) BEGIN
IF clk'EVENT AND clk='1' THEN IF current_state=st0 THEN IF m1 =\"11\" THEN m1<=\"00\"; ELSE m1<=m1+1;
END IF; .
.
END IF; END IF;
cout0<=m1(1) AND m1(0); END PROCESS; PROCESS(clk) BEGIN
IF clk'EVENT AND clk='1' THEN
IF current_state=st2 THEN IF m2 =\"11\" THEN m2<=\"00\"; ELSE m2<=m2+1; END IF; END IF; END IF;
cout2<=m2(1) AND m2(0); END PROCESS;
PROCESS(clk)
BEGIN
IF clk'EVENT AND clk='1' THEN IF current_state=st1 THEN IF m3 =\"01\" THEN m3<=\"00\"; ELSE m3<=m3+1; END IF; END IF; END IF;
cout1<=m3(0); END PROCESS; END ARCHITECTURE mysta;
【例7-3】 步进电机控制器的有限状态机实现。
(P248)
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ;
ENTITY stepmotor IS PORT(
clk,reset:IN STD_LOGIC; dir:IN STD_LOGIC;
phase :OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); END ENTITY stepmotor ;
ARCHITECTURE arc1 OF stepmotor IS
TYPE states IS (s0,s1,s2,s3); SIGNAL current_state: states;
BEGIN
PROCESS(clk) BEGIN
IF clk'EVENT AND clk='1' THEN IF reset='1' THEN
current_state<=s0; ELSE
CASE current_state IS WHEN s0 => .
.
IF dir='1' THEN
current_state<=s1; ELSE
current_state<=s3; END IF; WHEN s1 =>
IF dir='1' THEN
current_state<=s2; ELSE
current_state<=s0; END IF; WHEN s2 =>
IF dir='1' THEN
current_state<=s3; ELSE
current_state<=s1; END IF; WHEN s3 =>
IF dir='1' THEN
current_state<=s0; ELSE
current_state<=s2; END IF; WHEN OTHERS =>
current_state<=s0;
END CASE; END IF; END IF;
END PROCESS;
PROCESS (current_state) BEGIN
CASE current_state IS WHEN s0 =>
phase<=\"0001\"; WHEN s1 =>
phase<=\"0010\"; WHEN s2 =>
phase<=\"0100\"; WHEN s3 =>
phase<=\"1000\"; END CASE; END PROCESS;
END ARCHITECTURE arc1;
【例7-4】 Mealy型有限状态机。
(P250)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_11.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY pacheck IS PORT (
clk, rst: IN STD_LOGIC;
id: IN STD_LOGIC_VECTOR(3 DOWNTO 0); y: OUT STD_LOGIC_VECTOR(1 DOWNTO 0));
.
.
END ENTITY pacheck;
ARCHITECTURE arc1 OF pacheck is
TYPE states IS (state0, state1, state2, state3, state4); SIGNAL state: states;
SIGNAL y1: STD_LOGIC_VECTOR(1 DOWNTO 0); BEGIN
PROCESS (clk, rst) BEGIN
IF rst='1' then
state <= state0;
ELSIF (clk'EVENT and clk='1') then CASE state IS
WHEN state0 =>
IF id = x\"3\" THEN
state <= state1;
ELSE
state <= state0; END IF;
WHEN state1 => IF id = x\"1\" THEN
state <= state2; ELSE
state <= state1; END IF; WHEN state2 =>
IF id = x\"7\" THEN
state <= state3; ELSE state <= state2; END IF; WHEN state3 =>
IF id < x\"b\" THEN
state <= state4; ELSE
state <= state3;
END IF; WHEN state4 =>
IF id = x\"5\" THEN
state <= state0; ELSE state <= state4; END IF;
WHEN OTHERS => state <=state0; END CASE; END IF; END PROCESS;
PROCESS(state,clk,id)
VARIABLE tmp: STD_LOGIC_VECTOR(1 DOWNTO 0); BEGIN
CASE state IS
WHEN state0 => IF id=x\"3\" THEN tmp:=\"01\";ELSE tmp:=\"00\"; END IF; WHEN state1 => IF id=x\"1\" THEN tmp:=\"10\";ELSE tmp:=\"00\"; END IF; WHEN state2 => IF id=x\"7\" THEN tmp:=\"11\";ELSE tmp:=\"00\"; END IF; WHEN state3 => IF id=x\"B\" THEN tmp:=\"00\";ELSE tmp:=\"00\"; END IF; WHEN state4 => IF id=x\"5\" THEN tmp:=\"01\";ELSE tmp:=\"00\"; END IF; WHEN OTHERS => y<=\"00\"; END CASE;
IF clk'EVENT AND clk='1' THEN .
.
y1<=tmp; END IF; END PROCESS; y<=y1;
END ARCHITECTURE arc1;
【例7-5】 顺序编码的有限状态机。
(P253)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_11.ALL; ENTITY my_sma IS PORT(
x: IN STD_LOGIC; clk: IN STD_LOGIC; q: OUT STD_LOGIC); END ENTITY my_sma;
ARCHITECTURE arc1 OF my_sma IS
SUBTYPE states IS STD_LOGIC_VECTOR(2 DOWNTO 0); SIGNAL current_state,next_state:states; BEGIN
PROCESS(current_state,x) BEGIN
CASE current_state IS WHEN \"000\" => IF x='0' THEN q<='0';
next_state<=\"000\"; ELSE
q<='0';
next_state<=\"001\"; END IF; WHEN \"001\" =>
IF x='0' THEN q<='0';
next_state<=\"001\"; ELSE
q<='0';
next_state<=\"010\"; END IF; WHEN \"010\" =>
IF x='0' THEN q<='0';
next_state<=\"010\"; ELSE
q<='0';
next_state<=\"011\"; END IF; WHEN \"011\" =>
IF x='0' THEN q<='0';
next_state<=\"011\"; ELSE
q<='0';
next_state<=\"100\"; END IF; WHEN \"100\" =>
IF x='0' THEN q<='0';
.
.
next_state<=\"100\"; ELSE
q<='0';
next_state<=\"101\"; END IF; WHEN \"101\" =>
IF x='0' THEN q<='1';
next_state<=\"000\"; ELSE
q<='1';
next_state<=\"001\";
END IF; WHEN OTHERS => NULL; END CASE; END PROCESS;
PROCESS(clk) BEGIN
IF clk'event AND clk='1' THEN current_state<=next_state; END IF; END PROCESS;
END ARCHITECTURE arc1;
【例7-6】 采用状态位直接输出编码的交通灯控制系统。
(P255)
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; ENTITY traffic IS
PORT (clock, sensor1, sensor2, reset : IN STD_LOGIC; red1, yellow1, green1, red2, yellow2, green2 : OUT STD_LOGIC); END ENTITY traffic ;
ARCHITECTURE arc1 OF traffic IS
SUBTYPE states IS STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL current_state, next_state : states;
CONSTANT st0:states:= \"00110000\"; CONSTANT st1:states:= \"00110001\"; CONSTANT st2:states:= \"00110010\"; CONSTANT st3:states:= \"01010000\"; CONSTANT st4:states:= \"10000100\"; CONSTANT st5:states:= \"10000101\"; CONSTANT st6:states:= \"10000110\"; CONSTANT st7:states:= \"10001011\";
BEGIN
PROCESS (reset, clock) BEGIN
IF (reset='1') THEN current_state <= st0 ;
ELSIF clock'event and clock='1' THEN current_state <= next_state ; END IF ;
END PROCESS;
PROCESS (state, sensor1, sensor2) BEGIN
.
.
red1 <= '0'; yellow1 <= '0'; green1 <= '0'; red2 <= '0'; yellow2 <= '0'; green2 <= '0'; CASE state IS WHEN st0 => IF sensor2 = sensor1 THEN next_state <= st1; ELSIF (sensor1 = '0' AND sensor2 = '1') THEN next_state <= st2; ELSE next_state <= st0; END IF; WHEN st1 => next_state <= st2; WHEN st2 => next_state <= st3; WHEN st3 => next_state <= st4; WHEN st4 => IF (sensor1 = '0' AND sensor2 = '0') THEN next_state <= st5; ELSIF (sensor1 = '1' AND sensor2 = '0') THEN next_state <= st6; ELSE next_state <= st4; END IF; WHEN st5 => next_state <= st6; WHEN st6 => next_state <= st7; WHEN st7 => next_state <= st0; WHEN OTHERS =>
next_state <= st0; END CASE; END PROCESS;
red1 <= current_state(7); yellow1 <= current_state(6); green1 <= current_state(5); red2 <= current_state(4);
yellow2 <= current_state(3); green2 <= current_state(2); END ARCHITECTURE arc1;
【例7-7】 一位热码编码的有限状态机。
(P257)
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; ENTITY my_sma IS PORT(
x: IN STD_LOGIC; clk: IN STD_LOGIC; q: OUT STD_LOGIC); END ENTITY my_sma;
ARCHITECTURE arc1 OF my_sma IS
SUBTYPE states IS STD_LOGIC_VECTOR(2 DOWNTO 0); SIGNAL current_state,next_state:states;
CONSTANT st0: states := \"100000\";
CONSTANT st1: states := \"010000\"; CONSTANT st2: states := \"001000\"; .
.
CONSTANT st3: states := \"000100\"; CONSTANT st4: states := \"000010\"; CONSTANT st5: states := \"000001\";
BEGIN
PROCESS(current_state,x) BEGIN
CASE current_state IS WHEN st0 =>
IF x='0' THEN q<='0';
next_state<=st0; ELSE
q<='0';
next_state<=st1; END IF; WHEN st1 =>
IF x='0' THEN q<='0';
next_state<=st1; ELSE
q<='0';
next_state<=st2; END IF; WHEN st2 =>
IF x='0' THEN q<='0';
next_state<=st2; ELSE
q<='0';
next_state<=st3; END IF; WHEN st3 =>
IF x='0' THEN q<='0';
next_state<=st3; ELSE
q<='0';
next_state<=st4; END IF; WHEN st4 =>
IF x='0' THEN q<='0';
next_state<=st4; ELSE
q<='0';
next_state<=st5; END IF; WHEN st5 =>
IF x='0' THEN q<='1';
next_state<=st0; ELSE
q<='1';
next_state<=st1;
END IF; WHEN OTHERS => NULL; END CASE; END PROCESS;
PROCESS(clk) BEGIN
IF clk'event AND clk='1' THEN current_state<=next_state; END IF; END PROCESS; .
.
END ARCHITECTURE arc1;
（P276）
【例8-1】 全加器的设计。
LIBRARY IEEE;
USE IEEE.STD_LOGIC_11.ALL; ENTITY full_adder IS
PORT(i0, i1,ci : IN STD_LOGIC; co, s : OUT STD_LOGIC); END ENTITY full_adder;
ARCHITECTURE arc1 OF full_adder IS SIGNAL tmp: STD_LOGIC; BEGIN
tmp <= i0 XOR i1 AFTER 5ns; s <= tmp XOR ci AFTER 5ns;
co <= (i0 AND i1) OR (tmp AND ci) AFTER 10ns; END arc1;
ARCHITECTURE arc2 OF full_adder IS BEGIN
PROCESS(i0,i1,ci)
VARIABLE n : INTEGER ;
CONSTANT cout: STD_LOGIC_VECTOR(0 TO 3) := \"0011\"; CONSTANT sum: STD_LOGIC_VECTOR(0 TO 3) := \"0101\"; BEGIN
n :=0 ;
IF i0= '1' THEN n:= n+1;END IF; IF i1= '1' THEN n:= n+1;END IF; IF ci= '1' THEN n:= n+1;END IF; s<= sum(n); co<= cout(n); END PROCESS;
END ARCHITECTURE arc2 ;
CONFIGURATION con1 OF full_adder IS FOR arc1 END FOR; END con1;
CONFIGURATION con2 OF full_adder IS FOR arc2 END FOR; END con2;
（P277）
【例8-2】 采用元件配置说明方式实现的全加器的设计。
LIBRARY IEEE;
USE IEEE.STD_LOGIC_11.ALL; ENTITY or21 IS
PORT(in1,in2:IN STD_LOGIC; q : OUT STD_LOGIC); END ENTITY or21;
ARCHITECTURE arc1 OF or21 IS BEGIN .
.
q<= in1 OR in2 AFTER 10 ns; END ARCHITECTURE arc1;
CONFIGURATION con1 OF or21 IS FOR arc1 END FOR; END con1;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_11.ALL; ENTITY half_adder IS
PORT(in1,in2:IN STD_LOGIC; co,s : OUT STD_LOGIC); END ENTITY half_adder ;
ARCHITECTURE arc2 OF half_adder IS BEGIN
PROCESS(in1,in2) BEGIN
s <= in1 XOR in2 AFTER 10 ns; co <= in1 AND in2 AFTER 10 ns; END PROCESS;
END ARCHITECTURE arc2 ;
CONFIGURATION con2 OF half_adder IS FOR arc2 END FOR; END con2;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_11.ALL; ENTITY full_adder IS
PORT(in1,in2,ci:IN STD_LOGIC; co,s : OUT STD_LOGIC); END ENTITY full_adder ;
ARCHITECTURE arc OF full_adder IS COMPONENT or21
PORT(in1,in2:IN STD_LOGIC; q : OUT STD_LOGIC); END COMPONENT ;
COMPONENT half_adder
PORT(in1,in2:IN STD_LOGIC; co,s : OUT STD_LOGIC); END COMPONENT ;
SIGNAL tmp1,tmp2,tmp3: STD_LOGIC; BEGIN
U1: half_adder PORT MAP(in1,in2,tmp1,tmp2); U2: half_adder PORT MAP(ci,tmp1,tmp3,s);
U3: or21 PORT MAP(tmp2,tmp3,co); END ARCHITECTURE arc ;
(P281)
【例8-3】 ×8bit 的ROM初始化。
LIBRARY IEEE;
USE IEEE.STD_LOGIC_11.ALL; PACKAGE rom_int IS .
.
SUBTYPE ROM_WORD IS STD_LOGIC_VECTOR(7 DOWNTO 0); SUBTYPE ROM_RANGE IS INTEGER RANGE 0 TO 63; TYPE ROM_TYPE IS ARRAY(ROM_RANGE) OF ROM_WORD; CONSTANT ROM:ROM_TYPE:=(
(\"00001000\"),(\"00011010\"),(\"00000001\"),(\"10100000\"),(\"01000001\"), (\"00000010\"),(\"01010000\"),(\"00111100\"),
(\"00011010\"),(\"00000001\"),(\"00001000\"),(\"01000001\"),(\"00000010\"), (\"00111100\"),(\"10100000\"),(\"01010000\"),
(\"00000001\"),(\"00011010\"),(\"01000001\"),(\"00000010\"),(\"10100000\"), (\"00001000\"),(\"00111100\"),(\"11111111\"),
(\"01000001\"),(\"00000001\"),(\"00011010\"),(\"00000010\"),(\"00000010\"), (\"00111100\"),(\"10110101\"),(\"01010000\"),
(\"10001000\"),(\"01000001\"),(\"00001000\"),(\"01010101\"),(\"00000001\"), (\"00001000\"),(\"00111100\"),(\"00000010\"),
(\"00111101\"),(\"00111101\"),(\"00000001\"),(\"00011010\"),(\"01000001\"), (\"10100000\"),(\"00000010\"),(\"01010000\"),
(\"00111100\"),(\"01000001\"),(\"00111100\"),(\"00001000\"),(\"00011010\"), (\"10100000\"),(\"00001000\"),(\"00000010\"),
(\"01000001\"),(\"00111100\"),(\"00000001\"),(\"10100000\"),(\"00000010\"), (\"00011010\"),(\"00011010\"),(\"00001000\") ); END rom_int;
(P282)
【例8-4】 ×8bit 的ROM初始化。
…
SUBTYPE ROM_WORD IS STD_LOGIC_VECTOR(7 DOWNTO 0); SUBTYPE ROM_RANGE IS INTEGER RANGE 0 TO 63; TYPE ROM_TYPE IS ARRAY(ROM_RANGE) OF ROM_WORD; VARIABLE start1 : BOOLEAN :=TRUE; VARIABLE l : LINE; VARIABLE j : INTEGER; VARIABLE rom: ROM_TYPE;
FILE romin :TEXT IS IN \"myrom.in\"; …
IF start1 THEN
FOR j IN rom'RANGE LOOP READLINE(romin,l); READ(l,rom(j)); END LOOP; END IF;
(P282)
【例8-5】 ×8bit 的ROM设计。
LIBRARY IEEE;
USE IEEE.STD_LOGIC_11.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; USE WORK.ROM_INT.ALL;
ENTITY rom1 IS PORT(
addr:IN STD_LOGIC_VECTOR(5 DOWNTO 0) ; clk: IN STD_LOGIC; read: IN STD_LOGIC;
dataout: OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); END ENTITY rom1 ; .
.
ARCHITECTURE arc1 OF rom1 IS
SIGNAL n: INTEGER RANGE 0 TO 63; BEGIN
PROCESS(clk) BEGIN
n<=CONV_INTEGER(addr);
IF clk'EVENT AND clk='1' THEN IF read='1' THEN
dataout<=ROM(n); ELSE
dataout<=(others=>'Z'); END IF; END IF; END PROCESS; END ARCHITECTURE arc1;
(P283)
【例8-6】 ×8bit 的ROM设计。
LIBRARY IEEE;
USE IEEE.STD_LOGIC_11.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; USE STD.TEXTIO.ALL;
ENTITY rom2 IS PORT(
addr:IN STD_LOGIC_VECTOR(5 DOWNTO 0) ; clk: IN STD_LOGIC; read: IN STD_LOGIC;
dataout: OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); END ENTITY rom2 ;
ARCHITECTURE arc1 OF rom2 IS
SUBTYPE ROM_WORD IS STD_LOGIC_VECTOR(7 DOWNTO 0); SUBTYPE ROM_RANGE IS INTEGER RANGE 0 TO 63; TYPE ROM_TYPE IS ARRAY(ROM_RANGE) OF ROM_WORD; SIGNAL n: INTEGER RANGE 0 TO 63;
BEGIN
PROCESS(clk)
VARIABLE start1 : BOOLEAN :=TRUE; VARIABLE l : LINE; VARIABLE j : INTEGER; VARIABLE rom: ROM_TYPE; FILE romin : TEXT ; BEGIN
IF clk'EVENT AND clk='1' THEN IF start1 THEN
FILE_OPEN(romin,\"myrom.in\ FOR j IN rom'RANGE LOOP READLINE(romin,l); READ(l,rom(j)); END LOOP;
start1:=FALSE; END IF;
n<=CONV_INTEGER(addr); IF read='1' THEN
.
.
dataout<=ROM(n); ELSE
dataout<=\"ZZZZZZZZ\"; END IF; END IF; END PROCESS; END ARCHITECTURE arc1;
(P284)
【例8-7】 32×4bit 的RAM设计。
LIBRARY IEEE;
USE IEEE.STD_LOGIC_11.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY ram2 IS PORT(
data:INOUT STD_LOGIC_VECTOR(3 DOWNTO 0); addr: IN STD_LOGIC_VECTOR(4 DOWNTO 0); cs:IN STD_LOGIC;
read : IN STD_LOGIC; write: IN STD_LOGIC); END ENTITY ram2;
ARCHITECTURE arc1 OF ram2 IS
SUBTYPE RAM_WORD IS STD_LOGIC_VECTOR(3 DOWNTO 0); SUBTYPE RAM_RANGE IS INTEGER RANGE 0 TO 31; TYPE RAM_TYPE IS ARRAY(RAM_RANGE) OF RAM_WORD; SIGNAL myram: RAM_TYPE;
SIGNAL n: INTEGER range 0 TO 31;
BEGIN
n<= CONV_INTEGER(addr);
PROCESS(read,write,cs,n,data) BEGIN
IF cs='0' THEN
IF read='1' THEN data<=myram(n); ELSIF write='1' THEN myram(n)<= data; END IF; ELSE
data<=\"ZZZZ\"; END IF; END PROCESS;
END ARCHITECTURE arc1;
P285
【例8-8】 16×4bit的FIFO设计。
LIBRARY IEEE;
USE IEEE.STD_LOGIC_11.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY fifo2 IS PORT(
datain:IN STD_LOGIC_VECTOR(3 DOWNTO 0); dataout:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); clk,reset,wr,rd:IN STD_LOGIC; full,empty : OUT STD_LOGIC); END ENTITY fifo2; .
.
ARCHITECTURE arc1 OF fifo2 IS
SUBTYPE RAM_WORD IS STD_LOGIC_VECTOR(3 DOWNTO 0); SUBTYPE RAM_RANGE IS INTEGER RANGE 0 TO 15; TYPE RAM_TYPE IS ARRAY(RAM_RANGE) OF RAM_WORD; SIGNAL myfifo: RAM_TYPE;
SIGNAL wp,rp:INTEGER RANGE 0 TO 15; SIGNAL in_full,in_empty:STD_LOGIC;
BEGIN
full<=in_full; empty<=in_empty;
dataout<=myfifo(rp);
PROCESS(clk) --data in stack BEGIN
IF clk'EVENT AND clk='1' THEN
IF (wr='0' AND in_full='0') THEN myfifo(wp)<=datain; END IF; END IF; END PROCESS;
PROCESS(clk,reset) --wp modification BEGIN
IF reset='1' THEN wp<=0;
ELSIF (clk'EVENT AND clk='1') THEN IF (wr='0' AND in_full='0') THEN IF(wp=15) THEN wp<=0; ELSE
wp<=wp+1; END IF; END IF; END IF; END PROCESS;
PROCESS(clk,reset) --rp modification BEGIN
IF (reset='1') THEN rp<=15;
ELSIF (clk'EVENT AND clk='1') THEN IF (rd='0' AND in_empty='0') THEN IF(rp=15) THEN rp<=0; ELSE
rp<=rp+1; END IF; END IF; END IF; END PROCESS;
PROCESS(clk,reset) --empty flag BEGIN
IF reset='1' THEN in_empty<='1';
ELSIF (clk'EVENT AND clk='1') THEN
IF ( (rp=wp-2 OR (rp=15 AND wp=1) OR (rp=14 AND wp=0)) AND (rd='0' and wr='1') ) THEN in_empty<='1';
ELSIF(in_empty='1' AND wr='0') THEN in_empty<='0'; .
.
END IF; END IF; END PROCESS;
PROCESS(clk,reset) --full flag BEGIN
IF reset='1' THEN in_full<='0';
ELSIF (clk'EVENT AND clk='1') THEN
IF ( rp=wp AND wr='0' AND rd='1') THEN in_full<='1';
ELSIF(in_full='1' AND rd='0') THEN in_full<='0'; END IF; END IF; END PROCESS;
END ARCHITECTURE arc1;
P290
【例8-9】 ALU输入选择模块设计。
LIBRARY IEEE;
USE IEEE.STD_LOGIC_11.ALL; USE IEEE.NUMERIC_STD.ALL; ENTITY alumux IS PORT(
D,Q,A,B:IN UNSIGNED(3 DOWNTO 0);
ALUIN_CTRL : IN STD_LOGIC_VECTOR(2 DOWNTO 0); R,S : BUFFER UNSIGNED(3 DOWNTO 0) );
END ENTITY alumux;
ARCHITECTURE arc1 OF alumux IS BEGIN
WITH ALUIN_CTRL SELECT
R<= A WHEN \"000\"|\"001\
\"0000\" WHEN \"010\"|\"011\"|\"100\ D WHEN OTHERS; WITH ALUIN_CTRL SELECT
S<= Q WHEN \"000\"|\"010\"|\"110\ B WHEN \"001\"|\"011\ A WHEN \"100\"|\"101\ \"0000\" WHEN OTHERS; END ARCHITECTURE arc1;
P290
【例8-10】 ALU算术逻辑运算模块设计。
LIBRARY IEEE;
USE IEEE.STD_LOGIC_11.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.NUMERIC_STD.ALL; ENTITY alu IS
PORT( R,S : IN UNSIGNED(3 DOWNTO 0);
ALU_CTRL: IN STD_LOGIC_VECTOR(2 DOWNTO 0); CIN: IN STD_LOGIC;
F:BUFFER UNSIGNED(3 DOWNTO 0); G_BAR,P_BAR: BUFFER STD_LOGIC; C4:BUFFER STD_LOGIC; .
.
OVR:BUFFER STD_LOGIC ); END ENTITY alu ;
ARCHITECTURE arc1 OF alu IS
SIGNAL R1,S1,F1:UNSIGNED(4 DOWNTO 0); BEGIN
R1<= '0'&R; S1<= '0'&S;
PROCESS(R1,S1,CIN,ALU_CTRL) BEGIN
CASE ALU_CTRL IS WHEN \"000\" =>
IF CIN='0' THEN F1<= R1 + S1; ELSE
F1<= R1 + S1 + 1; END IF; WHEN \"001\" =>
IF CIN='0' THEN
F1<= S1 + NOT(R1); ELSE
F1<= S1 + NOT(R1)+1; END IF; WHEN \"010\" =>
IF CIN='0' THEN
F1<= R1 + NOT(S1); ELSE
F1<= R1 + NOT(S1)+1; END IF;
WHEN \"011\" => F1<=R1 OR S1; WHEN \"100\" => F1<=R1 AND S1;
WHEN \"101\" => F1<= (NOT R1) AND S1; WHEN \"110\" => F1<=R1 XOR S1;
WHEN \"111\" => F1<=NOT(R1 XOR S1); WHEN OTHERS=> F1<=\"--\"; END CASE; END PROCESS;
F<=F1(3 DOWNTO 0); C4<= F1(4); G_BAR<= NOT(
(R(3) AND S(3)) OR
((R(3) OR S(3)) AND (R(2) AND S(2))) OR
((R(3) OR S(3)) AND (R(2) OR S(2)) AND (R(1) AND S(1))) OR ((R(3) OR S(3)) AND (R(2) OR S(2)) AND (R(1) AND S(1)) AND
(R(0) AND S(0))) );
P_BAR<= NOT (
(R(3) OR S(3)) AND (R(2) OR S(2)) AND (R(1) AND S(1)) AND
(R(0) AND S(0)) );
OVR <= '1' WHEN (F1(4)/=F1(3)) ELSE '0'; END ARCHITECTURE arc1;
P292
【例8-11】 存储器模块设计。
LIBRARY IEEE;
USE IEEE.STD_LOGIC_11.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.NUMERIC_STD.ALL; ENTITY ram1 IS
PORT( CLK: IN STD_LOGIC;
Aaddr,Baddr,F: IN UNSIGNED(3 DOWNTO 0); .
.
RAM1_CTRL :IN STD_LOGIC_VECTOR(2 DOWNTO 0); RAM0,RAM3:IN STD_LOGIC;
A,B: BUFFER UNSIGNED (3 DOWNTO 0) ) ; END ENTITY ram1;
ARCHITECTURE arc1 OF RAM1 IS
TYPE RAM_TYPE IS ARRAY(15 DOWNTO 0) OF UNSIGNED(3 DOWNTO 0); SIGNAL AB_DATA: RAM_TYPE;
SIGNAL CTRL : STD_LOGIC_VECTOR(1 DOWNTO 0); BEGIN
CTRL <= RAM1_CTRL(2) & RAM1_CTRL(1) ; PROCESS ( CLK, Baddr ) BEGIN
IF (CLK'EVENT AND CLK='1') THEN CASE CTRL IS
WHEN \"01\" => AB_DATA(TO_INTEGER(Baddr))<= F;
WHEN \"10\" => AB_DATA(TO_INTEGER(Baddr))<= RAM3 & F(3 DOWNTO 1); WHEN \"11\" => AB_DATA(TO_INTEGER(Baddr))<= F(2 DOWNTO 0) & RAM0; WHEN OTHERS => AB_DATA(TO_INTEGER(Baddr))<= AB_DATA(TO_INTEGER(Baddr)); END CASE ; END IF ;
END PROCESS ;
A <= AB_DATA ( TO_INTEGER ( Aaddr ) ) ; B <= AB_DATA ( TO_INTEGER ( Baddr ) ) ; END ARCHITECTURE arc1 ;
P293
【例8-12】 寄存器模块设计。
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ;
USE IEEE.STD_LOGIC_UNSIGNED.ALL ; USE IEEE.NUMERIC_STD.ALL ; ENTITY qreg1 IS
PORT ( CLK : IN STD_LOGIC ;
F : IN UNSIGNED ( 3 DOWNTO 0 ) ;
Q_CTRL : IN STD_LOGIC_VECTOR ( 2 DOWNTO 0 ) ; Q0, Q3 : INOUT STD_LOGIC ;
Q : BUFFER UNSIGNED ( 3 DOWNTO 0 ) ) ; END ENTITY qreg1 ;
ARCHITECTURE arc1 OF qreg1 IS
SIGNAL Q_DATA: UNSIGNED(3 DOWNTO 0); BEGIN
PROCESS(CLK) BEGIN
IF (CLK'EVENT AND CLK='1') THEN CASE Q_CTRL IS
WHEN \"000\" => Q_DATA<= F;
WHEN \"100\" => Q_DATA<= Q3 & Q(3 DOWNTO 1); WHEN \"110\" => Q_DATA<= Q(2 DOWNTO 0) & Q0; WHEN OTHERS => Q_DATA<= Q_DATA; END CASE; END IF; END PROCESS;
Q3<= F(3) WHEN (Q_CTRL=\"110\" OR Q_CTRL=\"111\") ELSE 'Z'; Q0<= F(0) WHEN (Q_CTRL=\"100\" OR Q_CTRL=\"101\") ELSE 'Z'; END ARCHITECTURE arc1 ;
.
.
P293
【例8-13】 输出选择模块设计。
LIBRARY IEEE;
USE IEEE.STD_LOGIC_11.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.NUMERIC_STD.ALL; ENTITY outmux IS
PORT( A, F : IN UNSIGNED(3 DOWNTO 0) ;
MUX_CTRL : IN STD_LOGIC_VECTOR(2 DOWNTO 0) ; OE : IN STD_LOGIC ;
Y : BUFFER UNSIGNED (3 DOWNTO 0) ) ; END ENTITY outmux;
ARCHITECTURE arc1 OF outmux IS
SIGNAL Y_DATA: UNSIGNED(3 DOWNTO 0); BEGIN
Y_DATA<= A WHEN MUX_CTRL=\"010\" ELSE F; Y<= Y_DATA WHEN OE='0' ELSE \"ZZZZ\"; END ARCHITECTURE arc1;
P294
【例8-14】 4位微处理器系统的顶层描述。
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ;
USE IEEE.STD_LOGIC_UNSIGNED.ALL ; USE IEEE.NUMERIC_STD.ALL ; PACKAGE cpu4_comps IS COMPONENT alumux
PORT( D,Q,A,B:IN UNSIGNED(3 DOWNTO 0);
ALUIN_CTRL : IN STD_LOGIC_VECTOR(2 DOWNTO 0); R,S : BUFFER UNSIGNED(3 DOWNTO 0) ); END COMPONENT;
COMPONENT alu
PORT( R,S : IN UNSIGNED(3 DOWNTO 0);
ALU_CTRL: IN STD_LOGIC_VECTOR(2 DOWNTO 0); CIN: IN STD_LOGIC;
F:BUFFER UNSIGNED(3 DOWNTO 0); G_BAR,P_BAR: BUFFER STD_LOGIC; C4:BUFFER STD_LOGIC; OVR:BUFFER STD_LOGIC ); END COMPONENT;
COMPONENT ram1
PORT( CLK: IN STD_LOGIC;
Aaddr,Baddr,F: IN UNSIGNED(3 DOWNTO 0);
RAM1_CTRL :IN STD_LOGIC_VECTOR(2 DOWNTO 0); RAM0,RAM3:INOUT STD_LOGIC;
A,B: BUFFER UNSIGNED (3 DOWNTO 0) ); END COMPONENT;
COMPONENT qreg1
PORT ( CLK : IN STD_LOGIC ;
F: IN UNSIGNED(3 DOWNTO 0) ;
Q_CTRL :IN STD_LOGIC_VECTOR(2 DOWNTO 0) ; Q0,Q3:INOUT STD_LOGIC ; .
.
Q: BUFFER UNSIGNED (3 DOWNTO 0) ) ; END COMPONENT;
COMPONENT outmux
PORT( A, F : IN UNSIGNED(3 DOWNTO 0);
MUX_CTRL :IN STD_LOGIC_VECTOR(2 DOWNTO 0); OE : IN STD_LOGIC;
Y: BUFFER UNSIGNED (3 DOWNTO 0) ); END COMPONENT; END cpu4_comps ;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_11.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.NUMERIC_STD.ALL; USE WORK.cpu4_comps.ALL; ENTITY cpu4 IS
PORT( CLK: IN STD_LOGIC;
Aaddr,Baddr: IN UNSIGNED(3 DOWNTO 0); D:IN UNSIGNED(3 DOWNTO 0);
I:IN STD_LOGIC_VECTOR(8 DOWNTO 0); CIN : IN STD_LOGIC; OE: IN STD_LOGIC;
RAM0,RAM3:INOUT STD_LOGIC; Q0,Q3:INOUT STD_LOGIC;
Y: BUFFER UNSIGNED (3 DOWNTO 0); G_BAR,P_BAR:BUFFER STD_LOGIC; C4: BUFFER STD_LOGIC; OVR: BUFFER STD_LOGIC; F_0: BUFFER STD_LOGIC; F_3:BUFFER STD_LOGIC ) ; END ENTITY cpu4 ;
ARCHITECTURE arc1 OF cpu4 IS
SIGNAL ALUIN_CTRL: STD_LOGIC_VECTOR(2 DOWNTO 0):= I(2 DOWNTO 0); SIGNAL ALU_CTRL: STD_LOGIC_VECTOR(2 DOWNTO 0):= I(5 DOWNTO 3); SIGNAL RAM1_CTRL: STD_LOGIC_VECTOR(2 DOWNTO 0):= I(8 DOWNTO 6); SIGNAL Q_CTRL: STD_LOGIC_VECTOR(2 DOWNTO 0):= I(8 DOWNTO 6); SIGNAL MUX_CTRL: STD_LOGIC_VECTOR(2 DOWNTO 0):= I(8 DOWNTO 6); SIGNAL A,B: UNSIGNED(3 DOWNTO 0); SIGNAL Q: UNSIGNED(3 DOWNTO 0); SIGNAL R,S: UNSIGNED(3 DOWNTO 0); SIGNAL F: UNSIGNED(3 DOWNTO 0); BEGIN
U1: ram1 PORT MAP (CLK,Aaddr,Baddr,F,RAM1_CTRL,RAM0,RAM3,A,B) ; U2: qreg1 PORT MAP (CLK,F,Q_CTRL,Q0,Q3,Q) ; U3: alumux PORT MAP (D,Q,A,B,ALUIN_CTRL,R,S) ;
U4: alu PORT MAP ( R,S,ALU_CTRL,CIN,F,G_BAR,P_BAR,C4,OVR) ; U5: outmux PORT MAP ( A,F,MUX_CTRL,OE,Y) ; F_3 <= F(3) ;
F_0 <= '0' WHEN F = \"0000\" ; END ARCHITECTURE arc1 ;
P299
【例9-1】 全加器仿真程序。
LIBRARY IEEE;
USE IEEE.STD_LOGIC_11.ALL; ENTITY f_adder IS .
.
PORT(
ain,bin:IN STD_LOGIC; cin:IN STD_LOGIC;
sum,cout:OUT STD_LOGIC );
END ENTITY f_adder;
ARCHITECTURE arc1 OF f_adder IS SIGNAL tmp: STD_LOGIC; BEGIN
tmp <= ain XOR bin ; sum <= tmp XOR cin ;
cout <= (ain AND bin) OR (tmp AND cin) ; END ARCHITECTURE arc1;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_11.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY test_fadder IS END ENTITY test_fadder;
ARCHITECTURE arc1 OF test_fadder IS COMPONENT f_adder IS
PORT(ain,bin:IN STD_LOGIC; cin:IN STD_LOGIC;
cout,sum:OUT STD_LOGIC ); END COMPONENT f_adder;
SIGNAL test_a,test_b,test_c : STD_LOGIC; SIGNAL test_co,test_s:STD_LOGIC;
BEGIN
U0: f_adder PORT MAP (ain=>test_a ,bin=>test_b,cin=>test_c, cout=>test_co,sum=>test_s);
PROCESS BEGIN
test_a <= '0'; WAIT FOR 400 ns; test_a <= '1'; WAIT FOR 400 ns; test_a <= '0'; WAIT FOR 200 ns; test_a <= '1';
WAIT FOR 1000 ns; test_a <= '0'; WAIT;
END PROCESS;
PROCESS BEGIN
test_b <= '0'; WAIT FOR 500 ns; test_b <= '1'; WAIT FOR 800 ns; test_b <= '0'; WAIT;
END PROCESS;
PROCESS BEGIN
test_c <= '0'; .
.
WAIT FOR 400 ns; test_c <= '1'; WAIT FOR 700 ns; test_c <= '0'; WAIT FOR 400 ns; test_c <= '1'; WAIT FOR 600 ns; test_c <= '0'; WAIT;
END PROCESS;
END ARCHITECTURE arc1;
P302
【例9-2】 全加器仿真程序。
LIBRARY IEEE;
USE STD_TEXTIO.ALL;
USE IEEE.STD_LOGIC_11.ALL; USE IEEE.STD_LOGIC_TEXTIO.ALL; ENTITY test_fadder IS END ENTITY test_fadder;
ARCHITECTURE arc2 OF test_fadder IS COMPONENT f_adder IS
PORT(ain,bin:IN STD_LOGIC; cin:IN STD_LOGIC;
cout,sum:OUT STD_LOGIC ); END COMPONENT f_adder;
FILE intest : TEXT IS IN \"test1.in\";
SIGNAL test_ain,test_bin,test_cin : STD_LOGIC; SIGNAL test_co,test_s:STD_LOGIC; BEGIN
U0: f_adder PORT MAP (ain=>test_ain ,bin=>test_bin,cin=>test_cin, cout=>test_co,sum=>test_s); PROCESS
VARIABLE li:LINE;
VARIABLE ain,bin,cin:STD_LOGIC; BEGIN
READLINE (intest,li); READ(li,ain); READ(li,bin); READ(li,cin); test_ain<=ain;
test_bin<=bin; test_cin<=cin; WAIT FOR 100 ns;
IF(ENDFILE(intest))THEN WAIT;
END IF; END PROCESS;
END ARCHITECTURE arc2;
P304
【例9-3】 全加器仿真程序。
LIBRARY IEEE;
USE STD_TEXTIO.ALL;
USE IEEE.STD_LOGIC_11.ALL; .
.
USE IEEE.STD_LOGIC_TEXTIO.ALL; ENTITY test_fadder IS END ENTITY test_fadder;
ARCHITECTURE arc1 OF test_fadder IS COMPONENT f_adder IS
PORT(ain,bin:IN STD_LOGIC; cin:IN STD_LOGIC;
cout,sum:OUT STD_LOGIC ); END COMPONENT f_adder;
FILE intest : TEXT IS IN \"test1.in\";
FILE outtest : TEXT IS OUT \"test1.out\";
SIGNAL test_ain,test_bin,test_cin : STD_LOGIC; SIGNAL test_co,test_s:STD_LOGIC;
BEGIN
U0: f_adder PORT MAP (ain=>test_ain ,bin=>test_bin,cin=>test_cin, cout=>test_co,sum=>test_s); PROCESS
VARIABLE li,ou:LINE;
VARIABLE ain,bin,cin:STD_LOGIC;
VARIABLE out_vector:STD_LOGIC(1 DOWNTO 0); BEGIN
WHILE NOT ENDFILE (intest) LOOP READLINE (intest,li); READ(li,ain); READ(li,bin); READ(li,cin); test_ain<=ain; test_bin<=bin; test_cin<=cin;
WAIT FOR 20 ns; -- wait for circuit to settle out_vector := sum & cout; WRITE(ou,out_vector); WRITELINE(outtest,ou); WAIT FOR 80 ns; END LOOP;
ASSERT FALSE REPORT “Test completed”; END PROCESS;
END ARCHITECTURE arc1;
P305
【例9-4】 仿真程序。
LIBRARY IEEE;
USE IEEE.STD_LOGIC_11.ALL; ENTITY sim1 IS
PORT(a,b:IN STD_LOGIC; c:OUT STD_LOGIC); END ENTITY sim1;
ARCHITECTURE arc1 OF sim1 IS SIGNAL d,e:STD_LOGIC; BEGIN
d<= NOT(a) ; e<= b AND d; c<= d AND e;
END ARCHITECTURE arc1; .
.
P310
【例9-5】 加法器示例程序。
LIBRARY IEEE;
USE IEEE.STD_LOGIC_11.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; ENTITY sadder IS PORT(
a,b,c,d:IN STD_LOGIC_VECTOR(3 DOWNTO 0); s:IN STD_LOGIC;
q:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); cout:OUT STD_LOGIC);
END ENTITY sadder;
ARCHITECTURE arc1 OF sadder IS
SIGNAL tmp: STD_LOGIC_VECTOR(4 DOWNTO 0); BEGIN
PROCESS(a,b,c,d,s) BEGIN
IF s='0' THEN tmp<=('0'&a)+('0'&b); ELSE tmp<=('0'&c)+('0'&d); END IF; END PROCESS;
q<= tmp(3)&tmp(2)&tmp(1)&tmp(0); cout<=tmp(4);
END ARCHITECTURE arc1;
P311
【例9-6】 采用了面积优化的加法器示例程序。
LIBRARY IEEE;
USE IEEE.STD_LOGIC_11.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY sadder IS PORT(
a,b,c,d:IN STD_LOGIC_VECTOR(3 DOWNTO 0); s:IN STD_LOGIC;
q:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); cout: OUT STD_LOGIC); END ENTITY sadder;
ARCHITECTURE arc1 OF sadder IS
SIGNAL tmp,tmp1,tmp2: STD_LOGIC_VECTOR(4 DOWNTO 0); BEGIN
PROCESS(a,b,c,d,s) BEGIN
IF s='0' THEN
tmp1<='0'&a; tmp2<='0'&b; ELSE
tmp1<='0'&c; tmp2<='0'&d; END IF;
tmp<= tmp1+ tmp2; .
.
END PROCESS;
q<= tmp(3)&tmp(2)&tmp(1)&tmp(0); cout<=tmp(4); END ARCHITECTURE arc1;
P340
【例10-1】 由Quartus II软件生成的电路模块testblock下层的VHDL语言文件testblock.vhd的示例程序。
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_11.ALL ; -- Entity Declaration ENTITY testblock IS
-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! GENERIC(clr : string:= '1'; data_A[7..0] : string:= \"11111111\"; data_B[7..0] : string:= \"00000000\"; );
PORT ( clk : IN STD_LOGIC ; clr : IN STD_LOGIC ; addr_A : IN STD_LOGIC_VECTOR ( 15 downto 0 ) ; addr_B : IN STD_LOGIC_VECTOR ( 15 downto 0 ) ; data_A : INOUT STD_LOGIC_VECTOR ( 7 downto 0 ) ; data_B : INOUT STD_LOGIC_VECTOR ( 7 downto 0 ) ) ; -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! END testblock ;
-- Architecture Body
ARCHITECTURE testblock_architecture OF testblock IS BEGIN
-- 添加其他语句;
END testblock_architecture ;
P347
【例10-2】 由Quartus II软件的文本编辑器的“插入模板”对话框生成的实体声明的示例程序（采用VHDL语言编写程序）。
ENTITY __entity_name IS GENERIC ( __parameter_name : string := __default_value ; __parameter_name : integer:= __default_value ) ; PORT ( __input_name, __input_name : IN STD_LOGIC ; __input_vector_name : IN STD_LOGIC_VECTOR ( __high DOWNTO __low ) ; __bidir_name, __bidir_name : INOUT STD_LOGIC ; __output_name, __output_name : OUT STD_LOGIC ) ;
END __entity_name ;
.
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