STATUS BITS FOR CACHE MEMORY

专利名称：STATUS BITS FOR CACHE MEMORY发明人：WATT, Simon, Charles申请号：EP00901787.2申请日：20000204公开号：EP1190325B1公开日：20030618

摘要：Data processing apparatuses provided comprising a memory operable to storea plurality of data words, each data word being associated with at least one status bitgiving information regarding a status of said data word; a status bit store operable tostore said status bits within a hierarchical relationship such that a combined statusrelating to a plurality of first level status bits at a first level within said hierarchicalrelationship is indicated by a second lever status bit at a second level within saidhierarchical relationship, said second level being higher in said hierarchical relationshipthan said first level; and status querying logic operative to determine a status of a dataword within said memory by examining status bits within said status bit store starting at atop level within said hierarchical relationship and working down through said hierarchicalrelationship until a status bit is reached that indicates said status of said data wordindependently of any status bits lower in said hierarchical relationship. In this way aglobal or large-scale change to status bits may be made by modifying relatively fewhigher level status bits within the hierarchical relationship thereby achieving a high speedchange with reduced levels of special purpose hardware being required.

申请人：ADVANCED RISC MACH LTD

地址：GB

国籍：GB

代理机构：Robinson, Nigel Alexander Julian

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