Verilog HDL4 7 分频代码

module quarter_clk(reset,clk_in,clk_out);

input clk_in,reset;

output clk_out;

reg clk_out;

reg [4:0]count;

always@(posedge clk_in)

begin

if(!reset)

clk_out=0;

else

if (count<1)

begin

count<=count+1;

end

else

begin

count<=0;

clk_out=~clk_out;

end

end

endmodule

仿真

`define clk_cycle 50

module test_quarter_clk;

reg clk,reset;

wire clk_out;

always

#`clk_cycle clk=~clk;

initial

begin

clk=0;

reset=1;

#100 reset=0;

#100 reset=1;

#10000 $stop;

end

quarter_clk quarter_clk1(reset,clk,clk_out);

endmodule

7分频

module div7(rst,clk,cout1,cout2,cout);

input clk,rst;

output cout1,cout2,cout;

reg [2:0] m,n;

wire cout;

reg cout1,cout2;

assign cout=cout1|cout2;

always @(posedge clk)

begin

if(rst) begin cout1<=0;m<=0;end

else if(!rst) begin if(m==6) begin m<=0;end

else m<=m+1; if(m==2) cout1=~cout1;

else if(m==5) cout1=~cout1;

end

end

always @(negedge clk)

begin

if(rst) begin cout2<=0;n<=0;end

else if(!rst) begin if(n==6) begin n<=0;end

else n<=n+1;

if(n==2) cout2=~cout2;

else if(n==5) cout2=~cout2;

end

end

Endmodule

仿真

`timescale 1ns / 1ps

`define clk_cycle 50

module qii;

reg clk,rst;

wire cout1,cout2,cout;

always

#`clk_cycle clk=~clk;

initial

begin

clk=0;

rst=1;

#200 rst=0;

#10000 $stop;

end

div7 div71(rst,clk,cout1,cout2,cout);

endmodule