www.ti.com
SLAS547H–JUNE2007–REVISEDAUGUST2011
MIXEDSIGNALMICROCONTROLLER
FEATURES
LowSupply-VoltageRange,1.8Vto3.6VUltra-LowPowerConsumption
–ActiveMode:270µAat1MHz,2.2V–StandbyMode(VLO):0.3µA
–OffMode(RAMRetention):0.1µA
Ultra-FastWake-UpFromStandbyModeinLessThan1µs
16-BitRISCArchitecture,62.5-nsInstructionCycleTime
BasicClockModuleConfigurations:–InternalFrequenciesupto16MHz–InternalVeryLow-PowerLFOscillator–32-kHzCrystal
–InternalFrequenciesupto16MHzWithFourCalibratedFrequenciesto±1%–Resonator
–ExternalDigitalClockSource–ExternalResistor
12-BitAnalog-to-Digital(A/D)ConverterWithInternalReference,Sample-and-Hold,andAutoscanFeature
16-BitTimer_AWithThreeCapture/CompareRegisters
16-BitTimer_BWithSevenCapture/CompareWithShadowRegisters
FourUniversalSerialCommunicationInterfaces(USCI)
–USCI_A0andUSCI_A1
–EnhancedUARTSupportingAuto-BaudrateDetection
–IrDAEncoderandDecoder–SynchronousSPI
–USCI_B0andUSCI_B1–I2C
–SynchronousSPI
•••••
On-ChipComparator
SupplyVoltageSupervisor/MonitorWithProgrammableLevelDetectionBrownoutDetectorBootstrapLoader
SerialOnboardProgramming,NoExternalProgrammingVoltageNeeded,ProgrammableCodeProtectionbySecurityFuseFamilyMembersInclude:–MSP430F233
–8KB+256BFlashMemory,–1KBRAM–MSP430F235
–16KB+256BFlashMemory–2KBRAM
–MSP430F247,MSP430F2471(1)
–32KB+256BFlashMemory–4KBRAM
–MSP430F248,MSP430F2481–48KB+256BFlashMemory–4KBRAM
–MSP430F249,MSP430F2491–60KB+256BFlashMemory–2KBRAM–MSP430F2410
–56KB+256BFlashMemory–4KBRAM
Availablein64-PinQFPand64-PinQFNPackages(SeeAvailableOptions)
ForCompleteModuleDescriptions,See
MSP430x2xxFamilyUser’sGuide,LiteratureNumberSLAU144
TheMSP430F24x1devicesareidenticaltotheMSP430F24xdevices,withtheexceptionthattheADC12moduleisnotimplementedontheMSP430F24x1.
••
•••
•
•
•••
••
(1)
Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet.
MSP430isatrademarkofTexasInstruments.
Copyright©2007–2011,TexasInstrumentsIncorporated
PRODUCTIONDATAinformationiscurrentasofpublicationdate.ProductsconformtospecificationsperthetermsoftheTexasInstrumentsstandardwarranty.Productionprocessingdoesnotnecessarilyincludetestingofallparameters.
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MSP430F23xMSP430F24x(1)MSP430F2410
SLAS547H–JUNE2007–REVISEDAUGUST2011
www.ti.com
ThisintegratedcircuitcanbedamagedbyESD.TexasInstrumentsrecommendsthatallintegratedcircuitsbehandledwithappropriateprecautions.Failuretoobserveproperhandlingandinstallationprocedurescancausedamage.
ESDdamagecanrangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmaybemoresusceptibletodamagebecauseverysmallparametricchangescouldcausethedevicenottomeetitspublishedspecifications.
DESCRIPTION
TheTexasInstrumentsMSP430™familyofultra-lowpowermicrocontrollersconsistsofseveraldevicesfeaturingdifferentsetsofperipheralstargetedforvariousapplications.Thearchitecture,combinedwithfivelow-powermodes,isoptimizedtoachieveextendedbatterylifeinportablemeasurementapplications.Thedevicefeaturesapowerful16-bitRISCCPU,16-bitregisters,andconstantgeneratorsthatcontributetomaximumcodeefficiency.Thecalibrateddigitallycontrolledoscillator(DCO)allowswake-upfromlow-powermodestoactivemodeinlessthan1µs.
TheMSP430F23x/24x(1)/2410seriesaremicrocontrollerconfigurationswithtwobuilt-in16-bittimers,afast12-bitA/Dconverter(notMSP430F24x1),acomparator,four(twoinMSP430F23x)universalserialcommunicationinterface(USCI)modules,andupto48I/Opins.TheMSP430F24x1devicesareidenticaltotheMSP430F24xdevices,withtheexceptionthattheADC12moduleisnotimplemented.TheMSP430F23xdevicesareidenticaltotheMSP430F24xdevices,withtheexceptionthatareducedTimer_B,oneUSCImodule,andlessRAMareintegrated.
Typicalapplicationsincludesensorsystems,industrialcontrolapplications,hand-heldmeters,etc.
Table1.AvailableOptions
TA
PACKAGEDDEVICES(1)(2)
PLASTIC64-PINQFP(PM)
MSP430F233TPMMSP430F235TPMMSP430F247TPMMSP430F2471TPM
-40°Cto105°C
MSP430F248TPMMSP430F2481TPMMSP430F249TPMMSP430F2491TPMMSP430F2410TPM
(1)(2)
PLASTIC64-PINQFN(RGC)
MSP430F233TRGCMSP430F235TRGCMSP430F247TRGCMSP430F2471TRGCMSP430F248TRGCMSP430F2481TRGCMSP430F249TRGCMSP430F2491TRGCMSP430F2410TRGC
Forthemostcurrentpackageandorderinginformation,seethePackageOptionAddendumattheendofthisdocument,orseetheTIwebsiteatwww.ti.com.
Packagedrawings,thermaldata,andsymbolizationareavailableatwww.ti.com/packaging.
DevelopmentToolSupport
AllMSP430microcontrollersincludeanEmbeddedEmulationModule(EEM)allowingadvanceddebuggingandprogrammingthrougheasytousedevelopmenttools.Recommendedhardwareoptionsincludethefollowing:•DebuggingandProgrammingInterface–MSP-FET430UIF(USB)
–MSP-FET430PIF(ParallelPort)
•DebuggingandProgrammingInterfacewithTargetBoard–MSP-FET430U64(PMpackage)•StandaloneTargetBoard
–MSP-TS430PM64(PMpackage)•ProductionProgrammer–MSP-GANG430
2Copyright©2007–2011,TexasInstrumentsIncorporated
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MSP430F23xMSP430F24x(1)MSP430F2410
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SLAS547H–JUNE2007–REVISEDAUGUST2011
DevicePinout,MSP430F23x
AVCCDVSSAVSSP6.2/A2P6.1/A1P6.0/A0RST/NMITCKTMSTDI/TCLKTDO/TDIXT2INXT2OUTP5.7/TBOUTH/SVSOUTP5.6/ACLKP5.5/SMCLKDVCC
P6.3/A3P6.4/A4P6.5/A5P6.6/A6
P6.7/A7/SVSIN
VREF+XINXOUTVeREF+
VREF-/VeREF-P1.0/TACLK/CAOUT
P1.1/TA0P1.2/TA1P1.3/TA2P1.4/SMCLK
64636261605958575655545352515049
481234
56789101112131415
MSP430F23x
4746454443424140393837363534
PM OR RGC PACKAGE
(TOPVIEW)
163317181920212223242526272829303132
P5.4/MCLKP5.3P5.2P5.1P5.0
P4.7/TBCLKP4.6P4.5P4.4P4.3
P4.2/TB2P4.1/TB1P4.0/TB0P3.7P3.6
P3.5/UCA0RXD/UCA0SOMI
P1.5/TA0P1.6/TA1P1.7/TA2P2.0/ACLK/CA2P2.1/TAINCLK/CA3P2.2/CAOUT/TA0/CA4P2.3/CA0/TA1P2.4/CA1/TA2P2.5/ROSC/CA5P2.6/ADC12CLK/CA6P2.7/TA0/CA7P3.0/UCB0STE/UCA0CLKP3.1/UCB0SIMO/UCB0SDAP3.2/UCB0SOMI/UCB0SCLP3.3/UCB0CLK/UCA0STEP3.4/UCA0TXD/UCA0SIMOCopyright©2007–2011,TexasInstrumentsIncorporated3
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MSP430F23xMSP430F24x(1)MSP430F2410
SLAS547H–JUNE2007–REVISEDAUGUST2011
www.ti.com
DevicePinout,MSP430F24x,MSP430F2410
AVCCDVSSAVSSP6.2/A2P6.1/A1P6.0/A0RST/NMITCKTMSTDI/TCLKTDO/TDIXT2INXT2OUTP5.7/TBOUTH/SVSOUTP5.6/ACLKP5.5/SMCLKDVCC
P6.3/A3P6.4/A4P6.5/A5P6.6/A6
P6.7/A7/SVSIN
VREF+XINXOUTVeREF+
VREF-/VeREF-P1.0/TACLK/CAOUT
P1.1/TA0P1.2/TA1P1.3/TA2P1.4/SMCLK
64636261605958575655545352515049
481234
56789101112131415
MSP430F2410,MSP430F24x
4746454443424140393837363534
PM OR RGC PACKAGE
(TOPVIEW)
163317181920212223242526272829303132
P5.4/MCLK
P5.3/UCB1CLK/UCA1STEP5.2/UCB1SOMI/UCB1SCLP5.1/UCB1SIMO/UCB1SDAP5.0/UCB1STE/UCA1CLKP4.7/TBCLKP4.6/TB6P4.5/TB5P4.4/TB4P4.3/TB3P4.2/TB2P4.1/TB1P4.0/TB0
P3.7/UCA1RXD/UCA1SOMIP3.6/UCA1TXD/UCA1SIMOP3.5/UCA0RXD/UCA0SOMI
4
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P1.5/TA0P1.6/TA1P1.7/TA2P2.0/ACLK/CA2P2.1/TAINCLK/CA3P2.2/CAOUT/TA0/CA4P2.3/CA0/TA1P2.4/CA1/TA2P2.5/ROSC/CA5P2.6/ADC12CLK/CA6P2.7/TA0/CA7P3.0/UCB0STE/UCA0CLKP3.1/UCB0SIMO/UCB0SDAP3.2/UCB0SOMI/UCB0SCLP3.3/UCB0CLK/UCA0STEP3.4/UCA0TXD/UCA0SIMOCopyright©2007–2011,TexasInstrumentsIncorporated
MSP430F23xMSP430F24x(1)MSP430F2410
www.ti.com
SLAS547H–JUNE2007–REVISEDAUGUST2011
DevicePinout,MSP430F24x1
AVCCDVSSAVSSP6.2P6.1P6.0RST/NMITCKTMSTDI/TCLKTDO/TDIXT2INXT2OUTP5.7/TBOUTH/SVSOUTP5.6/ACLKP5.5/SMCLKDVCCP6.3P6.4P6.5P6.6
P6.7/A7/SVSIN
VREF+XINXOUTDVSSDVSS
P1.0/TACLK/CAOUT
P1.1/TA0P1.2/TA1P1.3/TA2P1.4/SMCLK
64636261605958575655545352515049
481234
56789101112131415
MSP430F24x1
4746454443424140393837363534
PM OR RGC PACKAGE
(TOPVIEW)
163317181920212223242526272829303132
P5.4/MCLK
P5.3/UCB1CLK/UCA1STEP5.2/UCB1SOMI/UCB1SCLP5.1/UCB1SIMO/UCB1SDAP5.0/UCB1STE/UCA1CLKP4.7/TBCLKP4.6/TB6P4.5/TB5P4.4/TB4P4.3/TB3P4.2/TB2P4.1/TB1P4.0/TB0
P3.7/UCA1RXD/UCA1SOMIP3.6/UCA1TXD/UCA1SIMOP3.5/UCA0RXD/UCA0SOMI
P1.5/TA0P1.6/TA1P1.7/TA2P2.0/ACLK/CA2P2.1/TAINCLK/CA3P2.2/CAOUT/TA0/CA4P2.3/CA0/TA1P2.4/CA1/TA2P2.5/ROSC/CA5P2.6/ADC12CLK/CA6P2.7/TA0/CA7P3.0/UCB0STE/UCA0CLKP3.1/UCB0SIMO/UCB0SDAP3.2/UCB0SOMI/UCB0SCLP3.3/UCB0CLK/UCA0STEP3.4/UCA0TXD/UCA0SIMOCopyright©2007–2011,TexasInstrumentsIncorporated5
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MSP430F23xMSP430F24x(1)MSP430F2410
SLAS547H–JUNE2007–REVISEDAUGUST2011
www.ti.com
FunctionalBlockDiagram,MSP430F23x
XIN/XT2IN2XOUT/XT2OUT
2P3.x/P4.xP5.x/P6.x
4x8DVCCDVSSAVCCAVSSP1.x/P2.x2x8ACLKOscillatorsBasic ClockSMCLKSystem+MCLKFlash16kB8kBRAM2kB1kBADC1212-Bit8ChannelsPortsP1/P22x8 I/OInterruptcapabilityPortsP3/P4P5/P64x8 I/O16MHzCPUincl. 16RegistersMABMDBEmulationJTAGInterfaceBORSVS/SVMHardwareMultiplierMPY,MPYS,MAC,MACSTimer_B3WatchdogWDT+15/16-BitTimer_A33 CCRegisters3 CCRegisters,ShadowRegComp_A+USCIA0UART/LIN,IrDA, SPIUSCI B0SPI, I2CRST/NMI6Copyright©2007–2011,TexasInstrumentsIncorporated
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MSP430F23xMSP430F24x(1)MSP430F2410
www.ti.com
SLAS547H–JUNE2007–REVISEDAUGUST2011
FunctionalBlockDiagram,MSP430F24x,MSP430F2410
XIN/XT2IN2XOUT/XT2OUT
2P3.x/P4.xP5.x/P6.x
4x8DVCCDVSSAVCCAVSSP1.x/P2.x2x8ACLKOscillatorsBasic ClockSMCLKSystem+MCLKFlash60kB56kB48kB32kBRAM2kB4kB4kB4kBADC1212-Bit8ChannelsPortsP1/P22x8 I/OInterruptcapabilityPortsP3/P4P5/P64x8 I/O16MHzCPUincl. 16RegistersMABMDBEmulationJTAGInterfaceBORSVS/SVMHardwareMultiplierMPY,MPYS,MAC,MACSTimer_B7WatchdogWDT+15/16-BitTimer_A33 CCRegisters7 CCRegisters,ShadowRegComp_A+USCIA0UART/LIN,IrDA, SPIUSCI B0SPI, I2CUSCIA1UART/LIN,IrDA, SPIUSCI B1SPI, I2CRST/NMICopyright©2007–2011,TexasInstrumentsIncorporated7
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MSP430F23xMSP430F24x(1)MSP430F2410
SLAS547H–JUNE2007–REVISEDAUGUST2011
www.ti.com
FunctionalBlockDiagram,MSP430F24x1
XIN/XT2IN2XOUT/XT2OUT
2P3.x/P4.xP5.x/P6.x
4x8DVCCDVSSAVCCAVSSP1.x/P2.x2x8ACLKOscillatorsBasic ClockSMCLKSystem+MCLKFlash60kB48kB32kBRAM2kB4kB4kBPortsP1/P22x8 I/OInterruptcapabilityPortsP3/P4P5/P64x8 I/O16MHzCPUincl. 16RegistersMABMDBEmulationJTAGInterfaceBORSVS/SVMHardwareMultiplierMPY,MPYS,MAC,MACSTimer_B7WatchdogWDT+15/16-BitTimer_A33 CCRegisters7 CCRegisters,ShadowRegComp_A+USCIA0UART/LIN,IrDA, SPIUSCI B0SPI, I2CUSCIA1UART/LIN,IrDA, SPIUSCI B1SPI, I2CRST/NMI8Copyright©2007–2011,TexasInstrumentsIncorporated
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MSP430F23xMSP430F24x(1)MSP430F2410
www.ti.com
SLAS547H–JUNE2007–REVISEDAUGUST2011
Table2.TerminalFunctions,MSP430F23x
TERMINALNAME
AVCCAVSSDVCCDVSS
P1.0/TACLK/CAOUTP1.1/TA0P1.2/TA1P1.3/TA2P1.4/SMCLKP1.5/TA0P1.6/TA1P1.7/TA2P2.0/ACLK/CA2P2.1/TAINCLK/CA3P2.2/CAOUT/TA0/CA4P2.3/CA0/TA1P2.4/CA1/TA2P2.5/ROSC/CA5P2.6/ADC12CLK/CA6P2.7/TA0/CA7
P3.0/UCB0STE/UCA0CLKP3.1/UCB0SIMO/UCB0SDAP3.2/UCB0SOMI/UCB0SCLP3.3/UCB0CLK/UCA0STEP3.4/UCA0TXD/UCA0SIMOP3.5/UCA0RXD/UCA0SOMIP3.6P3.7P4.0/TB0P4.1/TB1P4.2/TB2P4.3P4.4P4.5P4.6P4.7/TBCLKP5.0P5.1P5.2P5.3P5.4/MCLKP5.5/SMCLKP5.6/ACLK
P5.7/TBOUTH/SVSOUTP6.0/A0P6.1/A1P6.2/A2
NO.646216312131415161718192021222324252627282930313233343536373839404142434445464748495051596061
I/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/O
DESCRIPTION
Analogsupplyvoltage,positive.SuppliesonlytheanalogportionofADC12.Analogsupplyvoltage,negative.SuppliesonlytheanalogportionofADC12.Digitalsupplyvoltage,positive.Suppliesalldigitalparts.Digitalsupplyvoltage,negative.Suppliesalldigitalparts.
General-purposedigitalI/O/Timer_A,clocksignalTACLKinput/Comparator_Aoutput
General-purposedigitalI/O/Timer_A,capture:CCI0Ainput,compare:Out0output/BSLtransmitGeneral-purposedigitalI/O/Timer_A,capture:CCI1Ainput,compare:Out1outputGeneral-purposedigitalI/O/Timer_A,capture:CCI2Ainput,compare:Out2outputGeneral-purposedigitalI/O/SMCLKsignaloutput
General-purposedigitalI/O/Timer_A,compare:Out0outputGeneral-purposedigitalI/O/Timer_A,compare:Out1outputGeneral-purposedigitalI/O/Timer_A,compare:Out2outputGeneral-purposedigitalI/O/ACLKoutput/Comparator_AinputGeneral-purposedigitalI/O/Timer_A,clocksignalatINCLK
General-purposedigitalI/O/Timer_A,capture:CCI0Binput/Comparator_Aoutput/BSLreceive/Comparator_Ainput
General-purposedigitalI/O/Timer_A,compare:Out1output/Comparator_AinputGeneral-purposedigitalI/O/Timer_A,compare:Out2output/Comparator_Ainput
General-purposedigitalI/O/inputforexternalresistordefiningtheDCOnominalfrequency/Comparator_Ainput
General-purposedigitalI/O/conversionclock-12-bitADC/Comparator_AinputGeneral-purposedigitalI/O/Timer_A,compare:Out0output/Comparator_AinputGeneral-purposedigitalI/O/USCI_B0slavetransmitenable/USCIA0clockinput/output
General-purposedigitalI/O/USCI_B0slavein/masteroutinSPImode,SDAI2CdatainI2CmodeGeneral-purposedigitalI/O/USCI_B0slaveout/masterininSPImode,SCLI2CclockinI2CmodeGeneral-purposedigitalI/O/USCI_B0clockinput/output,USCIA0slavetransmitenable
General-purposedigitalI/O/USCI_A0transmitdataoutputinUARTmode,slavedatain/masteroutinSPImode
General-purposedigitalI/O/USCI_A0receivedatainputinUARTmode,slavedataout/masterininSPImode
General-purposedigitalI/OGeneral-purposedigitalI/O
General-purposedigitalI/O/Timer_B,capture:CCI0A/Binput,compare:Out0outputGeneral-purposedigitalI/O/Timer_B,capture:CCI1A/Binput,compare:Out1outputGeneral-purposedigitalI/O/Timer_B,capture:CCI2A/Binput,compare:Out2outputGeneral-purposedigitalI/OGeneral-purposedigitalI/OGeneral-purposedigitalI/OGeneral-purposedigitalI/O
General-purposedigitalI/O/Timer_B,clocksignalTBCLKinputGeneral-purposedigitalI/OGeneral-purposedigitalI/OGeneral-purposedigitalI/OGeneral-purposedigitalI/O
General-purposedigitalI/O/mainsystemclockMCLKoutputGeneral-purposedigitalI/O/submainsystemclockSMCLKoutputGeneral-purposedigitalI/O/auxiliaryclockACLKoutput
General-purposedigitalI/O/switchallPWMdigitaloutputportstohighimpedance-Timer_BTB0toTB6/SVScomparatoroutput
General-purposedigitalI/O/analoginputA0-12-bitADCGeneral-purposedigitalI/O/analoginputA1-12-bitADCGeneral-purposedigitalI/O/analoginputA2-12-bitADC
Copyright©2007–2011,TexasInstrumentsIncorporated9
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MSP430F23xMSP430F24x(1)MSP430F2410
SLAS547H–JUNE2007–REVISEDAUGUST2011
www.ti.com
Table2.TerminalFunctions,MSP430F23x(continued)
TERMINALNAME
P6.3/A3P6.4/A4P6.5/A5P6.6/A6P6.7/A7/SVSINXT2OUTXT2INRST/NMITCKTDI/TCLKTDO/TDITMSVeREF+VREF+VREF-/VeREF-XINXOUTQFNPad
NO.23456525358575554561071189NA
I/OI/OI/OI/OI/OI/OOIIIII/OIIOIIONA
DESCRIPTION
General-purposedigitalI/O/analoginputA3-12-bitADCGeneral-purposedigitalI/O/analoginputA4-12-bitADCGeneral-purposedigitalI/O/analoginputA5-12-bitADCGeneral-purposedigitalI/O/analoginputA6-12-bitADC
General-purposedigitalI/O/analoginputA7-12-bitADC/SVSinputOutputterminalofcrystaloscillatorXT2InputportforcrystaloscillatorXT2
Resetinput,nonmaskableinterruptinput,orbootstraploaderstart(inflashdevices)
Testclock(JTAG).TCKistheclockinputportfordeviceprogrammingtestandbootstraploaderstart.Testdatainputortestclockinput.ThedeviceprotectionfuseisconnectedtoTDI/TCLK.Testdataoutput.TDO/TDIdataoutputorprogrammingdatainputterminal.Testmodeselect.TMSisusedasaninputportfordeviceprogrammingandtest.Inputforanexternalreferencevoltage
OutputofpositiveterminalofthereferencevoltageintheADC12
Negativeterminalforthereferencevoltageforbothsources,theinternalreferencevoltage,oranexternalappliedreferencevoltage
InputforcrystaloscillatorXT1.Standardorwatchcrystalscanbeconnected.OutputforcrystaloscillatorXT1.Standardorwatchcrystalscanbeconnected.QFNpackagepadconnectiontoDVSSrecommended
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MSP430F23xMSP430F24x(1)MSP430F2410
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SLAS547H–JUNE2007–REVISEDAUGUST2011
Table3.TerminalFunctions,MSP430F24x,MSP430F2410
TERMINALNAME
AVCCAVSSDVCCDVSS
P1.0/TACLK/CAOUTP1.1/TA0P1.2/TA1P1.3/TA2P1.4/SMCLKP1.5/TA0P1.6/TA1P1.7/TA2P2.0/ACLK/CA2P2.1/TAINCLK/CA3P2.2/CAOUT/TA0/CA4P2.3/CA0/TA1P2.4/CA1/TA2P2.5/ROSC/CA5P2.6/ADC12CLK/CA6P2.7/TA0/CA7
P3.0/UCB0STE/UCA0CLKP3.1/UCB0SIMO/UCB0SDAP3.2/UCB0SOMI/UCB0SCLP3.3/UCB0CLK/UCA0STEP3.4/UCA0TXD/UCA0SIMOP3.5/UCA0RXD/UCA0SOMI
P3.6/UCA1TXD/UCA1SIMOP3.7/UCA1RXD/UCA1SOMIP4.0/TB0P4.1/TB1P4.2/TB2P4.3/TB3P4.4/TB4P4.5/TB5P4.6/TB6P4.7/TBCLK
P5.0/UCB1STE/UCA1CLKP5.1/UCB1SIMO/UCB1SDAP5.2/UCB1SOMI/UCB1SCLP5.3/UCB1CLK/UCA1STEP5.4/MCLKP5.5/SMCLKP5.6/ACLK
P5.7/TBOUTH/SVSOUTP6.0/A0
NO.64621631213141516171819202122232425262728293031323334353637383940414243444546474849505159
I/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/O
DESCRIPTION
Analogsupplyvoltage,positiveterminal.SuppliesonlytheanalogportionofADC12.Analogsupplyvoltage,negativeterminal.SuppliesonlytheanalogportionofADC12.Digitalsupplyvoltage,positiveterminal.Suppliesalldigitalparts.Digitalsupplyvoltage,negativeterminal.Suppliesalldigitalparts.
General-purposedigitalI/O/Timer_A,clocksignalTACLKinput/Comparator_Aoutput
General-purposedigitalI/O/Timer_A,capture:CCI0Ainput,compare:Out0output/BSLtransmitGeneral-purposedigitalI/O/Timer_A,capture:CCI1Ainput,compare:Out1outputGeneral-purposedigitalI/O/Timer_A,capture:CCI2Ainput,compare:Out2outputGeneral-purposedigitalI/O/SMCLKsignaloutput
General-purposedigitalI/O/Timer_A,compare:Out0outputGeneral-purposedigitalI/O/Timer_A,compare:Out1outputGeneral-purposedigitalI/O/Timer_A,compare:Out2outputGeneral-purposedigitalI/O/ACLKoutput/Comparator_AinputGeneral-purposedigitalI/O/Timer_A,clocksignalatINCLK
General-purposedigitalI/O/Timer_A,capture:CCI0Binput/Comparator_Aoutput/BSLreceive/Comparator_Ainput
General-purposedigitalI/O/Timer_A,compare:Out1output/Comparator_AinputGeneral-purposedigitalI/O/Timer_A,compare:Out2output/Comparator_Ainput
General-purposedigitalI/O/InputforexternalresistordefiningtheDCOnominalfrequency/Comparator_Ainput
General-purposedigitalI/O/Conversionclock-12-bitADC/Comparator_AinputGeneral-purposedigitalI/O/Timer_A,compare:Out0output/Comparator_AinputGeneral-purposedigitalI/O/USCI_B0slavetransmitenable/USCIA0clockinput/outputGeneral-purposedigitalI/O/USCI_B0slavein/masteroutinSPImode,SDAI2CdatainI2CmodeGeneral-purposedigitalI/O/USCI_B0slaveout/masterininSPImode,SCLI2CclockinI2CmodeGeneral-purposedigitalI/O/USCI_B0clockinput/output,USCIA0slavetransmitenable
General-purposedigitalI/O/USCI_A-transmitdataoutputinUARTmode,slavedatain/masteroutinSPImode
General-purposedigitalI/O/USCI_A0receivedatainputinUARTmode,slavedataout/masterininSPImode
General-purposedigitalI/O/USCI_A1transmitdataoutputinUARTmode,slavedatain/masteroutinSPImode
General-purposedigitalI/O/USCI_A1receivedatainputinUARTmode,slavedataout/masterininSPImode
General-purposedigitalI/O/Timer_B,capture:CCI0A/Binput,compare:Out0outputGeneral-purposedigitalI/O/Timer_B,capture:CCI1A/Binput,compare:Out1outputGeneral-purposedigitalI/O/Timer_B,capture:CCI2A/Binput,compare:Out2outputGeneral-purposedigitalI/O/Timer_B,capture:CCI3A/Binput,compare:Out3outputGeneral-purposedigitalI/O/Timer_B,capture:CCI4A/Binput,compare:Out4outputGeneral-purposedigitalI/O/Timer_B,capture:CCI5A/Binput,compare:Out5outputGeneral-purposedigitalI/O/Timer_B,capture:CCI6Ainput,compare:Out6outputGeneral-purposedigitalI/O/Timer_B,clocksignalTBCLKinput
General-purposedigitalI/O/USCI_B1slavetransmitenable/USCI_A1clockinput/outputGeneral-purposedigitalI/O/USCI_B1slavein/masteroutinSPImode,SDAI2CdatainI2CmodeGeneral-purposedigitalI/O/USCI_B1slaveout/masterininSPImode,SCLI2CclockinI2CmodeGeneral-purposedigitalI/O/USCI_B1clockinput/output,USCI_A1slavetransmitenableGeneral-purposedigitalI/O/mainsystemclockMCLKoutputGeneral-purposedigitalI/O/submainsystemclockSMCLKoutputGeneral-purposedigitalI/O/auxiliaryclockACLKoutput
General-purposedigitalI/O/switchallPWMdigitaloutputportstohighimpedance-Timer_BTB0toTB6/SVScomparatoroutput
General-purposedigitalI/O/analoginputA0-12-bitADC
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Table3.TerminalFunctions,MSP430F24x,MSP430F2410(continued)
TERMINALNAME
P6.1/A1P6.2/A2P6.3/A3P6.4/A4P6.5/A5P6.6/A6P6.7/A7/SVSINXT2OUTXT2INRST/NMITCKTDI/TCLKTDO/TDITMSVeREF+VREF+VREF-/VeREF-XINXOUTQFNPad
NO.606123456525358575554561071189NA
I/OI/OI/OI/OI/OI/OI/OI/OOIIIII/OIIOIIONA
DESCRIPTION
General-purposedigitalI/O/analoginputA1-12-bitADCGeneral-purposedigitalI/O/analoginputA2-12-bitADCGeneral-purposedigitalI/O/analoginputA3-12-bitADCGeneral-purposedigitalI/O/analoginputA4-12-bitADCGeneral-purposedigitalI/O/analoginputA5-12-bitADCGeneral-purposedigitalI/O/analoginputA6-12-bitADC
General-purposedigitalI/O/analoginputA7-12-bitADC/SVSinputOutputofcrystaloscillatorXT2InputforcrystaloscillatorXT2
Resetinput,nonmaskableinterruptinput,orbootstraploaderstart(inflashdevices)
Testclock(JTAG).TCKistheclockinputportfordeviceprogrammingtestandbootstraploaderstart.Testdatainputortestclockinput.ThedeviceprotectionfuseisconnectedtoTDI/TCLK.Testdataoutput.TDO/TDIdataoutputorprogrammingdatainputterminal.Testmodeselect.TMSisusedasaninputportfordeviceprogrammingandtest.Inputforanexternalreferencevoltage
PositiveoutputofthereferencevoltageintheADC12
Negativeinputforthereferencevoltageforbothsources,theinternalreferencevoltage,oranexternalappliedreferencevoltage
InputforcrystaloscillatorXT1.Standardorwatchcrystalscanbeconnected.OutputforcrystaloscillatorXT1.Standardorwatchcrystalscanbeconnected.QFNpackagepadconnectiontoDVSSrecommended(RGCpackageonly)
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Table4.TerminalFunctions,MSP430F24x1
TERMINALNAME
AVCCAVSSDVCCDVSS
P1.0/TACLK/CAOUTP1.1/TA0P1.2/TA1P1.3/TA2P1.4/SMCLKP1.5/TA0P1.6/TA1P1.7/TA2P2.0/ACLK/CA2P2.1/TAINCLK/CA3P2.2/CAOUT/TA0/CA4P2.3/CA0/TA1P2.4/CA1/TA2P2.5/ROSC/CA5P2.6/ADC12CLK/CA6P2.7/TA0/CA7
P3.0/UCB0STE/UCA0CLKP3.1/UCB0SIMO/UCB0SDAP3.2/UCB0SOMI/UCB0SCLP3.3/UCB0CLK/UCA0STEP3.4/UCA0TXD/UCA0SIMOP3.5/UCA0RXD/UCA0SOMI
P3.6/UCA1TXD/UCA1SIMOP3.7/UCA1RXD/UCA1SOMIP4.0/TB0P4.1/TB1P4.2/TB2P4.3/TB3P4.4/TB4P4.5/TB5P4.6/TB6P4.7/TBCLK
P5.0/UCB1STE/UCA1CLKP5.1/UCB1SIMO/UCB1SDAP5.2/UCB1SOMI/UCB1SCLP5.3/UCB1CLK/UCA1STEP5.4/MCLKP5.5/SMCLKP5.6/ACLK
P5.7/TBOUTH/SVSOUTP6.0
NO.64621631213141516171819202122232425262728293031323334353637383940414243444546474849505159
I/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/O
DESCRIPTION
Analogsupplyvoltage,positive.SuppliesonlytheanalogportionofADC12.Analogsupplyvoltage,negative.SuppliesonlytheanalogportionofADC12.Digitalsupplyvoltage,positive.Suppliesalldigitalparts.Digitalsupplyvoltage,negative.Suppliesalldigitalparts.
General-purposedigitalI/O/Timer_A,clocksignalTACLKinput/Comparator_Aoutput
General-purposedigitalI/O/Timer_A,capture:CCI0Ainput,compare:Out0output/BSLtransmitGeneral-purposedigitalI/O/Timer_A,capture:CCI1Ainput,compare:Out1outputGeneral-purposedigitalI/O/Timer_A,capture:CCI2Ainput,compare:Out2outputGeneral-purposedigitalI/O/SMCLKsignaloutput
General-purposedigitalI/O/Timer_A,compare:Out0outputGeneral-purposedigitalI/O/Timer_A,compare:Out1outputGeneral-purposedigitalI/O/Timer_A,compare:Out2outputGeneral-purposedigitalI/O/ACLKoutput/Comparator_AinputGeneral-purposedigitalI/O/Timer_A,clocksignalatINCLK
General-purposedigitalI/O/Timer_A,capture:CCI0Binput/Comparator_Aoutput/BSLreceive/Comparator_Ainput
General-purposedigitalI/O/Timer_A,compare:Out1output/Comparator_AinputGeneral-purposedigitalI/O/Timer_A,compare:Out2output/Comparator_Ainput
General-purposedigitalI/O/inputforexternalresistordefiningtheDCOnominalfrequency/Comparator_Ainput
General-purposedigitalI/O/conversionclock-12-bitADC/Comparator_AinputGeneral-purposedigitalI/O/Timer_A,compare:Out0output/Comparator_AinputGeneral-purposedigitalI/O/USCI_B0slavetransmitenable/USCIA0clockinput/output
General-purposedigitalI/O/USCI_B0slavein/masteroutinSPImode,SDAI2CdatainI2CmodeGeneral-purposedigitalI/O/USCI_B0slaveout/masterininSPImode,SCLI2CclockinI2CmodeGeneral-purposedigitalI/O/USCI_B0clockinput/output,USCIA0slavetransmitenable
General-purposedigitalI/O/USCI_A0transmitdataoutputinUARTmode,slavedatain/masteroutinSPImode
General-purposedigitalI/O/USCI_A0receivedatainputinUARTmode,slavedataout/masterininSPImode
General-purposedigitalI/O/USCI_A1transmitdataoutputinUARTmode,slavedatain/masteroutinSPImode
General-purposedigitalI/O/USCI_A1receivedatainputinUARTmode,slavedataout/masterininSPImode
General-purposedigitalI/O/Timer_B,capture:CCI0A/Binput,compare:Out0outputGeneral-purposedigitalI/O/Timer_B,capture:CCI1A/Binput,compare:Out1outputGeneral-purposedigitalI/O/Timer_B,capture:CCI2A/Binput,compare:Out2outputGeneral-purposedigitalI/O/Timer_B,capture:CCI3A/Binput,compare:Out3outputGeneral-purposedigitalI/O/Timer_B,capture:CCI4A/Binput,compare:Out4outputGeneral-purposedigitalI/O/Timer_B,capture:CCI5A/Binput,compare:Out5outputGeneral-purposedigitalI/O/Timer_B,capture:CCI6Ainput,compare:Out6outputGeneral-purposedigitalI/O/Timer_B,clocksignalTBCLKinput
General-purposedigitalI/O/USCI_B1slavetransmitenable/USCI_A1clockinput/output
General-purposedigitalI/O/USCI_B1slavein/masteroutinSPImode,SDAI2CdatainI2CmodeGeneral-purposedigitalI/O/USCI_B1slaveout/masterininSPImode,SCLI2CclockinI2CmodeGeneral-purposedigitalI/O/USCI_B1clockinput/output,USCI_A1slavetransmitenableGeneral-purposedigitalI/O/mainsystemclockMCLKoutputGeneral-purposedigitalI/O/submainsystemclockSMCLKoutputGeneral-purposedigitalI/O/auxiliaryclockACLKoutput
General-purposedigitalI/O/switchallPWMdigitaloutputportstohighimpedance-Timer_BTB0toTB6/SVScomparatoroutputGeneral-purposedigitalI/O
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Table4.TerminalFunctions,MSP430F24x1(continued)
TERMINALNAME
P6.1P6.2P6.3P6.4P6.5P6.6P6.7/SVSINXT2OUTXT2INRST/NMITCKTDI/TCLKTDO/TDITMSDVSSReservedDVSSXINXOUTQFNPad
NO.606123456525358575554561071189NA
I/OI/OI/OI/OI/OI/OI/OI/OOIIIII/OIIOIIONA
General-purposedigitalI/OGeneral-purposedigitalI/OGeneral-purposedigitalI/OGeneral-purposedigitalI/OGeneral-purposedigitalI/OGeneral-purposedigitalI/O
General-purposedigitalI/O/SVSinputOutputterminalofcrystaloscillatorXT2InputportforcrystaloscillatorXT2
Resetinput,nonmaskableinterruptinput,orbootstraploaderstart(inflashdevices).
Testclock(JTAG).TCKistheclockinputfordeviceprogrammingtestandbootstraploaderstart.Testdatainputortestclockinput.ThedeviceprotectionfuseisconnectedtoTDI/TCLK.Testdataoutput.TDO/TDIdataoutputorprogrammingdatainputterminal.Testmodeselect.TMSisusedasaninputportfordeviceprogrammingandtest.ConnectedtoDVSS
Reserved,donotconnectexternallyConnectedtoDVSS
InputforcrystaloscillatorXT1.Standardorwatchcrystalscanbeconnected.OutputforcrystaloscillatorXT1.Standardorwatchcrystalscanbeconnected.QFNpackagepadconnectiontoDVSSrecommended(RGCpackageonly)
DESCRIPTION
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SLAS547H–JUNE2007–REVISEDAUGUST2011
SHORT-FORMDESCRIPTION
CPU
TheMSP430CPUhasa16-bitRISCarchitecturethatishighlytransparenttotheapplication.Alloperations,otherthanprogram-flowinstructions,areperformedasregisteroperationsinconjunctionwithsevenaddressingmodesforsourceoperandandfouraddressingmodesfordestinationoperand.
TheCPUisintegratedwith16registersthatprovidereducedinstructionexecutiontime.Theregister-to-registeroperationexecutiontimeisonecycleoftheCPUclock.
Fouroftheregisters,R0toR3,arededicatedasprogramcounter,stackpointer,statusregister,andconstantgenerator,respectively.Theremainingregistersaregeneral-purposeregisters.
PeripheralsareconnectedtotheCPUusingdata,address,andcontrolbuses,andcanbehandledwithallinstructions.
Program CounterStack PointerStatus RegisterConstant GeneratorGeneral-Purpose RegisterGeneral-Purpose RegisterGeneral-Purpose RegisterGeneral-Purpose RegisterGeneral-Purpose RegisterGeneral-Purpose RegisterGeneral-Purpose RegisterGeneral-Purpose RegisterGeneral-Purpose RegisterGeneral-Purpose RegisterGeneral-Purpose RegisterGeneral-Purpose Register
PC/R0SP/R1SR/CG1/R2CG2/R3R4R5R6R7R8R9R10R11R12R13R14R15
InstructionSet
Theinstructionsetconsistsof51instructionswiththreeformatsandsevenaddressmodes.Eachinstructioncanoperateonwordandbytedata.Table5showsexamplesofthethreetypesofinstructionformats;Table6showstheaddressmodes.
Table5.InstructionWordFormats
INSTRUCTIONFORMAT
Dualoperands,source-destinationSingleoperands,destinationonlyRelativejump,unconditional/conditional
EXAMPLEADDR4,R5CALLR8JNE
OPERATIONR4+R5→R5PC→(TOS),R8→PCJump-on-equalbit=0
Table6.AddressModeDescriptions
ADDRESSMODERegisterIndexed
Symbolic(PCrelative)AbsoluteIndirect
IndirectautoincrementImmediate(1)(2)
S=sourceD=destination
S
(1)
D
(2)
SYNTAXMOVRs,RdMOVX(Rn),Y(Rm)MOVEDE,TONIMOV&MEM,&TCDATMOV@Rn,Y(Rm)MOV@Rn+,RmMOV#X,TONI
EXAMPLEMOVR10,R11MOV2(R5),6(R6)
OPERATIONR10→R11M(2+R5)→M(6+R6)M(EDE)→M(TONI)M(MEM)→M(TCDAT)
✓✓✓✓✓✓✓
✓✓✓✓
MOV@R10,Tab(R6)MOV@R10+,R11MOV#45,TONI
M(R10)→M(Tab+R6)M(R10)→R11R10+2→R10#45→M(TONI)
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OperatingModes
TheMSP430hasoneactivemodeandfivesoftware-selectablelow-powermodesofoperation.Aninterrupteventcanwakeupthedevicefromanyofthefivelow-powermodes,servicetherequest,andrestorebacktothelow-powermodeonreturnfromtheinterruptprogram.
Thefollowingsixoperatingmodescanbeconfiguredbysoftware:•Activemode(AM)
–Allclocksareactive.•Low-powermode0(LPM0)–CPUisdisabled.
–ACLKandSMCLKremainactive.MCLKisdisabled.•Low-powermode1(LPM1)
–CPUisdisabledACLKandSMCLKremainactive.MCLKisdisabled.–DCOdc-generatorisdisabledifDCOnotusedinactivemode.•Low-powermode2(LPM2)–CPUisdisabled.
–MCLKandSMCLKaredisabled.–DCOdc-generatorremainsenabled.–ACLKremainsactive.•Low-powermode3(LPM3)–CPUisdisabled.
–MCLKandSMCLKaredisabled.–DCOdc-generatorisdisabled.–ACLKremainsactive.•Low-powermode4(LPM4)–CPUisdisabled.–ACLKisdisabled.
–MCLKandSMCLKaredisabled.–DCOdc-generatorisdisabled.–Crystaloscillatorisstopped.
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InterruptVectorAddresses
Theinterruptvectorsandthepower-upstartingaddressarelocatedintheaddressrange0xFFFFto0xFFC0.Thevectorcontainsthe16-bitaddressoftheappropriateinterrupt-handlerinstructionsequence.Iftheresetvector(0xFFFE)contains0xFFFF(forexample,ifflashisnotprogrammed)theCPUentersLPM4afterpower-up.
Table7.InterruptVectorAddresses
INTERRUPTSOURCEPower-upExternalresetWatchdogFlashkeyviolationPCoutofrange(1)
NMI
Oscillatorfault
Flashmemoryaccessviolation
Timer_B7(4)Timer_B7(4)Comparator_A+Watchdogtimer+
Timer_A3Timer_A3
USCI_A0/USCI_B0receive
USCI_B0I2CstatusUSCI_A0/USCI_B0transmitUSCI_B0I2Creceive/transmit
ADC12(8)
I/OportP2(eightflags)I/OportP1(eightflags)USCI_A1/USCI_B1receive
USCI_B1I2CstatusUSCI_A1/USCI_B1transmitUSCI_B1I2Creceive/transmit
Reserved(9)(10)
(1)
INTERRUPTFLAG
PORIFGWDTIFGRSTIFGKEYV(see(2))NMIIFGOFIFGACCVIFG(2)(3)TBCCR0CCIFG(5)
TBCCR1toTBCCR6CCIFGs,
TBIFG(2)(5)
CAIFGWDTIFGTACCR0CCIFG(5)TACCR1CCIFG
TACCR2CCIFGTAIFG(2)(5)UCA0RXIFG,UCB0RXIFG(2)(6)UCA0TXIFG,UCB0TXIFG(2)(7)
ADC12IFG(2)(5)P2IFG.0toP2IFG.7P1IFG.0toP1IFG.7
(2)(5)(2)(5)
SYSTEMINTERRUPTWORDADDRESSPRIORITY
Reset0xFFFE31,highest
(Non)maskable(Non)maskable(Non)maskableMaskableMaskableMaskableMaskableMaskableMaskableMaskableMaskableMaskableMaskableMaskableMaskableMaskable
0xFFFC0xFFFA0xFFF80xFFF60xFFF40xFFF20xFFF00xFFEE0xFFEC0xFFEA0xFFE80xFFE60xFFE40xFFE20xFFE00xFFDEto0xFFC0
30292827262524232221201918171615to0,lowest
UCA1RXIFG,UCB1RXIFG(2)(6)UCA1TXIFG,UCB1TXIFG(2)(7)
Reserved
AresetisgeneratediftheCPUtriestofetchinstructionsfromwithinthemoduleregistermemoryaddressrange(0x0000to0x01FF)orfromwithinunusedaddressrange.(2)Multiplesourceflags
(3)(Non)maskable:Theindividualinterrupt-enablebitcandisableaninterruptevent,butthegeneral-interruptenablecannot.
(4)Timer_B7inMSP430F24x(1)/MSP430F2410familyhassevenCCRs,Timer_B3inMSP430F23xfamilyhasthreeCCRs.InTimer_B3,
thereareonlyinterruptflagsTBCCR0CCIFG,TBCCR1CCIFG,andTBCCR2CCIFG,andtheinterruptenablebitsTBCCTL0CCIE,TBCCTL1CCIE,andTBCCTL2CCIE.(5)Interruptflagsarelocatedinthemodule.
(6)InSPImode:UCB0RXIFG.InI2Cmode:UCALIFG,UCNACKIFG,ICSTTIFG,UCSTPIFG.(7)InUART/SPImode:UCB0TXIFG.InI2Cmode:UCB0RXIFG,UCB0TXIFG.(8)ADC12isnotimplementedintheMSP430F24x1family.
(9)Theaddress0xFFDEisusedasbootstraploadersecuritykey(BSLSKEY).A0xAA55atthislocationdisablestheBSLcompletely.A
zerodisablestheerasureoftheflashifaninvalidpasswordissupplied.
(10)Theinterruptvectorsataddresses0xFFDEto0xFFC0arenotusedinthisdeviceandcanbeusedforregularprogramcodeif
necessary.
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SpecialFunctionRegisters
Mostinterruptenablebitsarecollectedinthelowestaddressspace.Special-functionregisterbitsnotallocatedtoafunctionalpurposearenotphysicallypresentinthedevice.Thisarrangementprovidessimplesoftwareaccess.
Legend
rw
rw-0,1rw-(0),(1)
Bitcanbereadandwritten.
Bitcanbereadandwritten.ItisResetorSetbyPUC.Bitcanbereadandwritten.ItisResetorSetbyPOR.SFRbitisnotpresentindevice.
Table8.InterruptEnable1
Address00h
7
6
5ACCVIErw-0
WDTIEOFIENMIIEACCVIE
4NMIIErw-0
3
2
1OFIErw-0
0WDTIErw-0
Watchdogtimerinterruptenable.Inactiveifwatchdogmodeisselected.Activeifwatchdogtimerisconfiguredinintervaltimermode.
Oscillatorfaultinterruptenable(Non)maskableinterruptenable
Flashaccessviolationinterruptenable
Table9.InterruptEnable2
Address01h
7
6
5
4
3UCB0TXIE
rw-0
UCA0RXIEUCA0TXIEUCB0RXIEUCB0TXIE
USCI_A0receive-interruptenableUSCI_A0transmit-interruptenableUSCI_B0receive-interruptenableUSCI_B0transmit-interruptenable
2UCB0RXIE
rw-0
1UCA0TXIE
rw-0
0UCA0RXIE
rw-0
Table10.InterruptFlagRegister1
Address02h
7
6
5
4NMIIFGrw-0
WDTIFGOFIFGRSTIFGPORIFGNMIIFG
3RSTIFGrw-(0)
2PORIFGrw-(1)
1OFIFGrw-1
0WDTIFGrw-(0)
Setonwatchdogtimeroverflow(inwatchdogmode)orsecuritykeyviolation.ResetonVCCpower-uporaresetconditionatRST/NMIpininresetmode.Flagsetonoscillatorfault
Externalresetinterruptflag.SetonaresetconditionatRST/NMIpininresetmode.ResetonVCCpowerup.Power-onresetinterruptflag.SetonVCCpowerup.SetviaRST/NMIpin
Table11.InterruptFlagRegister2
Address03h
7
6
5
4
3UCB0TXIFG
rw-1
UCA0RXIFGUCA0TXIFGUCB0RXIFGUCB0TXIFG
USCI_A0receive-interruptflagUSCI_A0transmit-interruptflagUSCI_B0receive-interruptflagUSCI_B0transmit-interruptflag
2UCB0RXIFG
rw-0
1UCA0TXIFG
rw-1
0UCA0RXIFG
rw-0
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MemoryOrganization
Table12.MemoryOrganization
MSP430F233
Memory
Main:interruptvectorMain:codememoryRAM(Total)InformationmemoryBootmemoryRAMPeripherals
SizeFlashFlashSizeSizeFlashSizeROMSize16bit8bitSFR
8KB
0xFFFFto0xFFC00xFFFFto0xE0001KB
0x05FFto0x0200256Byte
0x10FFto0x10001KB
0x0FFFto0x0C001KB
0x05FFto0x02000x01FFto0x01000x00FFto0x00100x000Fto0x0000MSP430F247MSP430F2471
Memory
Main:interruptvectorMain:codememoryRAM(total)ExtendedMirrored
InformationmemoryBootmemoryRAM(mirroredat0x18FFto0x1100)Peripherals
SizeFlashFlashSizeSizeSizeSizeFlashSizeROMSize16bit8bitSFR
32KB
0xFFFFto0xFFC00xFFFFto0x80004KB
0x20FFto0x11002KB
0x20FFto0x19002KB
0x18FFto0x1100256Byte
0x10FFto0x10001KB
0x0FFFto0x0C002KB
0x09FFto0x02000x01FFto0x01000x00FFto0x00100x000Fto0x0000
MSP430F23516KB
0xFFFFto0xFFC00xFFFFto0xC0002KB
0x09FFto0x0200256Byte
0x10FFto0x10001KB
0x0FFFto0x0C002KB
0x09FFto0x02000x01FFto0x01000x00FFto0x00100x000Fto0x0000MSP430F248MSP430F248148KB
0xFFFFto0xFFC00xFFFFto0x40004KB
0x20FFto0x11002KB
0x20FFto0x19002KB
0x18FFto0x1100256Byte
0x10FFto0x10001KB
0x0FFFto0x0C002KB
0x09FFto0x02000x01FFto0x01000x00FFto0x00100x000Fto0x0000
MSP430F249MSP430F249160KB
0xFFFFto0xFFC00xFFFFto0x11002KB
0x09FFto0x0200256Byte
0x10FFto0x10001KB
0x0FFFto0x0C002KB
0x09FFto0x02000x01FFto0x01000x00FFto0x00100x000Fto0x0000
MSP430F241056KB
0xFFFFto0xFFC00xFFFFto0x21004KB
0x20FFto0x11002KB
0x20FFto0x19002KB
0x18FFto0x1100256Byte
0x10FFto0x10001KB
0x0FFFto0x0C002KB
0x09FFto0x02000x01FFto0x01000x00FFto0x00100x000Fto0x0000
BootstrapLoader(BSL)
TheMSP430bootstraploader(BSL)enablesuserstoprogramtheflashmemoryorRAMusingaUARTserialinterface.AccesstotheMSP430memoryviatheBSLisprotectedbyuser-definedpassword.ForcompletedescriptionofthefeaturesoftheBSLanditsimplementation,seetheMSP430ProgrammingViatheBootstrapLoaderUser’sGuide(SLAU319).
Table13.BSLFunctionPins
BSLFUNCTIONDatatransmitDatareceive
PM,RGCPACKAGEPINS
13-P1.122-P2.2
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FlashMemory
TheflashmemorycanbeprogrammedviatheJTAGport,thebootstraploader,orin-systembytheCPU.TheCPUcanperformsingle-byteandsingle-wordwritestotheflashmemory.Featuresoftheflashmemoryinclude:•Flashmemoryhasnsegmentsofmainmemoryandfoursegmentsofinformationmemory(AtoD)of64byteseach.Eachsegmentinmainmemoryis512bytesinsize.
•Segments0tonmaybeerasedinonestep,oreachsegmentmaybeindividuallyerased.•SegmentsAtoDcanbeerasedindividually,orasagroupwithsegments0ton.SegmentsAtoDarealsocalledinformationmemory.
•SegmentAcontainscalibrationdata.Afterreset,segmentAisprotectedagainstprogramminganderasing.Itcanbeunlocked,butcareshouldbetakennottoerasethissegmentifthedevice-specificcalibrationdataisrequired.
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Peripherals
PeripheralsareconnectedtotheCPUthroughdata,address,andcontrolbusesandcanbehandledusingallinstructions.Forcompletemoduledescriptions,seetheMSP430x2xxFamilyUser'sGuide(SLAU144).
OscillatorandSystemClock
Theclocksystemissupportedbythebasicclockmodulethatincludessupportfora32768-Hzwatchcrystaloscillator,aninternalvery-low-powerlow-frequencyoscillator,aninternaldigitally-controlledoscillator(DCO),andahigh-frequencycrystaloscillator.Thebasicclockmoduleisdesignedtomeettherequirementsofbothlowsystemcostandlowpowerconsumption.TheinternalDCOprovidesafastturn-onclocksourceandstabilizesinlessthan1µs.Thebasicclockmoduleprovidesthefollowingclocksignals:
•Auxiliaryclock(ACLK),sourcedfroma32768-Hzwatchcrystal,ahigh-frequencycrystal,ortheinternalvery-low-powerLFoscillator.
•Mainclock(MCLK),thesystemclockusedbytheCPU.
•Sub-Mainclock(SMCLK),thesub-systemclockusedbytheperipheralmodules.
CalibrationDataStoredinInformationMemorySegmentA
CalibrationdataisstoredfortheDCOandfortheADC12.Itisorganizedinatag-length-value(TLV)structure.
Table14.TagsUsedbytheADCCalibrationTags
NAME
TAG_DCO_30TAG_ADC12_1TAG_EMPTY
ADDRESS0x10F60x10DA
-VALUE0x010x100xFE
ADC12_1calibrationtag
Identifierforemptymemoryareas
DESCRIPTION
DCOfrequencycalibrationatVCC=3VandTA=25°Catcalibration
Table15.LabelsUsedbytheADCCalibrationTags
LABEL
CAL_ADC_25T85CAL_ADC_25T30
CAL_ADC_25VREF_FACTORCAL_ADC_15T85CAL_ADC_15T30
CAL_ADC_15VREF_FACTORCAL_ADC_OFFSETCAL_ADC_GAIN_FACTORCAL_BC1_1MHZCAL_DCO_1MHZCAL_BC1_8MHZCAL_DCO_8MHZCAL_BC1_12MHZCAL_DCO_12MHZCAL_BC1_16MHZCAL_DCO_16MHZ
CONDITIONATCALIBRATION/DESCRIPTIONINCHx=0x1010,REF2_5=1,TA=85°CINCHx=0x1010,REF2_5=1,TA=30°CREF2_5=1,TA=30°C,IVREF+=1.0mAINCHx=0x1010,REF2_5=0,TA=85°CINCHx=0x1010,REF2_5=0,TA=30°CREF2_5=0,TA=30°C,IVREF+=0.5mAExternalVref=1.5V,fADC12CLK=5MHzExternalVref=1.5V,fADC12CLK=5MHz--------SIZEwordwordwordwordwordwordwordwordbytebytebytebytebytebytebytebyte
ADDRESSOFFSET
0x000E0x000C0x000A0x00080x00060x00040x00020x00000x00070x00060x00050x00040x00030x00020x00010x0000
Brownout,SupplyVoltageSupervisor(SVS)
Thebrownoutcircuitisimplementedtoprovidetheproperinternalresetsignaltothedeviceduringpoweronandpoweroff.TheSVScircuitrydetectsifthesupplyvoltagedropsbelowauser-selectablelevelandsupportsbothsupplyvoltagesupervision(thedeviceisautomaticallyreset)andsupplyvoltagemonitoring(SVM,thedeviceisnotautomaticallyreset).
TheCPUbeginscodeexecutionafterthebrownoutcircuitreleasesthedevicereset.However,VCCmaynothaverampedtoVCC(min)atthattime.TheusermustensurethatthedefaultDCOsettingsarenotchangeduntilVCCreachesVCC(min).Ifdesired,theSVScircuitcanbeusedtodeterminewhenVCCreachesVCC(min).
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DigitalI/O
Thereareuptosix8-bitI/Oportsimplemented—portsP1throughP6:•AllindividualI/Obitsareindependentlyprogrammable.
•Anycombinationofinput,output,andinterruptconditionispossible.
•Edge-selectableinterruptinputcapabilityforalleightbitsofportP1andP2.•Read/writeaccesstoport-controlregistersissupportedbyallinstructions.•EachI/Ohasanindividuallyprogrammablepullup/pulldownresistor.
WatchdogTimer(WDT+)
TheprimaryfunctionoftheWDT+moduleistoperformacontrolledsystemrestartafterasoftwareproblemoccurs.Iftheselectedtimeintervalexpires,asystemresetisgenerated.Ifthewatchdogfunctionisnotneededinanapplication,themodulecanbedisabledorconfiguredasanintervaltimerandcangenerateinterruptsatselectedtimeintervals.
HardwareMultiplier
Themultiplicationoperationissupportedbyadedicatedperipheralmodule.Themoduleperforms16x16,16x8,8x16,and8x8bitoperations.Themoduleiscapableofsupportingsignedandunsignedmultiplicationaswellassignedandunsignedmultiplyandaccumulateoperations.Theresultofanoperationcanbeaccessedimmediatelyaftertheoperandshavebeenloadedintotheperipheralregisters.Noadditionalclockcyclesarerequired.
Timer_A3
Timer_A3isa16-bittimer/counterwiththreecapture/compareregisters.Timer_A3cansupportmultiplecapture/compares,PWMoutputs,andintervaltiming.Timer_A3alsohasextensiveinterruptcapabilities.Interruptsmaybegeneratedfromthecounteronoverflowconditionsandfromeachofthecapture/compareregisters.
Table16.Timer_A3SignalConnections
INPUTPINNUMBER
12-P1.0
DEVICEINPUT
SIGNAL
TACLKACLKSMCLK
21-P2.113-P1.122-P2.2
TAINCLKTA0TA0DVSSDVCC
14-P1.2
TA1CAOUT(internal)
DVSSDVCC
15-P1.3
TA2ACLK(internal)
DVSSDVCC
(1)
NotavailableintheMSP430F24x1devices.
MODULEINPUT
NAME
TACLKACLKSMCLKINCLKCCI0ACCI0BGNDVCCCCI1ACCI1BGNDVCCCCI2ACCI2BGNDVCC
CCR2
TA2
CCR1
TA1
14-P1.218-P1.623-P2.3ADC12(1)(internal)
15-P1.319-P1.724-P2.4
CCR0
TA0
13-P1.117-P1.527-P2.7
Timer
NA
MODULEBLOCK
MODULEOUTPUT
SIGNAL
OUTPUTPINNUMBER
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Timer_B7(MSP430F24x(1)andMSP430F2410Devices)
Timer_B7isa16-bittimer/counterwithsevencapture/compareregisters.Timer_B7cansupportmultiplecapture/compares,PWMoutputs,andintervaltiming.Timer_B7alsohasextensiveinterruptcapabilities.Interruptsmaybegeneratedfromthecounteronoverflowconditionsandfromeachofthecapture/compareregisters.
Table17.Timer_B7SignalConnections
INPUTPINNUMBER
43-P4.7
DEVICEINPUT
SIGNAL
TBCLKACLKSMCLK
43-P4.736-P4.036-P4.0
TBCLKTB0TB0DVSSDVCC
37-P4.137-P4.1
TB1TB1DVSSDVCC
38-P4.238-P4.2
TB2TB2DVSSDVCC
39-P4.339-P4.3
TB3TB3DVSSDVCC
40-P4.440-P4.4
TB4TB4DVSSDVCC
41-P4.541-P4.5
TB5TB5DVSSDVCC
42-P4.6
TB6ACLK(internal)
DVSSDVCC
(1)(2)
NotavailableintheMSP430F24x1devices.NotavailableintheMSP430F24x1devices.
MODULEINPUT
NAME
TBCLKACLKSMCLKINCLKCCI0ACCI0BGNDVCCCCI1ACCI1BGNDVCCCCI2ACCI2BGNDVCCCCI3ACCI3BGNDVCCCCI4ACCI4BGNDVCCCCI5ACCI5BGNDVCCCCI6ACCI6BGNDVCC
CCR6
TB6
42-P4.6
CCR5
TB5
41-P4.5
CCR4
TB4
40-P4.4
CCR3
TB3
39-P4.3
CCR2
TB2
38-P4.2
CCR1
TB1
37-P4.1ADC12(2)(internal)
CCR0
TB0
36-P4.0ADC12(1)(internal)
Timer
NA
MODULEBLOCK
MODULEOUTPUT
SIGNAL
OUTPUTPINNUMBER
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Timer_B3(MSP430F23xDevices)
Timer_B3isa16-bittimer/counterwithsevencapture/compareregisters.Timer_B3cansupportmultiplecapture/compares,PWMoutputs,andintervaltiming.Timer_B3alsohasextensiveinterruptcapabilities.Interruptsmaybegeneratedfromthecounteronoverflowconditionsandfromeachofthecapture/compareregisters.
Table18.Timer_B3SignalConnections
INPUTPINNUMBER
43-P4.7
DEVICEINPUT
SIGNAL
TBCLKACLKSMCLK
43-P4.736-P4.036-P4.0
TBCLKTB0TB0DVSSDVCC
37-P4.137-P4.1
TB1TB1DVSSDVCC
38-P4.238-P4.2
TB2TB2DVSSDVCC
MODULEINPUT
NAME
TBCLKACLKSMCLKINCLKCCI0ACCI0BGNDVCCCCI1ACCI1BGNDVCCCCI2ACCI2BGNDVCC
CCR2
TB2
38-P4.2
CCR1
TB1
37-P4.1ADC12(internal)
CCR0
TB0
36-P4.0ADC12(internal)
Timer
NA
MODULEBLOCK
MODULEOUTPUT
SIGNAL
OUTPUTPINNUMBER
UniversalSerialCommunicationsInterface(USCI)
TheUSCImodulesareusedforserialdatacommunication.TheUSCImodulesupportssynchronouscommunicationprotocols,suchasSPI(3or4pin)orI2C,andasynchronouscombinationprotocols,suchasUART,enhancedUARTwithautomaticbaudratedetection(LIN),andIrDA.
TheUSCIAmoduleprovidessupportforSPI(3or4pin),UART,enhancedUART,andIrDA.TheUSCIBmoduleprovidessupportforSPI(3or4pin)andI2C.
Comparator_A+
Theprimaryfunctionofthecomparator_A+moduleistosupportprecisionslopeanalog-to-digitalconversions,battery-voltagesupervision,andmonitoringofexternalanalogsignals.
ADC12(MSP430F23x,MSP430F24x,andMSP430F2410Devices)
TheADC12modulesupportsfast,12-bitanalog-to-digitalconversions.Themoduleimplementsa12-bitSARcore,sampleselectcontrol,referencegenerator,anda16-wordconversion-and-controlbuffer.Theconversion-and-controlbufferallowsupto16independentADCsamplestobeconvertedandstoredwithoutanyCPUintervention.
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PeripheralFileMap
Table19.PeripheralFileMap
MODULE
ADC12
(MSP430F24x,
MSP430F2410,andMSP430F23x)
Interrupt-enableregisterInterrupt-flagregisterControlregister1Controlregister0Conversionmemory15Conversionmemory14Conversionmemory13Conversionmemory12Conversionmemory11Conversionmemory10Conversionmemory9Conversionmemory8Conversionmemory7Conversionmemory6Conversionmemory5Conversionmemory4Conversionmemory3Conversionmemory2Conversionmemory1Conversionmemory0
ADCmemory-controlregister15ADCmemory-controlregister14ADCmemory-controlregister13ADCmemory-controlregister12ADCmemory-controlregister11ADCmemory-controlregister10ADCmemory-controlregister9ADCmemory-controlregister8ADCmemory-controlregister7ADCmemory-controlregister6ADCmemory-controlregister5ADCmemory-controlregister4ADCmemory-controlregister3ADCmemory-controlregister2ADCmemory-controlregister1ADCmemory-controlregister0
REGISTERNAME
Interrupt-vector-wordregister
SHORTFORMADC12IVADC12IEADC12IFGADC12CTL1ADC12CTL0ADC12MEM15ADC12MEM14ADC12MEM13ADC12MEM12ADC12MEM11ADC12MEM10ADC12MEM9ADC12MEM8ADC12MEM7ADC12MEM6ADC12MEM5ADC12MEM4ADC12MEM3ADC12MEM2ADC12MEM1ADC12MEM0ADC12MCTL15ADC12MCTL14ADC12MCTL13ADC12MCTL12ADC12MCTL11ADC12MCTL10ADC12MCTL9ADC12MCTL8ADC12MCTL7ADC12MCTL6ADC12MCTL5ADC12MCTL4ADC12MCTL3ADC12MCTL2ADC12MCTL1ADC12MCTL0
ADDRESS0x01A80x01A60x01A40x01A20x01A00x015E0x015C0x015A0x01580x01560x01540x01520x01500x014E0x014C0x014A0x01480x01460x01440x01420x01400x008F0x008E0x008D0x008C0x008B0x008A0x00890x00880x00870x00860x00850x00840x00830x00820x00810x0080
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Table19.PeripheralFileMap(continued)
MODULE
Timer_B7
(MSP430F24x(1)andMSP430F2410)
REGISTERNAME
Capture/compareregister6Capture/compareregister5Capture/compareregister4Capture/compareregister3Capture/compareregister2Capture/compareregister1Capture/compareregister0Timer_Bregister
Capture/comparecontrol6Capture/comparecontrol5Capture/comparecontrol4Capture/comparecontrol3Capture/comparecontrol2Capture/comparecontrol1Capture/comparecontrol0Timer_BcontrolTimer_Binterruptvector
Timer_B3
(MSP430F23x)
Capture/compareregister2Capture/compareregister1Capture/compareregister0Timer_Bregister
Capture/comparecontrol2Capture/comparecontrol1Capture/comparecontrol0Timer_BcontrolTimer_Binterruptvector
Timer_A3
Capture/compareregister2Capture/compareregister1Capture/compareregister0Timer_AregisterReservedReservedReservedReserved
Capture/comparecontrol2Capture/comparecontrol1Capture/comparecontrol0Timer_AcontrolTimer_Ainterruptvector
HardwareMultiplier
SumextendResulthighwordResultlowwordSecondoperand
Multiplysigned+accumulate/operand1Multiply+accumulate/operand1Multiplysigned/operand1Multiplyunsigned/operand1
26
TACCTL2TACCTL1TACCTL0TACTLTAIVSUMEXTRESHIRESLOOP2MACSMACMPYSMPY
SHORTFORMTBCCR6TBCCR5TBCCR4TBCCR3TBCCR2TBCCR1TBCCR0TBRTBCCTL6TBCCTL5TBCCTL4TBCCTL3TBCCTL2TBCCTL1TBCCTL0TBCTLTBIVTBCCR2TBCCR1TBCCR0TBRTBCCTL2TBCCTL1TBCCTL0TBCTLTBIVTACCR2TACCR1TACCR0TAR
ADDRESS0x019E0x019C0x019A0x01980x01960x01940x01920x01900x018E0x018C0x018A0x01880x01860x01840x01820x01800x011E0x01960x01940x01920x01900x01860x01840x01820x01800x011E0x01760x01740x01720x01700x016E0x016C0x016A0x01680x01660x01640x01620x01600x012E0x013E0x013C0x013A0x01380x01360x01340x01320x0130
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Table19.PeripheralFileMap(continued)
MODULE
Flash
Flashcontrol4Flashcontrol3Flashcontrol2Flashcontrol1
WatchdogUSCIA0/B0
WatchdogTimercontrolUSCIA0autobaudratecontrolUSCIA0transmitbufferUSCIA0receivebufferUSCIA0status
USCIA0modulationcontrolUSCIA0baudratecontrol1USCIA0baudratecontrol0USCIA0control1USCIA0control0
USCIA0IrDAreceivecontrolUSCIA0IrDAtransmitcontrolUSCIB0transmitbufferUSCIB0receivebufferUSCIB0status
USCIB0I2CInterruptenableUSCIB0baudratecontrol1USCIB0baudratecontrol0USCIB0control1USCIB0control0
USCIB0I2CslaveaddressUSCIB0I2Cownaddress
REGISTERNAME
SHORTFORMFCTL4FCTL3FCTL2FCTL1WDTCTLUCA0ABCTLUCA0TXBUFUCA0RXBUFUCA0STATUCA0MCTLUCA0BR1UCA0BR0UCA0CTL1UCA0CTL0UCA0IRRCTLUCA0IRTCLTUCB0TXBUFUCB0RXBUFUCB0STATUCB0CIEUCB0BR1UCB0BR0UCB0CTL1UCB0CTL0UCB0SAUCB0OA
ADDRESS0x01BE0x012C0x012A0x01280x01200x005D0x00670x00660x00650x00640x00630x00620x00610x00600x005F0x005E0x006F0x006E0x006D0x006C0x006B0x006A0x00690x00680x011A0x0118
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Table19.PeripheralFileMap(continued)
MODULE
USCIA1/B1
(MSP430F24x(1)andMSP430F2410)
USCIA1transmitbufferUSCIA1receivebufferUSCIA1status
USCIA1modulationcontrolUSCIA1baudratecontrol1USCIA1baudratecontrol0USCIA1control1USCIA1control0
USCIA1IrDAreceivecontrolUSCIA1IrDAtransmitcontrolUSCIB1transmitbufferUSCIB1receivebufferUSCIB1status
USCIB1I2CInterruptenableUSCIB1baudratecontrol1USCIB1baudratecontrol0USCIB1control1USCIB1control0
USCIB1I2CslaveaddressUSCIB1I2CownaddressUSCIA1/B1interruptenableUSCIA1/B1interruptflag
Comparator_A+
Comparator_AportdisableComparator_Acontrol2Comparator_Acontrol1
BasicClock
Basicclocksystemcontrol3Basicclocksystemcontrol2Basicclocksystemcontrol1DCOclockfrequencycontrol
Brownout,SVSPortP6
SVScontrolregister(resetbybrownoutsignal)PortP6resistorenablePortP6selectionPortP6directionPortP6outputPortP6input
PortP5
PortP5resistorenablePortP5selectionPortP5directionPortP5outputPortP5input
PortP4
PortP4resistorenablePortP4selectionPortP4directionPortP4outputPortP4input
REGISTERNAME
USCIA1autobaudratecontrol
SHORTFORMUCA1ABCTLUCA1TXBUFUCA1RXBUFUCA1STATUCA1MCTLUCA1BR1UCA1BR0UCA1CTL1UCA1CTL0UCA1IRRCTLUCA1IRTCLTUCB1TXBUFUCB1RXBUFUCB1STATUCB1CIEUCB1BR1UCB1BR0UCB1CTL1UCB1CTL0UCB1SAUCB1OAUC1IEUC1IFGCAPDCACTL2CACTL1BCSCTL3BCSCTL2BCSCTL1DCOCTLSVSCTLP6RENP6SELP6DIRP6OUTP6INP5RENP5SELP5DIRP5OUTP5INP4RENP4SELP4DIRP4OUTP4IN
ADDRESS0x00CD0x00D70x00D60x00D50x00D40x00D30x00D20x00D10x00D00x00CF0x00CE0x00DF0x00DE0x00DD0x00DC0x00DB0x00DA0x00D90x00D80x017E0x017C0x00060x00070x005B0x005A0x00590x00530x00580x00570x00560x00550x00130x00370x00360x00350x00340x00120x00330x00320x00310x00300x00110x001F0x001E0x001D0x001C
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Table19.PeripheralFileMap(continued)
MODULE
PortP3
PortP3resistorenablePortP3selectionPortP3directionPortP3outputPortP3input
PortP2
PortP2resistorenablePortP2selectionPortP2interruptenablePortP2interrupt-edgeselectPortP2interruptflagPortP2directionPortP2outputPortP2input
PortP1
PortP1resistorenablePortP1selectionPortP1interruptenablePortP1interrupt-edgeselectPortP1interruptflagPortP1directionPortP1outputPortP1input
SpecialFunctions
SFRinterruptflag2SFRinterruptflag1SFRinterruptenable2SFRinterruptenable1
REGISTERNAME
SHORTFORMP3RENP3SELP3DIRP3OUTP3INP2RENP2SELP2IEP2IESP2IFGP2DIRP2OUTP2INP1RENP1SELP1IEP1IESP1IFGP1DIRP1OUTP1INIFG2IFG1IE2IE1
ADDRESS0x00100x001B0x001A0x00190x00180x002F0x002E0x002D0x002C0x002B0x002A0x00290x00280x00270x00260x00250x00240x00230x00220x00210x00200x00030x00020x00010x0000
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AbsoluteMaximumRatings(1)
VoltageappliedatVCCtoVSSVoltageappliedtoanypin
(2)
-0.3Vto4.1V-0.3VtoVCC+0.3V
±2mA
UnprogrammeddeviceProgrammeddevice
-55°Cto150°C-55°Cto150°C
DiodecurrentatanydeviceterminalStoragetemperature,Tstg(1)(2)(3)
(3)
Stressesbeyondthoselistedunderabsolutemaximumratingsmaycausepermanentdamagetothedevice.Thesearestressratingsonly,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderrecommendedoperatingconditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability.
AllvoltagesreferencedtoVSS.TheJTAGfuse-blowvoltage,VFB,isallowedtoexceedtheabsolutemaximumrating.ThevoltageisappliedtotheTESTpinwhenblowingtheJTAGfuse.
HighertemperaturemaybeappliedduringboardsolderingprocessaccordingtothecurrentJEDECJ-STD-020specificationwithpeakreflowtemperaturesnothigherthanclassifiedonthedevicelabelontheshippingboxesorreels.
RecommendedOperatingConditions(1)(2)
MIN
(3)
NOMMAX3.63.6
UNITVVV
VCCVSSTA
Supplyvoltage
AVCC=DVCC=VCCAVSS=DVSS=VSS
Duringprogramexecution
Duringprogram/eraseflashmemoryIversionTversion
1.82.2
0
-40-40dcdcdc
Supplyvoltage
Operatingfree-airtemperatureProcessorfrequency
(maximumMCLKfrequency)(1)(2)(seeFigure1)
851054.151216
°C
VCC=1.8V,Dutycycle=50%±10%VCC=2.7V,Dutycycle=50%±10%VCC≥3.3V,Dutycycle=50%±10%
fSYSTEM
MHz
(1)(2)(3)
TheMSP430CPUisclockeddirectlywithMCLK.BoththehighandlowphaseofMCLKmustnotexceedthepulsewidthofthespecifiedmaximumfrequency.
Modulesmighthaveadifferentmaximuminputclockspecification.Seethespecificationoftherespectivemoduleinthisdatasheet.ItisrecommendedtopowerAVCCandDVCCfromthesamesource.Amaximumdifferenceof0.3VbetweenAVCCandDVCCcanbetoleratedduringpower-up.
Legend:16MHzSystemFrequency−MHzSupply voltage rangeduring flash memoryprogramming
12MHzSupply voltage rangeduring program execution
7.5MHz4.15MHz1.8V2.2V2.7V3.3V3.6VSupply Voltage−V
NOTE:Minimumprocessorfrequencyisdefinedbysystemclock.FlashprogramoreraseoperationsrequireaminimumVCC
of2.2V.
Figure1.OperatingArea
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ActiveModeSupplyCurrent(IntoDVCC+AVCC)ExcludingExternalCurrent(1)(2)
overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)
PARAMETER
TESTCONDITIONS
fDCO=fMCLK=fSMCLK=1MHz,fACLK=32768Hz,
Programexecutesinflash,BCSCTL1=CALBC1_1MHZ,DCOCTL=CALDCO_1MHZ,
CPUOFF=0,SCG0=0,SCG1=0,OSCOFF=0
fDCO=fMCLK=fSMCLK=1MHz,fACLK=32768Hz,
ProgramexecutesinRAM,BCSCTL1=CALBC1_1MHZ,DCOCTL=CALDCO_1MHZ,
CPUOFF=0,SCG0=0,SCG1=0,OSCOFF=0
fMCLK=fSMCLK=fACLK=32768Hz/8=4096Hz,fDCO=0Hz,
Programexecutesinflash,SELMx=11,SELS=1,
DIVMx=DIVSx=DIVAx=11,
CPUOFF=0,SCG0=1,SCG1=0,OSCOFF=0
fMCLK=fSMCLK=fDCO(0,0)≈100kHz,fACLK=0Hz,
Programexecutesinflash,
RSELx=0,DCOx=0,CPUOFF=0,SCG0=0,SCG1=0,OSCOFF=1
TA
-40°Cto85°C
105°C-40°Cto85°C
105°C-40°Cto85°C
105°C-40°Cto85°C
105°C-40°Cto85°C
105°C-40°Cto85°C
105°C-40°Cto85°C
105°C-40°Cto85°C
105°C
3V3.3V3VVCC2.2V
MIN
TYP2752953864172302483213441.562755706784
MAX3123184454492612673663703.810.54.712.2728189100
µAµAµAµAUNIT
IAM,1MHz
Activemode(AM)current(1MHz)
2.2V
IAM,1MHz
Activemode(AM)current(1MHz)
2.2V
IAM,4kHz
Activemode(AM)current(4kHz)
2.2V3V
IAM,100kHz
Activemode(AM)current(100kHz)
(1)(2)
Allinputsaretiedto0VorVCC.Outputsdonotsourceorsinkanycurrent.
ThecurrentsarecharacterizedwithaMicroCrystalCC4V-T1ASMDcrystalwithaloadcapacitanceof9pF.Theinternalandexternalloadcapacitanceischosentocloselymatchtherequired9pF.
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TypicalCharacteristics-Active-ModeSupplyCurrent(IntoDVCC+AVCC)
ACTIVE-MODECURRENT
vs
SUPPLYVOLTAGE
TA=25°C
8.07.0Active Mode Current−mA6.0
fDCO= 12 MHz5.04.03.02.01.00.01.5
fDCO= 1 MHz0.00.0
fDCO= 8 MHzfDCO= 16 MHz4.0Active Mode Current−mA5.0
TA= 85°CTA= 25°CACTIVE-MODECURRENT
vs
DCOFREQUENCY
3.0
VCC= 3 V2.0
TA= 85°CTA= 25°C1.0
VCC= 2.2 V2.02.53.03.54.04.08.012.016.0
VCC−Supply Voltage−VfDCO−DCO Frequency−MHz
Figure2.Figure3.
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Low-Power-ModeSupplyCurrents(IntoVCC)ExcludingExternalCurrent(1)(2)
overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)
PARAMETER
TESTCONDITIONS
fMCLK=0MHz,
fSMCLK=fDCO=1MHz,fACLK=32768Hz,
BCSCTL1=CALBC1_1MHZ,DCOCTL=CALDCO_1MHZ,
CPUOFF=1,SCG0=0,SCG1=0,OSCOFF=0
fMCLK=0MHz,
fSMCLK=fDCO(0,0)≈100kHz,fACLK=0Hz,
RSELx=0,DCOx=0,
CPUOFF=1,SCG0=0,SCG1=0,OSCOFF=1
fMCLK=fSMCLK=0MHz,fDCO=1MHz,fACLK=32768Hz,
BCSCTL1=CALBC1_1MHZ,DCOCTL=CALDCO_1MHZ,
CPUOFF=1,SCG0=0,SCG1=1,OSCOFF=0
TA
-40°Cto85°C
105°C-40°Cto85°C
105°C-40°Cto85°C
105°C-40°Cto85°C
105°C-40°Cto85°C
105°C-40°Cto85°C
105°C-40°C25°C
Low-powermode3(LPM3)current(4)
fDCO=fMCLK=fSMCLK=0MHz,fACLK=32768Hz,
CPUOFF=1,SCG0=1,SCG1=1,OSCOFF=0
85°C105°C-40°C25°C85°C105°C-40°C25°C
Low-powermode3current,(LPM3)(4)
fDCO=fMCLK=fSMCLK=0MHz,fACLKfrominternalLFoscillator(VLO),
CPUOFF=1,SCG0=1,SCG1=1,OSCOFF=0
85°C105°C-40°C25°C85°C105°C
Low-powermode4(LPM4)current(5)
fDCO=fMCLK=fSMCLK=0MHz,fACLK=0Hz,
CPUOFF=1,SCG0=1,SCG1=1,OSCOFF=1
-40°C25°C85°C105°C
2.2V/3V3V2.2V3V2.2V3V3V3VVCC2.2V
MIN
TYP6063758033363640202523280.80.92.460.913.9100.30.31.85.50.40.4290.10.11.66.5
MAX6572909538434247253030351.21.33131.31.44.3150.90.92.413113150.50.52.513
µAµAµAµAµAµAUNIT
ILPM0,1MHz
Low-powermode0(LPM0)current(3)
2.2V
ILPM0,100kHz
Low-powermode0(LPM0)current(3)
2.2V
ILPM2
Low-powermode2(LPM2)current(4)
ILPM3,LFXT1
ILPM3,VLO
ILPM4
(1)(2)(3)(4)(5)Allinputsaretiedto0VorVCC.Outputsdonotsourceorsinkanycurrent.
ThecurrentsarecharacterizedwithaMicroCrystalCC4V-T1ASMDcrystalwithaloadcapacitanceof9pF.Theinternalandexternalloadcapacitanceischosentocloselymatchtherequired9pF.
CurrentforBrownoutandWDT+isincluded.TheWDT+isclockedbySMCLK.CurrentforBrownoutandWDT+isincluded.TheWDT+isclockedbyACLK.CurrentforBrownoutisincluded.
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TypicalCharacteristics-LPM4Current
LPM4CURRENT
vs
TEMPERATURE
10.0
ILPM4−Low−power mode current−µA9.08.07.06.05.04.03.02.01.0
0.0
−40.0−20.00.0
Vcc = 1.8 V20.040.060.080.0100.0120.0VCC= 3.6 VVCC= 3 VVcc = 2.2VTA−Temperature−°C
Figure4.
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Schmitt-TriggerInputs(PortsP1,P2,P3,P4,P5,P6,RST/NMI,JTAG,XIN,XT2IN)
overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)
PARAMETER
VIT+
Positive-goinginputthresholdvoltage
TESTCONDITIONS
VCC2.2V3V
VIT-Negative-goinginputthresholdvoltage
2.2V3V
VhysRPullCI
Inputvoltagehysteresis(VIT+-VIT-)Pullup/pulldownresistorInputcapacitance
Forpullup:VIN=VSS,Forpulldown:VIN=VCCVIN=VSSorVCC
2.2V3V3V
MIN0.45VCC
11.350.25VCC
0.550.750.20.320
355TYP
MAX0.75VCC
1.652.250.55VCC
1.201.651150
VkΩpFVVUNIT
Inputs(PortsP1,P2)
overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)
PARAMETER
t(int)tcapfTAext,fTBextfTAint,fTBint(1)
ExternalinterrupttimingTimer_ATimer_BcapturetimingTimer_A,Timer_Bclockfrequencyexternallyappliedtopin
Timer_A,Timer_Bclockfrequency
TESTCONDITIONS
PortP1,P2:P1.xtoP2.x,Externaltriggerpulsewidthtosetinterruptflag(1)TA0,TA1,TA2
TB0,TB1,TB2,TB3,TB4,TB5,TB6TACLK,TBCLK,INCLK:t(H)=t(L)SMCLKorACLKsignalselected
VCC2.2V/3V2.2V3V2.2V3V2.2V3V
MIN206250
810810MAX
UNITnsnsMHzMHz
Anexternalsignalsetstheinterruptflageverytimetheminimuminterruptpulsewidtht(int)ismet.Itmaybesetevenwithtriggersignalsshorterthant(int).
LeakageCurrent(PortsP1,P2,P3,P4,P5,P6)
overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)
PARAMETER
Ilkg(Px.y)(1)(2)
High-impedanceleakagecurrent
See
TESTCONDITIONS
(1)(2)
VCC2.2V/3V
MINMAX±50
UNITnA
TheleakagecurrentismeasuredwithVSSorVCCappliedtothecorrespondingpin(s),unlessotherwisenoted.
Theleakageofthedigitalportpinsismeasuredindividually.Theportpinisselectedforinputandthepullup/pulldownresistorisdisabled.
StandardInputs(RST/NMI)
overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)
PARAMETER
VILVIH
Low-levelinputvoltageHigh-levelinputvoltage
TESTCONDITIONS
VCC2.2V/3V2.2V/3V
MINVSS0.8VCC
MAXVSS+0.6
VCC
UNITVV
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Outputs(PortsP1,P2,P3,P4,P5,P6)
overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)
PARAMETER
TESTCONDITIONS
IOH(max)=-1.5mA
VOH
High-leveloutputvoltage
IOH(max)=-6mA
(1)(2)
VCC2.2V3V2.2V3V
MINVCC-0.25VCC-0.6VCC-0.25VCC-0.6
VSSVSSVSSVSS
MAXVCCVCCVCCVCC
VSS+0.25VSS+0.6VSS+0.25VSS+0.6
UNIT
IOH(max)=-1.5mA(1)IOH(max)=-6mA(2)IOL(max)=1.5mA(1)IOL(max)=6mA(2)IOL(max)=1.5mA(1)IOL(max)=6mA(2)
V
VOL
Low-leveloutputvoltageV
(1)(2)
Themaximumtotalcurrent,IOH(max)andIOL(max),foralloutputscombined,shouldnotexceed±12mAtoholdthemaximumvoltagedropspecified.
Themaximumtotalcurrent,IOH(max)andIOL(max),foralloutputscombined,shouldnotexceed±48mAtoholdthemaximumvoltagedropspecified.
OutputFrequency(PortsP1,P2,P3,P4,P5,P6)
overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)
PARAMETER
fPx.yfPort°CLK
PortoutputfrequencywithloadClockoutputfrequency
TESTCONDITIONS
P1.4/SMCLK,CL=20pF,RL=1kΩ(1)(2)P2.0/ACLK/CA2,P1.4/SMCLK,CL=20pF(2)P1.0/TACLK/CAOUT,CL=20pF,LFmodeP1.0/TACLK/CAOUT,CL=20pF,XT1mode
t(Xdc)
Dutycycleofoutputfrequency
P1.1/TA0,CL=20pF,XT1modeP1.1/TA0,CL=20pF,DCO
P1.4/SMCLK,CL=20pF,XT2modeP1.4/SMCLK,CL=20pF,DCO
(1)(2)
VCC2.2V3V2.2V3V
MINDCDCDCDC30%40%40%
50%–15ns
40%
50%–15ns
50%50%TYP
MAX1012121670%60%60%
50%50%+15ns
60%
50%+15ns
MHzUNIT
MHz
Aresistivedividerwithtwo0.5-kΩresistorsbetweenVCCandVSSisusedasload.Theoutputisconnectedtothecentertapofthedivider.
Theoutputvoltagereachesatleast10%and90%VCCatthespecifiedtogglefrequency.
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TypicalCharacteristics-Outputs
Oneoutputloadedatatime.
TYPICALLOW-LEVELOUTPUTCURRENT
vs
LOW-LEVELOUTPUTVOLTAGE
25.0
TYPICALLOW-LEVELOUTPUTCURRENT
vs
LOW-LEVELOUTPUTVOLTAGE
50.0IOL−Typical Low-Level Output Current−mAVCC= 3 VP4.540.0
TA= 85°C30.0
IOL−Typical Low-Level Output Current−mAVCC= 2.2 VP4.520.0
TA= 25°CTA= 85°CTA= 25°C15.0
10.020.0
5.010.0
0.00.0
0.51.01.52.02.5
0.00.0
0.51.01.52.02.53.03.5
VOL−Low-Level Output Voltage−VVOL−Low-Level Output Voltage−V
Figure5.
TYPICALHIGH-LEVELOUTPUTCURRENT
vs
HIGH-LEVELOUTPUTVOLTAGE
0.0IOH−Typical High-Level Output Current−mAIOH−Typical High-Level Output Current−mAVCC= 2.2 VP4.5−5.0
0.0
VCC= 3 VP4.5−10.0
Figure6.
TYPICALHIGH-LEVELOUTPUTCURRENT
vs
HIGH-LEVELOUTPUTVOLTAGE
−10.0−20.0
−15.0
TA= 85°C−30.0
TA= 85°C−40.0
−20.0
−25.0
0.0
TA= 25°C0.5
1.0
1.5
2.0
2.5
VOH−High-Level Output Voltage−V
−50.0
0.0
TA= 25°C0.5
1.0
1.5
2.0
2.5
3.0
3.5
VOH−High-Level Output Voltage−V
Figure7.Figure8.
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POR/BrownoutReset(BOR)
PARAMETER
VCC(start)V(B_IT-)Vhys(B_IT-)td(BOR)t(reset)(1)(2)
Operatingvoltage
(1)(2)
overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)
TESTCONDITIONSdVCC/dt≤3V/sdVCC/dt≤3V/sdVCC/dt≤3V/s
70
130
VCC
MIN
TYP
MAX1.712102000
2.2V/3V
2
UNITVVmVµsµs
0.7×V(B_IT-)
NegativegoingVCCresetthresholdvoltageVCCresetthresholdhysteresisBORresetreleasedelaytime
PulselengthneededatRST/NMIpintoacceptedresetinternally
ThecurrentconsumptionofthebrownoutmoduleisalreadyincludedintheICCcurrentconsumptiondata.ThevoltagelevelV(B_IT-)+Vhys(B_IT-)is≤1.8V.
Duringpowerup,theCPUbeginscodeexecutionfollowingaperiodoftd(BOR)afterVCC=V(B_IT-)+Vhys(B_IT-).ThedefaultDCOsettingsmustnotbechangeduntilVCC≥VCC(min),whereVCC(min)istheminimumsupplyvoltageforthedesiredoperatingfrequency.
VCC
Vhys(B_IT−)V(B_IT−)VCC(start)
1
0
td(BOR)Figure9.POR/BrownoutReset(BOR)vsSupplyVoltage
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TypicalCharacteristics-POR/BrownoutReset(BOR)
21.510.500.001VCC(drop)
VCC= 3 VTypical ConditionsVCC3 V
tpwVCC(drop)−V1tpw−Pulse Width−µs
10001 ns1 nstpw−Pulse Width−µs
Figure10.VCC(drop)LevelWithaSquareVoltageDroptoGenerateaPOR/BrownoutSignal
VCC2VCC= 3 VVCC(drop)−V1.510.500.001VCC(drop)
tf= tr1tpw−Pulse Width−µs
1000tftrTypical Conditions3 V
tpwtpw−Pulse Width−µs
Figure11.VCC(drop)LevelWithaTriangleVoltageDroptoGenerateaPOR/BrownoutSignal
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SVS(SupplyVoltageSupervisor/Monitor)
overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted)
PARAMETERt(SVSR)td(SVSon)tsettleV(SVSstart)
dVCC/dt≤30V/ms
SVSon,switchfromVLD=0toVLD≠0,VCC=3VVLD≠0(1)
VLD≠0,VCC/dt≤3V/s(seeFigure12)
VLD=1
VCC/dt≤3V/s(seeFigure12)
Vhys(SVS_IT-)
VCC/dt≤3V/s(seeFigure12),externalvoltageappliedonA7
V(SVS_IT-)
VLD=2to14VLD=15VLD=1VLD=2VLD=3VLD=4VLD=5VLD=6
VCC/dt≤3V/s(seeFigure12andFigure13)
VLD=7VLD=8VLD=9VLD=10VLD=11VLD=12VLD=13VLD=14
VCC/dt≤3V/s(seeFigure12andFigure13),externalvoltageappliedonA7
ICC(SVS)(3)(1)(2)(3)
VLD≠0,VCC=2.2V/3V
VLD=15
700.001×V(SVS_IT-)
4.41.81.942.052.142.242.332.462.582.692.832.943.113.243.431.1
1.92.12.22.32.42.52.652.82.93.053.23.353.53.7(2)1.2101.55120
150
TESTCONDITIONS
dVCC/dt>30V/ms(seeFigure12)
MIN1
TYP
MAX1502000300121.71550.016×V(SVS_IT-)
202.052.252.372.482.62.712.8633.133.293.423.61(2)3.76(2)3.99(2)
1.315
µAVmVUNITµsµsµsVmV
tsettleisthesettlingtimethatthecomparatoroutputneedstohaveastablelevelafterVLDisswitchedfromVLD≠0toadifferentVLDvaluesomewherebetween2and15.Theoverdriveisassumedtobe>50mV.Therecommendedoperatingvoltagerangeislimitedto3.6V.
ThecurrentconsumptionoftheSVSmoduleisnotincludedintheICCcurrentconsumptiondata.
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Software sets VLD >0:SVS is activeAVCCV(SVS_IT−)V(SVSstart)V(B_IT−)VCC(start)BrownoutRegionBrown-outRegionVhys(SVS_IT−)Vhys(B_IT−)Brownout10SVS out10Set POR1td(BOR)SVS Circuit isActive From VLD > to VCC< V(B_IT−)td(BOR)td(SVSon)undefinedtd(SVSR)0Figure12.SVSReset(SVSR)vsSupplyVoltage
VCC3 Vtpw2Rectangular Drop1.5VCC(min)−VTriangular Drop11 ns0.5VCC3 Vtpw1 nsVCC(min)01101001000VCC(min)tf= trtftrtpw−Pulse Width−µs
t−Pulse Width−µs
Figure13.VCC(min):SquareVoltageDropandTriangleVoltageDroptoGenerateanSVSSignal(VLD=1)
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MainDCOCharacteristics
•••
AllrangesselectedbyRSELxoverlapwithRSELx+1:RSELx=0overlapsRSELx=1,...RSELx=14overlapsRSELx=15.
DCOcontrolbitsDCOxhaveastepsizeasdefinedbyparameterSDCO.
ModulationcontrolbitsMODxselecthowoftenfDCO(RSEL,DCO+1)isusedwithintheperiodof32DCOCLKcycles.ThefrequencyfDCO(RSEL,DCO)isusedfortheremainingcycles.Thefrequencyisanaverageequalto:
faverage=
32×fDCO(RSEL,DCO)×fDCO(RSEL,DCO+1)
MOD×fDCO(RSEL,DCO)+(32–MOD)×fDCO(RSEL,DCO+1)
DCOFrequency
overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)
PARAMETER
VCCfDCO(0,0)fDCO(0,3)fDCO(1,3)fDCO(2,3)fDCO(3,3)fDCO(4,3)fDCO(5,3)fDCO(6,3)fDCO(7,3)fDCO(8,3)fDCO(9,3)fDCO(10,3)fDCO(11,3)fDCO(12,3)fDCO(13,3)fDCO(14,3)fDCO(15,3)fDCO(15,7)SRSELSDCO
SupplyvoltagerangeDCOfrequency(0,0)DCOfrequency(0,3)DCOfrequency(1,3)DCOfrequency(2,3)DCOfrequency(3,3)DCOfrequency(4,3)DCOfrequency(5,3)DCOfrequency(6,3)DCOfrequency(7,3)DCOfrequency(8,3)DCOfrequency(9,3)DCOfrequency(10,3)DCOfrequency(11,3)DCOfrequency(12,3)DCOfrequency(13,3)DCOfrequency(14,3)DCOfrequency(15,3)DCOfrequency(15,7)FrequencystepbetweenrangeRSELandRSEL+1
TESTCONDITIONS
RSELx<14RSELx=14RSELx=15
RSELx=0,DCOx=0,MODx=0RSELx=0,DCOx=3,MODx=0RSELx=1,DCOx=3,MODx=0RSELx=2,DCOx=3,MODx=0RSELx=3,DCOx=3,MODx=0RSELx=4,DCOx=3,MODx=0RSELx=5,DCOx=3,MODx=0RSELx=6,DCOx=3,MODx=0RSELx=7,DCOx=3,MODx=0RSELx=8,DCOx=3,MODx=0RSELx=9,DCOx=3,MODx=0RSELx=10,DCOx=3,MODx=0RSELx=11,DCOx=3,MODx=0RSELx=12,DCOx=3,MODx=0RSELx=13,DCOx=3,MODx=0RSELx=14,DCOx=3,MODx=0RSELx=15,DCOx=3,MODx=0RSELx=15,DCOx=7,MODx=0SRSEL=fDCO(RSEL+1,DCO)/fDCO(RSEL,DCO)
2.2V/3V2.2V/3V2.2V/3V2.2V/3V2.2V/3V2.2V/3V2.2V/3V2.2V/3V2.2V/3V2.2V/3V2.2V/3V2.2V/3V2.2V/3V2.2V/3V2.2V/3V2.2V/3V3V3V2.2V/3V2.2V/3V2.2V/3V
1.0540
1.0850
VCC
MIN1.82.23.00.060.070.100.140.200.280.390.540.801.101.602.503.004.306.008.6012.016.0
TYP
MAX3.63.63.60.140.170.200.280.400.540.771.061.502.103.004.305.507.309.6013.918.526.01.551.1260
MHzMHzMHzMHzMHzMHzMHzMHzMHzMHzMHzMHzMHzMHzMHzMHzMHzMHzratioratio%VUNIT
FrequencystepbetweentapDCO
SDCO=fDCO(RSEL,DCO+1)/fDCO(RSEL,DCO)
andDCO+1Dutycycle
MeasuredatP1.4/SMCLK
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CalibratedDCOFrequencies-ToleranceatCalibration
overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)
PARAMETER
Frequencytoleranceatcalibration
fCAL(1MHz)
1-MHzcalibrationvalue
BCSCTL1=CALBC1_1MHZ,DCOCTL=CALDCO_1MHZ,Gatingtime:5ms
BCSCTL1=CALBC1_8MHZ,DCOCTL=CALDCO_8MHZ,Gatingtime:5ms
BCSCTL1=CALBC1_12MHZ,DCOCTL=CALDCO_12MHZ,Gatingtime:5ms
BCSCTL1=CALBC1_16MHZ,DCOCTL=CALDCO_16MHZ,Gatingtime:2ms
TESTCONDITIONS
TA25°C25°C
VCC3V3V
MIN-10.990
TYP±0.21
MAX+11.010
UNIT%MHz
fCAL(8MHz)
8-MHzcalibrationvalue25°C3V7.92088.080MHz
fCAL(12MHz)
12-MHzcalibrationvalue25°C3V11.881212.12MHz
fCAL(16MHz)
16-MHzcalibrationvalue25°C3V15.841616.16MHz
CalibratedDCOFrequencies-ToleranceOverTemperature0°Cto85°C
overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)
PARAMETER1-MHztoleranceovertemperature
8-MHztoleranceovertemperature
12-MHztoleranceovertemperature
16-MHztoleranceovertemperature
fCAL(1MHz)
1-MHzcalibrationvalue
BCSCTL1=CALBC1_1MHZ,DCOCTL=CALDCO_1MHZ,Gatingtime:5ms
BCSCTL1=CALBC1_8MHZ,DCOCTL=CALDCO_8MHZ,Gatingtime:5ms
BCSCTL1=CALBC1_12MHZ,DCOCTL=CALDCO_12MHZ,Gatingtime:5ms
BCSCTL1=CALBC1_16MHZ,DCOCTL=CALDCO_16MHZ,Gatingtime:2ms
TESTCONDITIONS
TA0°Cto85°C0°Cto85°C0°Cto85°C0°Cto85°C
VCC3V3V3V3V2.2V
0°Cto85°C
3V3.6V2.2V
0°Cto85°C
3V3.6V2.2V
0°Cto85°C
3V3.6V3V
0°Cto85°C
3.6V
MIN-2.5-2.5-2.5-30.970.9750.977.767.87.611.6411.6411.6415.5215
TYP±0.5±1.0±1.0±2.01118881212121616
MAX2.52.52.531.031.0251.038.48.28.2412.3612.3612.3616.4816.48
MHzMHzMHzMHzUNIT%%%%
fCAL(8MHz)
8-MHzcalibrationvalue
fCAL(12MHz)
12-MHzcalibrationvalue
fCAL(16MHz)
16-MHzcalibrationvalue
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CalibratedDCOFrequencies-ToleranceOverSupplyVoltageVCC
overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)
PARAMETER
1-MHztoleranceoverVCC8-MHztoleranceoverVCC12-MHztoleranceoverVCC16-MHztoleranceoverVCC
fCAL(1MHz)
1-MHzcalibrationvalue
BCSCTL1=CALBC1_1MHZ,DCOCTL=CALDCO_1MHZ,Gatingtime:5ms
BCSCTL1=CALBC1_8MHZ,DCOCTL=CALDCO_8MHZ,Gatingtime:5ms
BCSCTL1=CALBC1_12MHZ,DCOCTL=CALDCO_12MHZ,Gatingtime:5ms
BCSCTL1=CALBC1_16MHZ,DCOCTL=CALDCO_16MHZ,Gatingtime:2ms
TESTCONDITIONS
TA25°C25°C25°C25°C25°C
VCC1.8Vto3.6V1.8Vto3.6V2.2Vto3.6V3Vto3.6V1.8Vto3.6V
MIN-3-3-3-60.97
TYP±2±2±2±21
MAX+3+3+3+31.03
UNIT%%%%MHz
fCAL(8MHz)
8-MHzcalibrationvalue25°C1.8Vto3.6V7.7688.24MHz
fCAL(12MHz)
12-MHzcalibrationvalue25°C2.2Vto3.6V11.641212.36MHz
fCAL(16MHz)
16-MHzcalibrationvalue25°C3Vto3.6V151616.48MHz
CalibratedDCOFrequencies-OverallTolerance
overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)
PARAMETER
1-MHztoleranceoverall
8-MHztoleranceoverall
12-MHz
toleranceoverall16-MHz
toleranceoverall
fCAL(1MHz)
BCSCTL1=CALBC1_1MHZ,
1-MHz
DCOCTL=CALDCO_1MHZ,
calibrationvalue
Gatingtime:5msBCSCTL1=CALBC1_8MHZ,
8-MHz
DCOCTL=CALDCO_8MHZ,
calibrationvalue
Gatingtime:5msBCSCTL1=CALBC1_12MHZ,
12-MHz
DCOCTL=CALDCO_12MHZ,
calibrationvalue
Gatingtime:5msBCSCTL1=CALBC1_16MHZ,
16-MHz
DCOCTL=CALDCO_16MHZ,
calibrationvalue
Gatingtime:2ms
TESTCONDITIONS
TA
-40°Cto105°C-40°Cto105°C-40°Cto105°C-40°Cto105°C-40°Cto105°C
VCC1.8Vto3.6V1.8Vto3.6V2.2Vto3.6V3Vto3.6V1.8Vto3.6V
MIN-5-5-5-60.95
TYP±2±2±2±31
MAX+5+5+5+61.05
UNIT%%%%MHz
fCAL(8MHz)
-40°Cto105°C1.8Vto3.6V7.688.4MHz
fCAL(12MHz)
-40°Cto105°C2.2Vto3.6V11.41212.6MHz
fCAL(16MHz)
-40°Cto105°C3Vto3.6V151617MHz
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TypicalCharacteristics-CalibratedDCOFrequency
CALIBRATED1-MHzFREQUENCY
vs
SUPPLYVOLTAGE
1.04
8.208.15
1.03
8.10
Frequency−MHzFrequency−MHz1.02
8.058.007.957.90
1.00
TA= 105°C0.99
1.5
2.0
2.5
3.0
3.5
4.0
TA= 85°C7.857.80
1.5
TA= 85°CTA=−40°CCALIBRATED8-MHzFREQUENCY
vs
SUPPLYVOLTAGE
1.01
TA=−40°CTA= 25°CTA= 25°CTA= 105°C2.0
2.5
3.0
3.5
4.0
VCC−Supply Voltage−VVCC−Supply Voltage−V
Figure14.
CALIBRATED12-MHzFREQUENCY
vs
SUPPLYVOLTAGE
12.5
16.1
Figure15.
CALIBRATED16-MHzFREQUENCY
vs
SUPPLYVOLTAGE
12.3
TA=−40°C12.1
TA= 25°CTA= 85°CTA= 105°C16.0
TA=−40°CTA= 25°CFrequency−MHzFrequency−MHz15.9
15.8
TA= 85°C11.9
15.7
11.7
15.6
TA= 105°C11.5
1.5
2.02.53.03.54.0
15.5
1.5
2.02.53.03.54.0
VCC−Supply Voltage−VVCC−Supply Voltage−V
Figure16.Figure17.
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Wake-UpFromLower-PowerModes(LPM3/4)
overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)
PARAMETER
TESTCONDITIONS
BCSCTL1=CALBC1_1MHZ,DCOCTL=CALDCO_1MHZ
BCSCTL1=CALBC1_8MHZ,
DCOclockwake-uptimeDCOCTL=CALDCO_8MHZfromLPM3/4(1)BCSCTL1=CALBC1_12MHZ,
DCOCTL=CALDCO_12MHZ
BCSCTL1=CALBC1_16MHZ,DCOCTL=CALDCO_16MHZ
tCPU,LPM3/4(1)(2)
CPUwake-uptimefromLPM3/4(2)
2.2V/3VVCC
MIN
TYP
MAX
21.5
µs1
3V
1/fMCLK+tClock,LPM3/4
1
UNIT
tDCO,LPM3/4
TheDCOclockwake-uptimeismeasuredfromtheedgeofanexternalwake-upsignal(forexample,aportinterrupt)tothefirstclockedgeobservableexternallyonaclockpin(MCLKorSMCLK).ParameterapplicableonlyifDCOCLKisusedforMCLK.
TypicalCharacteristics-DCOClockWake-UpTimeFromLPM3/4
CLOCKWAKE-UPTIMEFROMLPM3
vs
DCOFREQUENCY
10.00DCO WakeTime−µsRSELx = 0 to 111.00RSELx = 12 to 150.100.10
1.00
DCO Frequency−MHz
10.00
Figure18.
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DCOWithExternalResistorROSC(1)
overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)
PARAMETER
fDCO,ROSCDTDV(1)
DCOoutputfrequencywithROSCTemperaturedriftDriftwithVCC
TESTCONDITIONS
DCOR=1,
RSELx=4,DCOx=3,MODx=0,TA=25°C
DCOR=1,
RSELx=4,DCOx=3,MODx=0DCOR=1,
RSELx=4,DCOx=3,MODx=0
VCC2.2V3V2.2V/3V2.2V/3V
TYP1.81.95±0.110
MHz%/°C%/VUNIT
ROSC=100kΩ.Metalfilmresistor,type0257,0.6Wwith1%toleranceandTK=±50ppm/°C.
TypicalCharacteristics-DCOWithExternalResistorROSC
DCOFREQUENCY
vsROSC
VCC=2.2V,TA=25°C
10.0010.00DCOFREQUENCY
vsROSC
VCC=3V,TA=25°C
DCO Frequency−MHz1.00RSELx = 40.10DCO Frequency−MHz1.00RSELx = 40.100.0110.00
100.001000.0010000.00
0.0110.00
100.001000.0010000.00
ROSC−External Resistor−kWROSC−External Resistor−kW
Figure19.DCOFREQUENCY
vs
TEMPERATURE
VCC=3V
2.502.25DCO Frequency−MHzDCO Frequency−MHz2.502.25Figure20.DCOFREQUENCY
vs
SUPPLYVOLTAGE
TA=25°C
2.001.751.501.251.000.750.500.250.00−50.0−25.0
0.0
25.0
50.0
ROSC= 100k2.001.751.501.251.000.750.500.250.002.0
2.5
3.0
ROSC= 100kROSC= 270kROSC= 270kROSC= 1MROSC= 1M75.0100.03.54.0
TA−Temperature−CVCC−Supply Voltage−V
Figure21.
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CrystalOscillatorLFXT1,Low-FrequencyMode(1)
overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)
PARAMETER
fLFXT1,LFfLFXT1,LF,logic
LFXT1oscillatorcrystalfrequency,LFmode0,1
TESTCONDITIONS
XTS=0,LFXT1Sx=0or1
VCC1.8Vto3.6V1.8Vto3.6V
10000MIN
TYP3276832768500
kΩ
20015.58.511
2.2V/3V2.2V/3V
3010
50
7010000
%HzpF
50000MAX
UNITHzHz
LFXT1oscillatorlogiclevel
squarewaveinputfrequency,XTS=0,LFXT1Sx=3,XCAPx=0LFmode
OscillationallowanceforLFcrystals
XTS=0,LFXT1Sx=0,
fLFXT1,LF=32768Hz,CL,eff=6pFXTS=0,LFXT1Sx=0,
fLFXT1,LF=32768Hz,CL,eff=12pFXTS=0,XCAPx=0XTS=0,XCAPx=1XTS=0,XCAPx=2XTS=0,XCAPx=3
Dutycycle,LFmode
XTS=0,MeasuredatP2.0/ACLK,fLFXT1,LF=32768Hz
XTS=0,LFXT1Sx=3,XCAPx=0(4)
OALF
CL,eff
Integratedeffectiveloadcapacitance,LFmode(2)
fFault,LF(1)
Oscillatorfaultfrequency,LFmode(3)
(2)(3)(4)
ToimproveEMIontheXT1oscillator,thefollowingguidelinesshouldbeobserved.(a)Keepthetracebetweenthedeviceandthecrystalasshortaspossible.(b)Designagoodgroundplanearoundtheoscillatorpins.
(c)PreventcrosstalkfromotherclockordatalinesintooscillatorpinsXINandXOUT.(d)AvoidrunningPCBtracesunderneathoradjacenttotheXINandXOUTpins.
(e)UseassemblymaterialsandpraxistoavoidanyparasiticloadontheoscillatorXINandXOUTpins.
(f)Ifconformalcoatingisused,ensurethatitdoesnotinducecapacitive/resistiveleakagebetweentheoscillatorpins.
(g)DonotroutetheXOUTlinetotheJTAGheadertosupporttheserialprogrammingadapterasshowninotherdocumentation.Thissignalisnolongerrequiredfortheserialprogrammingadapter.
Includesparasiticbondandpackagecapacitance(approximately2pFperpin).
BecausethePCBaddsadditionalcapacitance,itisrecommendedtoverifythecorrectloadbymeasuringtheACLKfrequency.Foracorrectsetup,theeffectiveloadcapacitanceshouldalwaysmatchthespecificationofthecrystalthatisused.
FrequenciesbelowtheMINspecificationsetthefaultflag.FrequenciesabovetheMAXspecificationdonotsetthefaultflag.Frequenciesinbetweenmightsettheflag.
Measuredwithlogic-levelinputfrequencybutalsoappliestooperationwithcrystals.
InternalVery-Low-PowerLow-FrequencyOscillator(VLO)
overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)
PARAMETER
fVLOdfVLO/dTdfVLO/dVCC(1)(2)
VLOfrequency
VLOfrequencytemperaturedrift
(1)(2)
VCC2.2V/3V2.2V/3V1.8Vto3.6V
MIN4
TYP120.54
MAX20
UNITkHz%/°C%/V
VLOfrequencysupplyvoltagedrift
Calculatedusingtheboxmethod:
Iversion:(MAX(-40to85°C)-MIN(-40to85°C))/MIN(-40to85°C)/(85°C-(-40°C))
Tversion:(MAX(-40to105°C)-MIN(-40to105°C))/MIN(-40to105°C)/(105°C-(-40°C))
Calculatedusingtheboxmethod:(MAX(1.8to3.6V)-MIN(1.8to3.6V))/MIN(1.8to3.6V)/(3.6V-1.8V)
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CrystalOscillatorLFXT1,High-FrequencyMode(1)
PARAMETER
fLFXT1,HF0fLFXT1,HF1
LFXT1oscillatorcrystalfrequency,HFmode0LFXT1oscillatorcrystalfrequency,HFmode1LFXT1oscillatorcrystalfrequency,HFmode2LFXT1oscillatorlogic-levelsquare-waveinputfrequency,HFmode
TESTCONDITIONS
XTS=1,LFXT1Sx=0,XCAPx=0XTS=1,LFXT1Sx=1,XCAPx=0
VCC1.8Vto3.6V1.8Vto3.6V1.8Vto3.6V
fLFXT1,HF2
XTS=1,LFXT1Sx=2,XCAPx=0
2.2Vto3.6V3Vto3.6V1.8Vto3.6V
XTS=1,LFXT1Sx=3,XCAPx=0XTS=1,XCAPx=0,LFXT1Sx=0,fLFXT1,HF=1MHz,CL,eff=15pFXTS=1,XCAPx=0,LFXT1Sx=1,fLFXT1,HF=4MHz,CL,eff=15pFXTS=1,XCAPx=0,LFXT1Sx=2,fLFXT1,HF=16MHz,CL,eff=15pF
CL,eff
Integratedeffectiveloadcapacitance,HFmode(2)
XTS=1,XCAPx=0(3)XTS=1,XCAPx=0,
MeasuredatP1.4/SMCLK,fLFXT1,HF=10MHzXTS=1,XCAPx=0,
MeasuredatP1.4/SMCLK,fLFXT1,HF=16MHz
(4)
MIN0.412220.40.40.4
TYPMAX
14101216101216
UNITMHzMHz
MHz
fLFXT1,HF,logic
2.2Vto3.6V3Vto3.6V
MHz
27008003001
40
2.2V/3V
40
2.2V/3V
30
50
60300
kHz
50
60
%pFΩ
OAHF
OscillationallowanceforHFcrystals(seeFigure23andFigure24)
Dutycycle,HFmode
fFault,HF(1)
Oscillatorfaultfrequency
XTS=1,LFXT1Sx=3,XCAPx=0(5)
(2)(3)(4)(5)
ToimproveEMIontheXT2oscillatorthefollowingguidelinesshouldbeobserved:(a)Keepthetracebetweenthedeviceandthecrystalasshortaspossible.(b)Designagoodgroundplanearoundtheoscillatorpins.
(c)PreventcrosstalkfromotherclockordatalinesintooscillatorpinsXINandXOUT.(d)AvoidrunningPCBtracesunderneathoradjacenttotheXINandXOUTpins.
(e)UseassemblymaterialsandpraxistoavoidanyparasiticloadontheoscillatorXINandXOUTpins.
(f)Ifconformalcoatingisused,ensurethatitdoesnotinducecapacitive/resistiveleakagebetweentheoscillatorpins.
(g)DonotroutetheXOUTlinetotheJTAGheadertosupporttheserialprogrammingadapterasshowninotherdocumentation.Thissignalisnolongerrequiredfortheserialprogrammingadapter.
Includesparasiticbondandpackagecapacitance(approximately2pFperpin).BecausethePCBaddsadditionalcapacitance,itisrecommendedtoverifythecorrectloadbymeasuringtheACLKfrequency.Foracorrectsetup,theeffectiveloadcapacitanceshouldalwaysmatchthespecificationoftheusedcrystal.
Requiresexternalcapacitorsatbothterminals.Valuesarespecifiedbycrystalmanufacturers.
FrequenciesbelowtheMINspecificationsetthefaultflag,frequenciesabovetheMAXspecificationdonotsetthefaultflag,andfrequenciesinbetweenmightsettheflag.
Measuredwithlogic-levelinputfrequency,butalsoappliestooperationwithcrystals.
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TypicalCharacteristics-LFXT1OscillatorinHFMode(XTS=1)
OSCILLATIONALLOWANCE
vs
CRYSTALFREQUENCYCL,eff=15pF,TA=25°C
100000.00OscillationAllowance−W10000.001000.00LFXT1Sx = 2100.00LFXT1Sx = 0LFXT1Sx = 110.000.10
1.0010.00100.00
Crystal Frequency−MHz
Figure23.
OSCILLATORSUPPLYCURRENT
vs
CRYSTALFREQUENCYCL,eff=15pF,TA=25°C
1600.01500.01400.01300.01200.01100.01000.0900.0800.0700.0600.0500.0400.0300.0200.0100.00.00.0
XTOscillator Supply Current−µALFXT1Sx = 2LFXT1Sx = 1LFXT1Sx = 04.0
8.0
12.0
16.0
20.0
Crystal Frequency−MHz
Figure24.
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CrystalOscillatorXT2(1)
PARAMETER
fXT2fXT2
XT2oscillatorcrystalfrequency,mode0
XT2oscillatorcrystalfrequency,mode1
XT2oscillatorcrystalfrequency,mode2
TESTCONDITIONSXT2Sx=0XT2Sx=1
VCC1.8Vto3.6V1.8Vto3.6V1.8Vto2.2V
fXT2
XT2Sx=2
2.2Vto3.0V3.0Vto3.6V1.8Vto2.2V
fXT2
XT2oscillatorlogic-levelsquare-wave
XT2Sx=3
inputfrequency
XT2Sx=0,fXT2=1MHz,CL,eff=15pF
OA
Oscillationallowance(seeFigure25andFigure26)
XT2Sx=1,fXT2=4MHz,CL,eff=15pF
XT2Sx=2,fXT2=16MHz,CL,eff=15pF
CL,eff
Integratedeffectiveloadcapacitance,HFmode(2)
See
(3)
MIN0.412220.40.40.4
TYPMAX
14101216101216
UNITMHzMHz
MHz
2.2Vto3.0V3.0Vto3.6V
MHz
27008003001
40
2.2V/3V
40
2.2V/3V
30
50
60300
kHz
50
60
%pFΩ
Dutycycle
MeasuredatP1.4/SMCLK,fXT2=10MHz
MeasuredatP1.4/SMCLK,fXT2=16MHz
fFault(1)
Oscillatorfaultfrequency,HFmode(4)XT2Sx=3(5)
(2)(3)(4)(5)
ToimproveEMIontheXT2oscillatorthefollowingguidelinesshouldbeobserved:(a)Keepthetracebetweenthedeviceandthecrystalasshortaspossible.(b)Designagoodgroundplanearoundtheoscillatorpins.
(c)PreventcrosstalkfromotherclockordatalinesintooscillatorpinsXT2INandXT2OUT.(d)AvoidrunningPCBtracesunderneathoradjacenttotheXT2INandXT2OUTpins.
(e)UseassemblymaterialsandpraxistoavoidanyparasiticloadontheoscillatorXT2INandXT2OUTpins.
(f)Ifconformalcoatingisused,ensurethatitdoesnotinducecapacitive/resistiveleakagebetweentheoscillatorpins.
Includesparasiticbondandpackagecapacitance(approximately2pFperpin).BecausethePCBaddsadditionalcapacitance,itisrecommendedtoverifythecorrectloadbymeasuringtheACLKfrequency.Foracorrectsetup,theeffectiveloadcapacitanceshouldalwaysmatchthespecificationoftheusedcrystal.
Requiresexternalcapacitorsatbothterminals.Valuesarespecifiedbycrystalmanufacturers.
FrequenciesbelowtheMINspecificationsetthefaultflag,frequenciesabovetheMAXspecificationdonotsetthefaultflag,andfrequenciesinbetweenmightsettheflag.
Measuredwithlogic-levelinputfrequency,butalsoappliestooperationwithcrystals.
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TypicalCharacteristics-XT2Oscillator
OSCILLATIONALLOWANCE
vs
CRYSTALFREQUENCYCL,eff=15pF,TA=25°C
100000.00OscillationAllowance−W10000.001000.00XT2Sx = 2100.00XT2Sx = 0XT2Sx = 110.000.10
1.0010.00100.00
Crystal Frequency−MHz
Figure25.
OSCILLATORSUPPLYCURRENT
vs
CRYSTALFREQUENCYCL,eff=15pF,TA=25°C
1600.01500.01400.01300.01200.01100.01000.0900.0800.0700.0600.0500.0400.0300.0200.0100.00.00.0
XTOscillator Supply Current−µAXT2Sx = 2XT2Sx = 1XT2Sx = 04.0
8.0
12.0
16.0
20.0
Crystal Frequency−MHz
Figure26.
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Timer_A
overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)
PARAMETER
fTAtTA,cap
Timer_AclockfrequencyTimer_Acapturetiming
TESTCONDITIONS
Internal:SMCLK,ACLKExternal:TACLK,INCLKDutycycle=50%±10%TA0,TA1,TA2
VCC2.2V3V2.2V/3V
20MIN
TYP
MAX1016
MHznsUNIT
Timer_B
overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)
PARAMETER
fTBtTB,cap
Timer_BclockfrequencyTimer_Bcapturetiming
TESTCONDITIONS
Internal:SMCLK,ACLKExternal:TACLK,INCLKDutycycle=50%±10%TB0,TB1,TB2
VCC2.2V3V2.2V/3V
20MIN
TYP
MAX1016
MHznsUNIT
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USCI(UARTMode)
overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)
PARAMETER
fUSCIfBITCLKtτ(1)(2)
USCIinputclockfrequencyBITCLKclockfrequency
(equalsbaudrateinMBaud)(1)UARTreceivedeglitchtime(2)
CONDITIONS
Internal:SMCLK,ACLKExternal:UCLK
Dutycycle=50%±10%
2.2V/3V2.2V3V
5050
150100
VCC
MIN
TYP
MAXfSYSTEM
1
UNITMHzMHzns
TheDCOwake-uptimemustbeconsideredinLPM3/4forbaudratesabove1MHz.
PulsesontheUARTreceiveinput(UCxRX)shorterthantheUARTreceivedeglitchtimearesuppressed.
USCI(SPIMasterMode)(1)
overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)(seeFigure27andFigure28)
PARAMETER
fUSCItSU,MItHD,MItVALID,MO(1)
USCIinputclockfrequencySOMIinputdatasetuptimeSOMIinputdataholdtimeSIMOoutputdatavalidtime
UCLKedgetoSIMOvalid,CL=20pF
TESTCONDITIONS
SMCLK,ACLK
Dutycycle=50%±10%
2.2V3V2.2V3V2.2V3V
1107500
3020
VCC
MIN
TYP
MAXfSYSTEM
UNITMHznsnsns
fUCxCLK=1/2tLO/HIwithtLO/HI≥max(tVALID,MO(USCI)+tSU,SI(Slave),tSU,MI(USCI)+tVALID,SO(Slave)).
Fortheslave'sparameterstSU,SI(Slave)andtVALID,SO(Slave),seetheSPIparametersoftheattachedslave.
USCI(SPISlaveMode)(1)
overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)(seeFigure29andFigure30)
PARAMETER
tSTE,LEADtSTE,LAGtSTE,ACCtSTE,DIStSU,SItHD,SItVALID,SO(1)
STEleadtime,STElowtoclockSTElagtime,LastclocktoSTEhighSTEaccesstime,STElowtoSOMIdataoutSTEdisabletime,STEhightoSOMIhighimpedance
SIMOinputdatasetuptimeSIMOinputdataholdtimeSOMIoutputdatavalidtime
UCLKedgetoSOMIvalid,CL=20pF
TESTCONDITIONS
VCC2.2V/3V2.2V/3V2.2V/3V2.2V/3V2.2V3V2.2V3V2.2V3V
20151010
7550
11075
10
5050
MIN
TYP50
MAX
UNITnsnsnsnsnsnsns
fUCxCLK=1/2tLO/HIwithtLO/HI≥max(tVALID,MO(Master)+tSU,SI(USCI),tSU,MI(Master)+tVALID,SO(USCI)).
Forthemaster'sparameterstSU,MI(Master)andtVALID,MO(Master)seetheSPIparametersoftheattachedslave.
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1/fUCxCLKCKPL=0
UCLK
CKPL=1
tLO/HItLO/HItSU,MItHD,MISOMI
tVALID,MOSIMO
Figure27.SPIMasterMode,CKPH=0
1/fUCxCLKCKPL=0
UCLK
CKPL=1
tLO/HItLO/HItSU,MISOMI
tHD,MItVALID,MOSIMO
Figure28.SPIMasterMode,CKPH=1
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tSTE,LEADSTE
1/fUCxCLKCKPL=0
UCLK
CKPL=1
tLO/HItLO/HItSU,SItHD,SISIMO
tSTE,LAGtSTE,ACCSOMI
tVALID,SOtSTE,DISFigure29.SPISlaveMode,CKPH=0
tSTE,LEADSTE
1/fUCxCLKCKPL=0
UCLK
CKPL=1
tLO/HItLO/HItSU,SISIMO
tHD,SItSTE,LAGtSTE,ACCSOMI
tVALID,SOtSTE,DISFigure30.SPISlaveMode,CKPH=1
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USCI(I2CMode)
overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)(seeFigure31)
PARAMETER
fUSCIfSCLtHD,STAtSU,STAtHD,DATtSU,DATtSU,STOtSP
USCIinputclockfrequencySCLclockfrequencyHoldtime(repeated)STARTSetuptimeforarepeatedSTARTDataholdtimeDatasetuptimeSetuptimeforSTOP
Pulsewidthofspikessuppressedbyinputfilter
tHD,STASDA
1/fSCLSCL
tSU,DATtHD,DATtSU,STOtSPtSU,STAtHD,STATESTCONDITIONSInternal:SMCLK,ACLKExternal:UCLK
Dutycycle=50%±10%
VCC
MINTYPMAXfSYSTEM
UNITMHzkHzµsµsnsnsµs
2.2V/3V
fSCL≤100kHzfSCL>100kHzfSCL≤100kHzfSCL>100kHz
2.2V/3V2.2V/3V2.2V/3V2.2V/3V2.2V/3V2.2V3V
040.64.70.6025045050
150100
400
600600
ns
Figure31.I2CModeTiming
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Comparator_A+(1)
overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted)
PARAMETER
I(DD)
I(Refladder/RefDiode)VICV(Ref025)V(Ref050)V(RefVT)V(offset)Vhys
Common-modeinputvoltagerangeVoltageat0.25VCCnode/VCC
TESTCONDITIONS
CAON=1,CARSEL=0,CAREF=0CAON=1,CARSEL=0,CAREF=1/2/3,NoloadatP2.3/CA0/TA1andP2.4/CA1/TA2CAON=1
PCA0=1,CARSEL=1,CAREF=1,
NoloadatP2.3/CA0/TA1andP2.4/CA1/TA2
VCC2.2V3V2.2V3V2.2V/3V2.2V/3V2.2V/3V2.2V3V2.2V/3V
CAON=1
TA=25°C,Overdrive10mV,Withoutfilter:CAF=0(3)
(seeFigure32andFigure33)TA=25°C,Overdrive10mV,Withoutfilter:CAF=1(3)
(seeFigure32andFigure33)
2.2V/3V2.2V3V2.2V3V
00.230.47390400-30080701.40.9
0.71651201.91.50.240.48480490
MIN
TYP25453045
MAX40605071VCC-10.250.5540550301.43002402.82.2
µsnsmVmVmVUNITµAµAV
Voltageat0.5VCCnode/PCA0=1,CARSEL=1,CAREF=2,VCCNoloadatP2.3/CA0/TA1andP2.4/CA1/TA2SeeFigure36andFigure37Offsetvoltage(2)Inputhysteresis
PCA0=1,CARSEL=1,CAREF=3,
NoloadatP2.3/CA0/TA1andP2.4/CA1/TA2,TA=85°C
t(response)
Responsetime(low-to-highandhigh-to-low)
(1)(2)(3)
TheleakagecurrentfortheComparator_A+terminalsisidenticaltoIlkg(Px.y)specification.
TheinputoffsetvoltagecanbecancelledbyusingtheCAEXbittoinverttheComparator_A+inputsonsuccessivemeasurements.Thetwosuccessivemeasurementsarethensummedtogether.
TheresponsetimeismeasuredatP2.2/CAOUT/TA0/CA4withaninputvoltagestep,withComparator_A+alreadyenabled(CAON=1).IfCAONissetatthesametime,asettlingtimeofupto300nsisaddedtotheresponsetime.
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0 V0VCC1CAONCAFLow Pass FilterV+V−
+_0101To InternalModules
CAOUTSet CAIFGFlag
τ≈2.0µs
Figure32.Comparator_A+BlockDiagram
OverdriveV−400 mVV+t(response)VCAOUTFigure33.Comparator_A+OverdriveDefinitionFigure34.Comparator_A+ShortResistanceTestCondition
CASHORTCA01VIN+−Comparator_A+CASHORT=1IOUT= 10µA
CA1Figure35.Comparator_A+ShortResistanceTestCondition
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TypicalCharacteristics,Comparator_A+
V(RefVT)vs
TEMPERATURE(VCC=3V)
650
VCC= 3 VV(REFVT)−Reference Volts−mVV(RefVT)vs
TEMPERATURE(VCC=2.2V)
650
VCC= 2.2 VV(REFVT)−Reference Volts−mV600
Typical550
600
Typical550
500500
450450
400−45
−25−51535557595
400−45
−25−51535557595
TA−Free-AirTemperature−°CTA−Free-AirTemperature−°C
Figure 1.V(RefVT)vsTemperature, VCC= 3 V
Figure36.
SHORTRESISTANCE
vsVIN/VCC
Figure37.
100.00Short Resistance−kWVCC= 1.8 VVCC= 2.2V10.00VCC= 3 VVCC= 3.6 V1.000.0
0.20.40.60.81.0
VIN/VCC−Normalized Input Voltage−V/V
Figure38.
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12-bitADC,PowerSupplyandInputRangeConditions(1)
overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted)
PARAMETER
AVCC
Analogsupplyvoltage
TESTCONDITIONS
AVCCandDVCCareconnectedtogetherAVSSandDVSSareconnectedtogetherV(AVSS)=V(DVSS)=0V
AllP6.0/A0toP6.7/A7terminals,AnaloginputsselectedinADC12MCTLxregister,P6Sel.x=1,0≤×≤7,V(AVSS)≤VP6.x/Ax≤V(AVCC)
fADC12CLK=5MHz,
ADC12ON=1,REFON=0,
SHT0=0,SHT1=0,ADC12DIV=0fADC12CLK=5MHz,
ADC12ON=0,REFON=1,REF2_5V=1fADC12CLK=5MHz,
ADC12ON=0,REFON=1,REF2_5V=0Onlyoneterminalcanbeselectedatonetime,P6.x/Ax
0V≤VAx≤VAVCC
2.2V3V3V2.2V3V2.2V3VVCC
MIN2.2
TYP
MAX3.6
UNITV
V(P6.x/Ax)
Analoginputvoltagerange(2)
OperatingsupplycurrentintoAVCCterminal(3)
0
0.650.80.50.50.5
VAVCC
0.810.70.70.7402000
V
IADC12
mAmAmApFΩ
IREF+
OperatingsupplycurrentintoAVCCterminal(4)Inputcapacitance(5)InputMUXONresistance(5)
CIRI(1)(2)(3)(4)(5)
TheleakagecurrentisdefinedintheleakagecurrenttablewithP6.x/Axparameter.
TheanaloginputvoltagerangemustbewithintheselectedreferencevoltagerangeVR+toVR–forvalidconversionresults.TheinternalreferencesupplycurrentisnotincludedincurrentconsumptionparameterIADC12.
TheinternalreferencecurrentissuppliedviaterminalAVCC.ConsumptionisindependentoftheADC12ONcontrolbit,unlessaconversionisactive.TheREFONbitenablessettlingofthebuilt-inreferencebeforestartinganA/Dconversion.Notproductiontested,limitsverifiedbydesign.
12-BitADC,ExternalReference(1)
overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted)
PARAMETER
VeREF+VREF–/VeREF–(VeREF+–VREF–/VeREF–)IVeREF+IVREF–/VeREF–(1)(2)(3)(4)
PositiveexternalreferencevoltageinputNegativeexternalreferencevoltageinputDifferentialexternalreferencevoltageinputStaticleakagecurrentStaticleakagecurrent
TESTCONDITIONSVeREF+>VREF–/VeREF–VeREF+>VREF–/VeREF–VeREF+>VREF–/VeREF–0V≤VeREF+≤VAVCC0V≤VeREF–≤VAVCC
(2)(3)(4)
VCC
MIN0
MAX1.2
UNITVVVµAµA
1.4VAVCC
1.4VAVCC
2.2V/3V2.2V/3V
±1±1
Theexternalreferenceisusedduringconversiontochargeanddischargethecapacitancearray.Theinputcapacitance,CI,isalsothedynamicloadforanexternalreferenceduringconversion.Thedynamicimpedanceofthereferencesupplyshouldfollowtherecommendationsonanalog-sourceimpedancetoallowthechargetosettlefor12-bitaccuracy.
Theaccuracylimitstheminimumpositiveexternalreferencevoltage.Lowerreferencevoltagelevelsmaybeappliedwithreducedaccuracyrequirements.
Theaccuracylimitsthemaximumnegativeexternalreferencevoltage.Higherreferencevoltagelevelsmaybeappliedwithreducedaccuracyrequirements.
Theaccuracylimitsminimumexternaldifferentialreferencevoltage.Lowerdifferentialreferencevoltagelevelsmaybeappliedwithreducedaccuracyrequirements.
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12-BitADC,Built-InReference
overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted)
PARAMETERPositivebuilt-inreferencevoltageoutput
TESTCONDITIONS
REF2_5V=1for2.5V,
IVREF+max≤IVREF+≤IVREF+minREF2_5V=0for1.5V,
IVREF+max≤IVREF+≤IVREF+minREF2_5V=0,
IVREF+max≤IVREF+≤IVREF+minREF2_5V=1,
-0.5mA≤IVREF+≤IVREF+minREF2_5V=1,
-1mA≤IVREF+≤IVREF+min
2.2V3V
IVREF+=500µA±100µA,Analoginputvoltage≈0.75V,REF2_5V=0
IVREF+=500µA±100µA,Analoginputvoltage≈1.25V,REF2_5V=1
IVREF+=100µA→900µA,
CVREF+=5µF,ax≈0.5×VREF+,Errorofconversionresult≤1LSBREFON=1,
0mA≤IVREF+≤IVREF+maxIVREF+isaconstantintherangeof0mA≤IVREF+≤1mA
IVREF+=0.5mA,CVREF+=10µF,VREF+=1.5V,VAVCC=2.2V
2.2V3V3V
TA
-40°Cto85°C
105°C-40°Cto85°C
105°C
VCC3V2.2V/3V
MIN2.42.371.441.422.22.82.90.010.01
-0.5-1±2±2±2
LSBV
NOM2.52.51.51.5
MAX2.62.641.561.57
VUNIT
VREF+
AVCC(min)
AVCCminimumvoltage,positivebuilt-inreferenceactive
LoadcurrentoutofVREF+terminal
IVREF+
mA
IL(VREF)+
Load-currentregulation,VREF+terminal(1)
LSB
IDL(VREF)+CVREF+TREF+
Loadcurrentregulation,VREF+terminal(2)
CapacitanceatpinVREF+(3)
Temperature
coefficientofbuilt-inreference(2)Settletimeofinternalreferencevoltage(seeFigure39)(4)(2)
3V2.2V/3V2.2V/3V
5
10
20nsµF
±100ppm/°C
tREFON
2.2V17ms
(1)(2)(3)(4)
Notproductiontested,limitscharacterized.Notproductiontested,limitsverifiedbydesign.
Theinternalbufferoperationalamplifierandtheaccuracyspecificationsrequireanexternalcapacitor.AllINLandDNLtestsusestwocapacitorsbetweenpinsVREF+andAVSSandVREF-–/VeREF–andAVSS:10µFtantalumand100nFceramic.
TheconditionisthattheerrorinaconversionstartedaftertREFONislessthan±0.5LSB.Thesettlingtimedependsontheexternalcapacitiveload.
CVREF+100µF10µFtREFON≈.66 x CVREF+[ms] with CVREF+inµF1µF01 ms10 ms100 mstREFONFigure39.TypicalSettlingTimeofInternalReferencetREFONvsExternalCapacitoronVREF+
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From Power Supply
+−10µF100nFDVCCDVSS+−Apply External Reference [VeREF+]or Use Internal Reference [VREF+]
10µF+−10µF+−10µF
100nF100nF100nFAVCCAVSSVREF+or VeREF+Apply External Reference
VREF−/VeREF−Figure40.SupplyVoltageandReferenceVoltageDesignVREF–/VeREF–ExternalSupply
From Power Supply
+−10µF100nFDVCCDVSS+−Apply External Reference [VeREF+]or Use Internal Reference [VREF+]
10µF+−10µFReference Is Internally
Switched toAVSS
100nF100nFAVCCAVSSVREF+or VeREF+VREF−/VeREF−Figure41.SupplyVoltageandReferenceVoltageDesignVREF–/VeREF–=AVSS,InternallyConnected
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12-BitADC,TimingParameters
overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted)
PARAMETER
fADC12CLKfADC12OSC
InternalADC12oscillator
TESTCONDITIONS
ForspecifiedperformanceofADC12linearityparametersADC12DIV=0,
fADC12CLK=fADC12OSC
CVREF+≥5µF,Internaloscillator,fADC12OSC=3.7MHzto6.3MHz
tCONVERT
Conversiontime
ExternalfADC12CLKfromACLK,MCLK,orSMCLK,
ADC12SSEL≉0See
(2)
VCC2.2V/3V2.2V/3V2.2V/3V
MIN0.453.72.06
NOMMAXUNIT
55
6.3MHz6.3MHz3.51
13×
ADC12DIV×1/fADC12CLK
100
µsµsnsns
tADC12ONtSample(1)(2)(3)
Turn-onsettlingtimeoftheADC(1)
Samplingtime(1)
RS=400Ω,RI=1000Ω,CI=30pF,τ=[RS+RI]×CI(3)
3V2.2V
12201400
Limitsverifiedbydesign
TheconditionisthattheerrorinaconversionstartedaftertADC12ONislessthan±0.5LSB.Thereferenceandinputsignalarealreadysettled.
ApproximatelytenTau(τ)areneededtogetanerroroflessthan±0.5LSB:
tSample=ln(2n+1)×(RS+RI)×CI+800ns,wheren=ADCresolution=12,RS=externalsourceresistance
12-BitADC,LinearityParameters
overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted)
PARAMETEREIEDEOEGET
Integrallinearityerror
TESTCONDITIONS
1.4V≤(VeREF+–VREF–/VeREF–)min≤1.6V1.6V<(VeREF+–VREF–/VeREF–)min≤VAVCC
VCC2.2V/3V2.2V/3V2.2V/3V2.2V/3V2.2V/3V
±2±1.1±2
MIN
NOM
MAX±2±1.7±1±4±2±5
UNITLSBLSBLSBLSBLSB
Differentiallinearity(VeREF+–VREF–/VeREF–)min≤(VeREF+–VREF–/VeREF–),errorCVREF+=10µF(tantalum)and100nF(ceramic)OffseterrorGainerrorTotalunadjustederror
(VeREF+–VREF–/VeREF–)min≤(VeREF+–VREF–/VeREF–),InternalimpedanceofsourceRS<100Ω,
CVREF+=10µF(tantalum)and100nF(ceramic)(VeREF+–VREF–/VeREF–)min≤(VeREF+–VREF–/VeREF–),CVREF+=10µF(tantalum)and100nF(ceramic)(VeREF+-–VREF–/VeREF–)min≤(VeREF+–VREF–/VeREF–),CVREF+=10µF(tantalum)and100nF(ceramic)
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12-BitADC,TemperatureSensorandBuilt-InVMID
overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted)
PARAMETER
ISENSORVSENSOR(2)(3)TCSENSOR(3)tSENSOR(sample)(3)IVMIDVMID
tVMID(sample)(1)(2)(3)(4)(5)(6)
Sampletime
requiredifchannel10isselected(4)OperatingsupplycurrentintoAVCCterminal(1)
TESTCONDITIONS
REFON=0,INCH=0Ah,ADC12ON=1,TA=25°C
ADC12ON=1,INCH=0Ah,TA=0°CADC12ON=1,INCH=0AhADC12ON=1,INCH=0Ah,
Errorofconversionresult≤1LSB
VCC2.2V3V2.2V3V2.2V3V2.2V3V2.2V3V2.2V3V2.2V3V
14001220
ns
1.11.5
3030
NANA
1.1±0.041.5±0.04
µs
MIN
TYP40609869863.553.55
3.55±3%3.55±3%
MAX120160
µAUNIT
mVmV/°C
Currentintodivider
ADC12ON=1,INCH=0Bh
atchannel11(5)AVCCdivideratchannel11Sampletime
requiredifchannel11isselected(6)
ADC12ON=1,INCH=0Bh,VMIDis~0.5×VAVCC
ADC12ON=1,INCH=0Bh,
Errorofconversionresult≤1LSB
µAV
ThesensorcurrentISENSORisconsumedif(ADC12ON=1andREFON=1),or(ADC12ON=1ANDINCH=0Ahandsamplesignalishigh).Thereforeitincludestheconstantcurrentthroughthesensorandthereference.
Thetemperaturesensoroffsetcanbeasmuchas±20°C.Asingle-pointcalibrationisrecommendedtominimizetheoffseterrorofthebuilt-intemperaturesensor.Limitscharacterized
Thetypicalequivalentimpedanceofthesensoris51kΩ.Thesampletimerequiredincludesthesensor-ontimetSENSOR(on)Noadditionalcurrentisneeded.TheVMIDisusedduringsampling.
Theon-timetVMID(on)isincludedinthesamplingtimetVMID(sample),noadditionalontimeisneeded.
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FlashMemory
overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)
PARAMETER
VCC(PGM/ERASE)fFTGIPGMIERASEtCPTtCMErasetRetentiontWordtBlock,tBlock,tBlock,
01-63End
TESTCONDITIONS
VCC
MIN2.2257
TYPMAX3.6476
UNITVkHzmAmAmsmscyclesyearstFTGtFTGtFTGtFTGtFTGtFTG
ProgramanderasesupplyvoltageFlashtiminggeneratorfrequencySupplycurrentfromVCCduringprogramSupplycurrentfromVCCduringeraseCumulativeprogramtime(1)CumulativemasserasetimeProgram/EraseenduranceDataretentiondurationWordorbyteprogramtime
BlockprogramtimeforfirstbyteorwordBlockprogramtimeforeachadditionalbyteorword
Blockprogramend-sequencewaittimeMasserasetimeSegmenterasetime
TJ=25°C
(2)(2)(2)(2)(2)(2)
2.2V/3.6V2.2V/3.6V2.2V/3.6V2.2V/3.6V
20104100
11
5710
1053025186105934819
tMassErasetSegErase(1)(2)
Thecumulativeprogramtimemustnotbeexceededwhenwritingtoa64-byteflashblock.Thisparameterappliestoallprogrammingmethods:individualword/bytewriteandblockwritemodes.
Thesevaluesarehardwiredintotheflashcontroller'sstatemachine(tFTG=1/fFTG).
RAM
overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)
PARAMETER
V(RAMh)(1)
RAMretentionsupplyvoltage
(1)
TESTCONDITIONSCPUhalted
MIN1.6
MAXUNITV
ThisparameterdefinestheminimumsupplyvoltageVCCwhenthedatainRAMremainsunchanged.Noprogramexecutionshouldhappenduringthissupplyvoltagecondition.
JTAGInterface
overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)
PARAMETER
fTCKRInternal(1)(2)
TCKinputfrequency
InternalpulldownresistanceonTEST
TESTCONDITIONSSeeSee
(1)(2)
VCC2.2V3V2.2V/3V
MIN0025
TYPMAX
510
UNITMHzkΩ
6090
fTCKmayberestrictedtomeetthetimingrequirementsofthemoduleselected.TMS,TDI/TCLK,andTCKpullupresistorsareimplementedinallversions.
JTAGFuse(1)
overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)
PARAMETER
VCC(FB)VFBIFBtFB(1)
Supplyvoltageduringfuse-blowconditionVoltagelevelonTESTforfuseblowSupplycurrentintoTESTduringfuseblowTimetoblowfuse
TESTCONDITIONS
TA=25°C
MIN2.56
71001MAX
UNITVVmAms
Oncethefuseisblown,nofurtheraccesstotheJTAG/Test,Spy-Bi-Wire,andemulationfeatureispossible,andJTAGisswitchedtobypassmode.
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APPLICATIONINFORMATION
PortP1PinSchematic:P1.0toP1.7,Input/OutputWithSchmittTrigger
P1REN.xDVSSP1DIR.x01P1OUT.xModule X OUTP1SEL.xP1IN.xENModule X INP1IRQ.xP1IFG.xP1SEL.xP1IES.xDP1IE.xQSetEN01P1.0/TACLKP1.1/TA0P1.2/TA1P1.3/TA2P1.4/SMCLKP1.5/TA0P1.6/TA1P1.7/TA2DVCCDirection0: Input1: Output011Pad LogicInterruptEdgeSelectCopyright©2007–2011,TexasInstrumentsIncorporated67
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Table20.PortP1.0toP1.7PinFunctions
PINNAME(P1.x)
x
P1.0(I/O)
P1.0/TACLK
0
Timer_A3.TACLKCAOUTP1.1(I/O)
P1.1/TA0
1
Timer_A3.CCI0ATimer_A3.TA0P1.2(I/O)
P1.2/TA1
2
Timer_A3.CCI1ATimer_A3.TA1P1.3(I/O)
P1.3/TA2
3
Timer_A3.CCI2ATimer_A3.TA2
P1.4/SMCLK
4
P1.4(I/O)SMCLKP1.5(I/O)
P1.5/TA0
5
Timer_A3.CCI0ATimer_A3.TA0P1.6(I/O)
P1.6/TA1
6
Timer_A3.CCI1ATimer_A3.TA1P1.7(I/O)
P1.7/TA2
7
Timer_A3.CCI2ATimer_A3.TA2
FUNCTION
CONTROLBITS/SIGNALSP1DIR.xI:0;O:1
01I:0;O:1
01I:0;O:1
01I:0;O:1
01I:0;O:1
1I:0;O:1
01I:0;O:1
01I:0;O:1
01
P1SEL.x
01101101101101011011011
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MSP430F23xMSP430F24x(1)MSP430F2410
www.ti.com
SLAS547H–JUNE2007–REVISEDAUGUST2011
PortP2PinSchematic:P2.0toP2.4,P2.6,andP2.7,Input/OutputWithSchmittTrigger
Pad LogicTo
Comparator_AFrom
Comparator_A
CAPD.xP2REN.x
DVSSP2DIR.x
01P2OUT.xModule X OUTP2SEL.xP2IN.x
ENModule X INP2IRQ.x
P2IFG.xP2SEL.xP2IES.xDP2IE.xQSetEN01BusKeeperENP2.0/ACLK/CA2P2.1/TAINCLK/CA3P2.2/CAOUT/TA0/CA4P2.3/CA0/TA1P2.4/CA1/TA2P2.6/ADC12CLK/CA6P2.7/TA0/CA7DVCCDirection0: Input1: Output011InterruptEdgeSelectCopyright©2007–2011,TexasInstrumentsIncorporated69
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MSP430F23xMSP430F24x(1)MSP430F2410
SLAS547H–JUNE2007–REVISEDAUGUST2011
www.ti.com
Table21.PortP2.0toP2.4,P2.6,andP2.7PinFunctions
PINNAME(P2.x)
x0
P2.0/ACLK/CA2
1
P2.1/TAINCLK/CA3
P2.0(I/O)ACLKCA2P2.1(I/O)Timer_A3.INCLKDVSSCA32
P2.2/CAOUT/TA0/CA4
P2.2(I/O)CAOUTTA0CA43
P2.3/CA0/TA1
4
P2.4/CA1/TA2
6
P2.6/ADC12CLK(2)/CA6
7
P2.7/TA0/CA7
P2.3(I/O)Timer_A3.TA1CA0P2.4(I/O)Timer_A3.TA2CA1P2.6(I/O)ADC12CLK(2)CA6P2.7(I/O)Timer_A3.TA0CA7
(1)(2)
X=Don'tcare
MSP430F24xandMSP430F23xdevicesonly
FUNCTION
CONTROLBITS/SIGNALS(1)CAPD.x
00100010001001001001001
P2DIR.xI:0;O:1
1XI:0;O:1
01XI:0;O:1
10XI:0;O:1
1XI:0;O:1
1XI:0;O:1
1XI:0;O:1
1X
P2SEL.x
01X011X011X01X0X101X01X
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MSP430F23xMSP430F24x(1)MSP430F2410
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SLAS547H–JUNE2007–REVISEDAUGUST2011
PortP2PinSchematic:P2.5,Input/OutputWithSchmittTrigger
To ComparatorFrom Comparator
CAPD.5To DCODCORP2REN.5
DVSSP2DIR.5
01P2OUT.5Module X OUT
P2SEL.5P2IN.5
ENModule X IN
P2IRQ.5
P2IFG.5P2SEL.5P2IES.5DP2IE.5QSetENDVCCDirection0: Input1: Output011in DCOPad Logic01BusKeeperENP2.5/ROSC/CA5InterruptEdgeSelectTable22.PortP2.5PinFunctions
PINNAME(P2.x)
x
P2.5(I/O)
P2.5/ROSC/CA5
5
ROSCDVSSCA5
(1)
X=Don'tcare
FUNCTION
CONTROLBITS/SIGNALS(1)
CAPD0001orselected
DCOR0100
P2DIR.5I:0;O:1
X1X
P2SEL.5
0X1X
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MSP430F23xMSP430F24x(1)MSP430F2410
SLAS547H–JUNE2007–REVISEDAUGUST2011
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PortP3PinSchematic:P3.0toP3.7,Input/OutputWithSchmittTrigger
P3REN.xDVSSP3DIR.xModule direction0101P3.0/UCB0STE/UCA0CLKP3.1/UCB0SIMO/UCB0SDAP3.2/UCB0SOMI/UCB0SCLP3.3/UCB0CLK/UCA0STEP3.4/UCA0TXD/UCA0SIMOP3.5/UCA0RXD/UCA0SOMIP3.6/UCA1TXD/UCA1SIMOP3.7/UCA1RXD/UCA1SOMIDVCCDirection0: Input1: Output011Pad LogicP3OUT.xModule X OUTP3SEL.xP3IN.xENModule X INDTable23.PortP3.0toP3.7PinFunctions
PINNAME(P3.x)
x
P3.0(I/O)
UCB0STE/UCA0CLK(2)(3)P3.1(I/O)
UCB0SIMO/UCB0SDA(2)(4)P3.2(I/O)
UCB0SOMI/UCB0SCL(2)(4)P3.3(I/O)
UCB0CLK/UCA0STEP3.4(I/O)
UCA0TXD/UCA0SIMOP3.5(I/O)
UCA0RXD/UCA0SOMIP3.6(I/O)
UCA1TXD(5)/UCA1SIMO(5)(2)P3.7(I/O)
UCA1RXD(5)/UCA1SOMI(5)(2)
(2)(2)(2)
FUNCTION
CONTROLBITS/SIGNALS(1)P3DIR.x
P3SEL.x
0101010101010101
I:0;O:1
XI:0;O:1
XI:0;O:1
XI:0;O:1
XI:0;O:1
XI:0;O:1
XI:0;O:1
XI:0;O:1
X
P3.0/UCB0STE/UCA0CLKP3.1/UCB0SIMO/UCB0SDAP3.2/UCB0SOMI/UCB0SCLP3.3/UCB0CLK/UCA0STEP3.4/UCA0TXD/UCA0SIMOP3.5/UCA0RXD/UCA0SOMIP3.6/UCA1TXD(5)/UCA1SIMO(5)P3.7/UCA1RXD(5)/UCA1SOMI(5)(1)(2)(3)(4)(5)
01234567
X=Don'tcare
ThepindirectioniscontrolledbytheUSCImodule.
UCA0CLKfunctiontakesprecedenceoverUCB0STEfunction.IfthepinisrequiredasUCA0CLKinputoroutput,USCIA/B0isforcedto3-wireSPImodeif4-wireSPImodeisselected.
IfI2Cfunctionalityisselected,theoutputdrivesonlythelogical0toVSSlevel.MSP430F24xandMSP430F24x1devicesonly
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MSP430F23xMSP430F24x(1)MSP430F2410
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SLAS547H–JUNE2007–REVISEDAUGUST2011
PortP4PinSchematic:P4.0toP4.7,Input/OutputWithSchmittTrigger
P4REN.x
DVSSP4DIR.x
01DVCCDirection0: Input1: Output011Pad LogicP4OUT.xModule X OUT
P4SEL.xP4IN.x
01P4.0/TB0P4.1/TB1P4.2/TB2P4.3/TB3P4.4/TB4P4.5/TB5P4.6/TB6P4.7/TBCLKENModule X INDTable24.PortP4.0toP4.7PinFunctions
PINNAME(P4.x)
x
P4.0(I/O)
P4.0/TB0
0
Timer_B7.CCI0AandTimer_B7.CCI0BTimer_B7.TB0P4.1(I/O)
P4.1/TB1
1
Timer_B7.CCI1AandTimer_B7.CCI1BTimer_B7.TB1P4.2(I/O)
P4.2/TB2
2
Timer_B7.CCI2AandTimer_B7.CCI2BTimer_B7.TB2P4.3(I/O)
P4.3/TB3(1)
3
Timer_B7.CCI3AandTimer_B7.CCI3B(1)Timer_B7.TB3(1)P4.4(I/O)
P4.4/TB4(1)
4
Timer_B7.CCI4AandTimer_B7.CCI4B(1)Timer_B7.TB4(1)P4.5(I/O)
P4.5/TB5(1)
5
Timer_B7.CCI5AandTimer_B7.CCI5B(1)Timer_B7.TB5(1)P4.6(I/O)
P4.6/TB6(1)
6
Timer_B7.CCI6AandTimer_B7.CCI6B(1)Timer_B7.TB6(1)
P4.7/TBCLK(1)
7
P4.7(I/O)Timer_B7.TBCLK
FUNCTION
CONTROLBITS/SIGNALSP4DIR.xI:0;O:1
01I:0;O:1
01I:0;O:1
01I:0;O:1
01I:0;O:1
01I:0;O:1
01I:0;O:1
01I:0;O:1
0
P4SEL.x
01101101101101101101101
MSP430F24xandMSP430F24x1devicesonly
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MSP430F23xMSP430F24x(1)MSP430F2410
SLAS547H–JUNE2007–REVISEDAUGUST2011
www.ti.com
PortP5PinSchematic:P5.0toP5.3,Input/OutputWithSchmittTrigger
P5REN.x
DVSSP5DIR.x
Module Direction
0101P5.0/UCB1STE/UCA1CLKP5.1/UCB1SIMO/UCB1SDAP5.2/UCB1SOMI/UCB1SCLP5.3/UCB1CLK/UCA1STEENModule X IN
DDVCCDirection0: Input1: Output011Pad LogicP5OUT.xModule X OUTP5SEL.xP5IN.x
Table25.PortP5.0toP5.3PinFunctions
PINNAME(P5.x)
x0123
P5.0(I/O)
UCB1STE(2)/UCA1CLK(2)(3)(4)P5.1(I/O)
UCB1SIMO(2)/UCB1SDA(2)(3)(5)P5.2(I/O)
UCB1SOMI(2)/UCB1SCL(2)(3)(5)P5.3(I/O)
UCB1CLK(2)/UCA1STE(2)(3)
FUNCTION
CONTROLBITS/SIGNALS(1)P5DIR.x
P5.0/UCB1STE(2)/UCA1CLK(2)P5.1/UCB1SIMO(2)/UCB1SDA(2)P5.2/UCB1SOMI(2)/UCB1SCL(2)P5.3/UCB1CLK(2)/UCA1STE(2)(1)(2)(3)(4)(5)
I:0;O:1
XI:0;O:1
XI:0;O:1
XI:0;O:1
X
P5SEL.x
01010101
X=Don'tcare
MSP430F24xandMSP430F24x1devicesonlyThepindirectioniscontrolledbytheUSCImodule.
UCA0CLKfunctiontakesprecedenceoverUCB0STEfunction.IfthepinisrequiredasUCA0CLKinputoroutput,USCIA/B0isforcedto3-wireSPImodeif4-wireSPImodeisselected.
IfI2Cfunctionalityisselected,theoutputdrivesonlythelogical0toVSSlevel.
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MSP430F23xMSP430F24x(1)MSP430F2410
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SLAS547H–JUNE2007–REVISEDAUGUST2011
PortP5PinSchematic:P5.4toP5.7,Input/OutputWithSchmittTrigger
P5REN.x
DVSSP5DIR.x
0101P5.4/MCLKP5.5/SMCLKP5.6/ACLKP5.7/TBOUTH/SVSOUTENModule X IN
DDVCCDirection0: Input1: Output011Pad LogicP5OUT.xModule X OUT
P5SEL.xP5IN.x
Table26.PortP5.4toP5.7PinFunctions
PINNAME(P5.x)P5.4/MCLKP5.5/SMCLKP5.6/ACLK
x456
P5.4(I/O)MCLKP5.5(I/O)SMCLKP5.6(I/O)ACLKP5.7(I/O)
P5.7/TBOUTH/SVSOUT
7
Timer_B7.TBOUTHSVSOUT
FUNCTION
CONTROLBITS/SIGNALSP5DIR.xI:0;O:1
1I:0;O:1
1I:0;O:1
1I:0;O:1
01
P5SEL.x
010101011
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MSP430F23xMSP430F24x(1)MSP430F2410
SLAS547H–JUNE2007–REVISEDAUGUST2011
www.ti.com
PortP6PinSchematic:P6.0toP6.6,Input/OutputWithSchmittTrigger
Pad LogicADC12AxFromADC12
P6REN.x
DVSSP6DIR.x
01P6OUT.xModule X OUT
P6SEL.xP6IN.x
ENModule X IN
D01BusKeeperENP6.0/A0P6.1/A1P6.2/A2P6.3/A3P6.4/A4P6.5/A5P6.6/A6DVCCDirection0: Input1: Output011Table27.PortP6.0toP6.6PinFunctions
PINNAME(P6.x)
x
P5.0(I/O)A0A1
(2)
FUNCTION
CONTROLBITS/SIGNALS(1)P6DIR.x
P6SEL.x
01010101010101
I:0;O:1
XI:0;O:1
XI:0;O:1
XI:0;O:1
XI:0;O:1
XI:0;O:1
XI:0;O:1
X
P6.0/A0(2)P6.1/A1(2)P6.2/A2(2)P6.3/A3(2)P6.4/A4(2)P6.5/A5(2)P6.6/A6(2)(1)(2)
0123456
P5.1(I/O)
(2)
P5.2(I/O)A2(2)P5.3(I/O)A3(2)P5.4(I/O)A4(2)P5.5(I/O)A5(2)P6.6(I/O)A6(2)
X=Don'tcare
MSP430F24xandMSP430F23xdevicesonly
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MSP430F23xMSP430F24x(1)MSP430F2410
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SLAS547H–JUNE2007–REVISEDAUGUST2011
PortP6PinSchematic:P6.7,Input/OutputWithSchmittTrigger
Pad LogicTo SVS MuxVLD = 15ADC12A7FromADC12
P6REN.7
DVSSP6DIR.7
01P6OUT.7Module X OUT
P6SEL.7P6IN.7
ENModule X IN
D01BusKeeperENP6.7/A7/SVSINDVCCDirection0: Input1: Output011Table28.PortP6.7PinFunctions
PINNAME(P6.x)
x
P6.7(I/O)
P6.7/A7/SVSIN
7
DVSSA7
(2)
FUNCTION
CONTROLBITS/SIGNALS(1)P6DIR.xI:0;O:1
1XX
P6SEL.x
01XX
INCHy001(y=7)
1
SVSIN(VLD=15)
(1)(2)
X=Don'tcare
MSP430F24xandMSP430F23xdevicesonly
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MSP430F23xMSP430F24x(1)MSP430F2410
SLAS547H–JUNE2007–REVISEDAUGUST2011
www.ti.com
JTAGPins(TMS,TCK,TDI/TCLK,TDO/TDI),Input/OutputWithSchmittTrigger
TDOControlled by JTAGControlled by JTAGJTAGControlledby JTAGTDIDVCCDVCCTDO/TDIFuseBurn &TestFuseTestandEmulationModuleDVCCTMSTMSDVCCTCKTCKDuring ProgrammingActivity andDuring Blowing of the Fuse, PinTDO/TDI Is Used toApply theTestInput Data for JTAG Circuitry
TDI/TCLK78Copyright©2007–2011,TexasInstrumentsIncorporated
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MSP430F23xMSP430F24x(1)MSP430F2410
www.ti.com
SLAS547H–JUNE2007–REVISEDAUGUST2011
JTAGFuseCheckMode
MSP430devicesthathavethefuseontheTESTterminalhaveafusecheckmodethatteststhecontinuityofthefusethefirsttimetheJTAGportisaccessedafterapower-onreset(POR).Whenactivated,afusecheckcurrent,ITF,of1mAat3V,2.5mAat5VcanflowfromtheTESTpintogroundifthefuseisnotburned.Caremustbetakentoavoidaccidentallyactivatingthefusecheckmodeandincreasingoverallsystempowerconsumption.
WhentheTESTpinisagaintakenlowafteratestorprogrammingsession,thefusecheckmodeandsensecurrentsareterminated.
ActivationofthefusecheckmodeoccurswiththefirstnegativeedgeontheTMSpinafterpoweruporifTMSisbeingheldlowduringpowerup.ThesecondpositiveedgeontheTMSpindeactivatesthefusecheckmode.Afterdeactivation,thefusecheckmoderemainsinactiveuntilanotherPORoccurs.AftereachPORthefusecheckmodehasthepotentialtobeactivated.
ThefusecheckcurrentflowsonlywhenthefusecheckmodeisactiveandtheTMSpinisinalowstate(seeFigure42).Therefore,theadditionalcurrentflowcanbepreventedbyholdingtheTMSpinhigh(defaultcondition).
TimeTMS Goes LowAfter PORTMS
ITFITDI/TCLK
Figure42.FuseCheckModeCurrent
NOTE
TheCODEandRAMdataprotectionisensurediftheJTAGfuseisblownandthe256-bitbootloaderaccesskeyisused.Also,seetheBootstrapLoadersectionformoreinformation.
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MSP430F23xMSP430F24x(1)MSP430F2410
SLAS547H–JUNE2007–REVISEDAUGUST2011
www.ti.com
REVISIONHISTORY
LITERATURENUMBERSLAS547SLAS547A
ProductPreviewreleaseProductionDatarelease
Correctedterminalnamesanddescriptionsforpins34and35in\"TerminalFunctions-MSP430F23x\"(page9)Correctedterminalnamesforpins13,14,and15in\"TerminalFunctions-MSP430F24x1\"(page13)
CorrectedinterruptsourceandflagentriesforUSCI_A1/USCI_B1in\"interruptvectoraddresses\"table(page17)Changedindexvaluesfrom1-3to0-2inFigures23to26(pages52and54)Changedfmax,BITCLKandtτparametersin\"USCI(UARTmode)\"table(page56)Corrected\"PortP1.0toP1.7pinfunctions\"table(page72)
RemovedincorrectCAPD.xcolumnin\"PortP6.0toP6.6pinfunctions\"table(page80)
AddedDevelopmentToolSupportsection(page2)
Updatedparametricvaluesin\"low-powermodesupplycurrentintoVCCexcludingexternalcurrent\"table(page34)UpdatednotesandtCMEraseMINvalue\"flashmemory\"table(page34)Changedlimitsontd(SVSon)parameter(page41)Changed\"Port6.0to6.6PinFunctions\"table(page77)Changed\"Port6.7PinFunctions\"table(page78)
ChangedTstg,Programmeddevice,to-55°Cto150°CinAbsoluteMaximumRatings
CorrectedformattingerrorofTAcolumninActiveModeSupplyCurrent(bothIAM,1MHzparameters)andinLow-Power-ModeSupplyCurrents(ILPM0,1MHzandILPM0,100kHzparameters)
SUMMARY
SLAS547B
SLAS547CSLAS547DSLAS547ESLAS547FSLAS547GSLAS547H
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PACKAGE OPTION ADDENDUM
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2-Apr-2012
PACKAGING INFORMATION
Orderable DeviceMSP430F233TPMMSP430F233TPMRMSP430F233TRGCMSP430F233TRGCRMSP430F233TRGCTMSP430F235TPMMSP430F235TPMRMSP430F235TRGCMSP430F235TRGCRMSP430F235TRGCTMSP430F2410TPMMSP430F2410TPMRMSP430F2410TRGCMSP430F2410TRGCRMSP430F2410TRGCTMSP430F2471TPMMSP430F2471TPMRMSP430F2471TRGC
Status
(1)
Package TypePackage
Drawing
LQFPLQFPVQFNVQFNVQFNLQFPLQFPVQFNVQFNVQFNLQFPLQFPVQFNVQFNVQFNLQFPLQFPVQFN
PMPMRGCRGCRGCPMPMRGCRGCRGCPMPMRGCRGCRGCPMPMRGC
Pins646464646464646464646464646464646464
Package Qty
1601000
Eco Plan
(2)
Lead/Ball Finish
MSL Peak Temp
(3)
Samples(Requires Login)
ACTIVEACTIVEOBSOLETEACTIVEACTIVEACTIVEACTIVEOBSOLETEACTIVEACTIVEACTIVEACTIVEOBSOLETEACTIVEACTIVEACTIVEACTIVEOBSOLETE
Green (RoHS& no Sb/Br)Green (RoHS& no Sb/Br)
TBDGreen (RoHS& no Sb/Br)Green (RoHS& no Sb/Br)Green (RoHS& no Sb/Br)Green (RoHS& no Sb/Br)
TBDGreen (RoHS& no Sb/Br)Green (RoHS& no Sb/Br)Green (RoHS& no Sb/Br)Green (RoHS& no Sb/Br)
TBDGreen (RoHS& no Sb/Br)Green (RoHS& no Sb/Br)Green (RoHS& no Sb/Br)Green (RoHS& no Sb/Br)
TBD
CU NIPDAULevel-3-260C-168 HRCU NIPDAULevel-3-260C-168 HRCall TI
Call TI
25002501601000
CU NIPDAULevel-3-260C-168 HRCU NIPDAULevel-3-260C-168 HRCU NIPDAULevel-3-260C-168 HRCU NIPDAULevel-3-260C-168 HRCall TI
Call TI
25002501601000
CU NIPDAULevel-3-260C-168 HRCU NIPDAULevel-3-260C-168 HRCU NIPDAULevel-3-260C-168 HRCU NIPDAULevel-3-260C-168 HRCall TI
Call TI
25002501601000
CU NIPDAULevel-3-260C-168 HRCU NIPDAULevel-3-260C-168 HRCU NIPDAULevel-3-260C-168 HRCU NIPDAULevel-3-260C-168 HRCall TI
Call TI
Addendum-Page 1
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PACKAGE OPTION ADDENDUM
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2-Apr-2012
Orderable DeviceMSP430F2471TRGCRMSP430F2471TRGCTMSP430F247TPMMSP430F247TPMRMSP430F247TRGCMSP430F247TRGCRMSP430F247TRGCTMSP430F2481TPMMSP430F2481TPMRMSP430F2481TRGCMSP430F2481TRGCRMSP430F2481TRGCTMSP430F248TPMMSP430F248TPMRMSP430F248TRGCMSP430F248TRGCRMSP430F248TRGCTMSP430F2491TPMMSP430F2491TPMR
Status
(1)
Package TypePackage
Drawing
VQFNVQFNLQFPLQFPVQFNVQFNVQFNLQFPLQFPVQFNVQFNVQFNLQFPLQFPVQFNVQFNVQFNLQFPLQFP
RGCRGCPMPMRGCRGCRGCPMPMRGCRGCRGCPMPMRGCRGCRGCPMPM
Pins64646464646464646464646464646464646464
Package Qty
25002501601000
Eco Plan
(2)
Lead/Ball Finish
MSL Peak Temp
(3)
Samples(Requires Login)
ACTIVEACTIVEACTIVEACTIVEOBSOLETEACTIVEACTIVEACTIVEACTIVEOBSOLETEACTIVEACTIVEACTIVEACTIVEOBSOLETEACTIVEACTIVEACTIVEACTIVE
Green (RoHS& no Sb/Br)Green (RoHS& no Sb/Br)Green (RoHS& no Sb/Br)Green (RoHS& no Sb/Br)
TBDGreen (RoHS& no Sb/Br)Green (RoHS& no Sb/Br)Green (RoHS& no Sb/Br)Green (RoHS& no Sb/Br)
TBDGreen (RoHS& no Sb/Br)Green (RoHS& no Sb/Br)Green (RoHS& no Sb/Br)Green (RoHS& no Sb/Br)
TBDGreen (RoHS& no Sb/Br)Green (RoHS& no Sb/Br)Green (RoHS& no Sb/Br)Green (RoHS& no Sb/Br)
CU NIPDAULevel-3-260C-168 HRCU NIPDAULevel-3-260C-168 HRCU NIPDAULevel-3-260C-168 HRCU NIPDAULevel-3-260C-168 HRCall TI
Call TI
25002501601000
CU NIPDAULevel-3-260C-168 HRCU NIPDAULevel-3-260C-168 HRCU NIPDAULevel-3-260C-168 HRCU NIPDAULevel-3-260C-168 HRCall TI
Call TI
25002501601000
CU NIPDAULevel-3-260C-168 HRCU NIPDAULevel-3-260C-168 HRCU NIPDAULevel-3-260C-168 HRCU NIPDAULevel-3-260C-168 HRCall TI
Call TI
25002501601000
CU NIPDAULevel-3-260C-168 HRCU NIPDAULevel-3-260C-168 HRCU NIPDAULevel-3-260C-168 HRCU NIPDAULevel-3-260C-168 HR
Addendum-Page 2
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PACKAGE OPTION ADDENDUM
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2-Apr-2012
Orderable DeviceMSP430F2491TRGCMSP430F2491TRGCRMSP430F2491TRGCTMSP430F249TPMMSP430F249TPMRMSP430F249TRGCMSP430F249TRGCRMSP430F249TRGCT
(1)
Status
(1)
Package TypePackage
Drawing
VQFNVQFNVQFNLQFPLQFPVQFNVQFNVQFN
RGCRGCRGCPMPMRGCRGCRGC
Pins6464646464646464
Package Qty
Eco Plan
TBD
(2)
Lead/Ball FinishCall TI
MSL Peak Temp Call TI
(3)
Samples(Requires Login)
OBSOLETEACTIVEACTIVEACTIVEACTIVEOBSOLETEACTIVEACTIVE
25002501601000
Green (RoHS& no Sb/Br)Green (RoHS& no Sb/Br)Green (RoHS& no Sb/Br)Green (RoHS& no Sb/Br)
TBDGreen (RoHS& no Sb/Br)Green (RoHS& no Sb/Br)
CU NIPDAULevel-3-260C-168 HRCU NIPDAULevel-3-260C-168 HRCU NIPDAULevel-3-260C-168 HRCU NIPDAULevel-3-260C-168 HRCall TI
Call TI
2500250
CU NIPDAULevel-3-260C-168 HRCU NIPDAULevel-3-260C-168 HR
The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availabilityinformation and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms \"Lead-Free\" or \"Pb-Free\" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement thatlead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used betweenthe die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines \"Green\" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weightin homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on informationprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 3
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PACKAGE OPTION ADDENDUM
www.ti.com
2-Apr-2012
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF MSP430F249 :
•Enhanced Product: MSP430F249-EP
NOTE: Qualified Version Definitions:
•Enhanced Product - Supports Defense, Aerospace and Medical Applications
Addendum-Page 4
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PACKAGEMATERIALSINFORMATION
www.ti.com
14-Jul-2012
TAPEANDREELINFORMATION
*Alldimensionsarenominal
Device
PackagePackagePinsTypeDrawingLQFPLQFPLQFPLQFPLQFPLQFPLQFPLQFPLQFPLQFPLQFPLQFPLQFPLQFPLQFPLQFPLQFPLQFP
PMPMPMPMPMPMPMPMPMPMPMPMPMPMPMPMPMPM
646464646464646464646464646464646464
SPQ
ReelReelA0DiameterWidth(mm)(mm)W1(mm)330.0330.0330.0330.0330.0330.0330.0330.0330.0330.0330.0330.0330.0330.0330.0330.0330.0330.0
24.424.424.424.424.424.424.424.424.424.424.424.424.424.424.424.424.424.4
13.013.013.013.013.013.013.013.013.013.013.013.013.013.013.013.013.013.0
B0(mm)13.013.013.013.013.013.013.013.013.013.013.013.013.013.013.013.013.013.0
K0(mm)2.12.12.12.12.12.12.12.12.12.12.12.12.12.12.12.12.12.1
P1(mm)16.016.016.016.016.016.016.016.016.016.016.016.016.016.016.016.016.016.0
WPin1(mm)Quadrant24.024.024.024.024.024.024.024.024.024.024.024.024.024.024.024.024.024.0
Q2Q2Q2Q2Q2Q2Q2Q2Q2Q2Q2Q2Q2Q2Q2Q2Q2Q2
MSP430F233TPMRMSP430F233TPMRMSP430F235TPMRMSP430F235TPMRMSP430F2410TPMRMSP430F2410TPMRMSP430F2471TPMRMSP430F2471TPMRMSP430F247TPMRMSP430F247TPMRMSP430F2481TPMRMSP430F2481TPMRMSP430F248TPMRMSP430F248TPMRMSP430F2491TPMRMSP430F2491TPMRMSP430F249TPMRMSP430F249TPMR
100010001000100010001000100010001000100010001000100010001000100010001000
PackMaterials-Page1
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PACKAGEMATERIALSINFORMATION
www.ti.com
14-Jul-2012
*Alldimensionsarenominal
DeviceMSP430F233TPMRMSP430F233TPMRMSP430F235TPMRMSP430F235TPMRMSP430F2410TPMRMSP430F2410TPMRMSP430F2471TPMRMSP430F2471TPMRMSP430F247TPMRMSP430F247TPMRMSP430F2481TPMRMSP430F2481TPMRMSP430F248TPMRMSP430F248TPMRMSP430F2491TPMRMSP430F2491TPMRMSP430F249TPMRMSP430F249TPMR
PackageType
LQFPLQFPLQFPLQFPLQFPLQFPLQFPLQFPLQFPLQFPLQFPLQFPLQFPLQFPLQFPLQFPLQFPLQFP
PackageDrawing
PMPMPMPMPMPMPMPMPMPMPMPMPMPMPMPMPMPM
Pins646464646464646464646464646464646464
SPQ100010001000100010001000100010001000100010001000100010001000100010001000
Length(mm)
367.0336.6367.0336.6367.0336.6367.0336.6336.6367.0336.6367.0336.6367.0367.0336.6367.0336.6
Width(mm)367.0336.6367.0336.6367.0336.6367.0336.6336.6367.0336.6367.0336.6367.0367.0336.6367.0336.6
Height(mm)
45.041.345.041.345.041.345.041.341.345.041.345.041.345.045.041.345.041.3
PackMaterials-Page2
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MTQF008A – JANUARY 1995 – REVISED DECEMBER 1996 MECHANICAL DATA PM (S-PQFP-G64) 0,270,174833PLASTIC QUAD FLATPACK0,500,08M493264170,13 NOM17,50 TYP10,20SQ9,8012,20SQ11,801,451,3516Gage Plane0,250,05 MIN0°–7°0,750,45Seating Plane1,60 MAX0,084040152/C 11/96NOTES:A.B.C.D.All linear dimensions are in millimeters.This drawing is subject to change without notice.Falls within JEDEC MS-026May also be thermally enhanced plastic with leads connected to the die pads.POST OFFICE BOX 655303 DALLAS, TEXAS 75265•1芯天下--http://oneic.com/芯天下--http://oneic.com/
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OnlythoseTIcomponentswhichTIhasspecificallydesignatedasmilitarygradeor“enhancedplastic”aredesignedandintendedforuseinmilitary/aerospaceapplicationsorenvironments.BuyeracknowledgesandagreesthatanymilitaryoraerospaceuseofTIcomponentswhichhavenotbeensodesignatedissolelyattheBuyer'srisk,andthatBuyerissolelyresponsibleforcompliancewithalllegalandregulatoryrequirementsinconnectionwithsuchuse.
TIhasspecificallydesignatedcertaincomponentswhichmeetISO/TS16949requirements,mainlyforautomotiveuse.Componentswhichhavenotbeensodesignatedareneitherdesignednorintendedforautomotiveuse;andTIwillnotberesponsibleforanyfailureofsuchcomponentstomeetsuchrequirements.ProductsAudioAmplifiersDataConvertersDLP®ProductsDSP
ClocksandTimersInterfaceLogicPowerMgmtMicrocontrollersRFID
OMAPMobileProcessorsWirelessConnectivity
www.ti.com/audioamplifier.ti.comdataconverter.ti.comwww.dlp.comdsp.ti.comwww.ti.com/clocksinterface.ti.comlogic.ti.compower.ti.commicrocontroller.ti.comwww.ti-rfid.comwww.ti.com/omap
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