CS8420
Digital Audio Sample Rate Converter
Features
Complete IEC60958, AES3, S/PDIF, EIAJ
General Description
The CS8420 is a stereo digital audio sample rate con-verter (SRC) with AES3-type and serial digital audioinputs, AES3-type and serial digital audio outputs, andincludes comprehensive control ability via a 4-wire mi-crocontroller port. Channel status and user data can beassembled in block-sized buffers, makingread/modify/writecycles easy.
Digital audio inputs and outputs may be 24, 20, or 16bits. The input data can be completely asynchronous tothe output data, with the output data being synchronousto an external system clock.
The CS8420 is available in a 28-pin SOIC package inboth Commercial (-10º to +70º C) and Automotivegrades (-40º to +85º C). The CDB8420 Customer Dem-onstration board is also available for device evaluationand implementation suggestions.
Please refer to “Ordering Information” on page93 for or-dering information.
Target applications include CD-R, DAT, MD, DVD andVTR equipment, mixing consoles, digital audio trans-mission equipment, high-quality D/A and A/Dconverters, effects processors, and computer audiosystems.
VD+DGNDCP1201-compatible Transceiver with Asynchronous Sample Rate Converter
Flexible 3-wire Serial Digital I/O Ports8-kHz to 108-kHz Sample Rate Range1:3 and 3:1 Maximum Input to Output Sample
Rate Ratio
128dB Dynamic Range-117dB THD+N at 1kHz
Excellent Performance at Almost a 1:1 RatioExcellent Clock Jitter Rejection24-bit I/O Words
Pin and Microcontroller Read/Write Access to
Channel Status and User Data
Microcontroller and Stand-Alone Modes
VA+AGNDFILTRERRRMCKILRCKISCLKSDINSerialAudioInputSampleRateConverterSerialAudioOutputOLRCKOSCLKSDOUTRXPReceiverRXNClock&DataRecoveryAES3S/PDIFDecoderC&UbitDataBufferAES3S/PDIFEncoderTXPDriverTXNMisc.ControlControlPort&RegistersOutputClockGeneratorH/SRSTEMPHUTCBLSDA/SCL/AD1/AD0/INTCDOUTCCLKCDINCSOMCKhttp://www.cirrus.comCopyright © Cirrus Logic, Inc. 2007(All Rights Reserved)APRIL '07DS245F4元器件交易网www.cecb2b.com
CS8420
TABLE OF CONTENTS
1. CHARACTERISTICS AND SPECIFICATIONS ......................................................................................6SPECIFIED OPERATING CONDITIONS ..............................................................................................6ABSOLUTE MAXIMUM RATINGS ........................................................................................................6PERFORMANCE SPECIFICATIONS ....................................................................................................7DIGITAL FILTER CHARACTERISTICS .................................................................................................7DC ELECTRICAL SPECIFICATIONS ....................................................................................................7DIGITAL INPUT CHARACTERISTICS ..................................................................................................8DIGITAL INTERFACE SPECIFICATIONS .............................................................................................8TRANSMITTER CHARACTERISTICS ..................................................................................................8SWITCHING CHARACTERISTICS .......................................................................................................8SWITCHING CHARACTERISTICS - SERIAL AUDIO PORTS ..............................................................9SWITCHING CHARACTERISTICS - CONTROL PORT - SPI™ MODE .............................................10SWITCHING CHARACTERISTICS - CONTROL PORT - I²C® MODE ...............................................112. TYPICAL CONNECTION DIAGRAM ...................................................................................................123. GENERAL DESCRIPTION ...................................................................................................................134. DATA I/O FLOW AND CLOCKING OPTIONS .....................................................................................145. SAMPLE RATE CONVERTER (SRC) ..................................................................................................185.1 Dither .............................................................................................................................................185.2 SRC Locking, Varispeed and the Sample Rate Ratio Register .....................................................186. THREE-WIRE SERIAL AUDIO PORTS ...............................................................................................197. AES3 TRANSMITTER AND RECEIVER ..............................................................................................227.1 AES3 Receiver ...............................................................................................................................22
7.1.1 PLL, Jitter Attenuation, and Varispeed ..................................................................................227.1.2 OMCK Out On RMCK ...........................................................................................................227.1.3 Error Reporting and Hold Function ........................................................................................227.1.4 Channel Status Data Handling ..............................................................................................237.1.5 User Data Handling ...............................................................................................................237.1.6 Non-Audio Auto Detection .....................................................................................................247.2 AES3 Transmitter ...........................................................................................................................24
7.2.1 Transmitted Frame and Channel Status Boundary Timing ...................................................247.2.2 TXN and TXP Drivers ............................................................................................................257.3 Mono Mode Operation ...................................................................................................................258. AES3 TRANSMITTER AND RECEIVER ..............................................................................................288.1 Sample Rate Converter .................................................................................................................288.2 Non-SRC Delay .............................................................................................................................299. CONTROL PORT DESCRIPTION AND TIMING .................................................................................309.1 SPI Mode .......................................................................................................................................309.2 I²C Mode ........................................................................................................................................319.3 Interrupts ........................................................................................................................................3110. CONTROL PORT REGISTER BIT DEFINITIONS .............................................................................3210.1 Memory Address Pointer (MAP) ..................................................................................................3210.2 Miscellaneous Control 1 (01h) .....................................................................................................3410.3 Miscellaneous Control 2 (02h) .....................................................................................................3510.4 Data Flow Control (03h) ...............................................................................................................3610.5 Clock Source Control (04h) ..........................................................................................................3710.6 Serial Audio Input Port Data Format (05h) ...................................................................................3810.7 Serial Audio Output Port Data Format (06h) ................................................................................3910.8 Interrupt 1 Register Status (07h) (Read Only) .............................................................................4010.9 Interrupt Register 2 Status (08h) (Read Only) .............................................................................4110.10 Interrupt 1 Register Mask (09h) .................................................................................................4110.11 Interrupt Register 1 Mode Registers MSB & LSB (0Ah,0Bh) .....................................................4110.12 Interrupt 2 Register Mask (0Ch) .................................................................................................42
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CS8420
10.13 Interrupt Register 2 Mode Registers MSB & LSB (0Dh,0Eh) .....................................................4210.14 Receiver Channel Status (0Fh) (Read Only) .............................................................................4310.15 Receiver Error (10h) (Read Only) ..............................................................................................4410.16 Receiver Error Mask (11h) .........................................................................................................4510.17 Channel Status Data Buffer Control (12h) .................................................................................4510.18 User Data Buffer Control (13h) ..................................................................................................4610.19 Sample Rate Ratio (1Eh) (Read Only) .......................................................................................4710.20 C-Bit or U-Bit Data Buffer (20h - 37h) ........................................................................................4710.21 CS8420 I.D. and Version Register (7Fh) (Read Only) ...............................................................4711. SYSTEM AND APPLICATIONS ISSUES ...........................................................................................4811.1 Reset, Power Down and Start-up Options ...................................................................................4811.2 Transmitter Startup ......................................................................................................................4811.3 SRC Invalid State .........................................................................................................................4911.4 C/U Buffer Data Corruption ..........................................................................................................4911.5 Block-Mode U-Data D-to-E Buffer Transfers ...............................................................................5011.6 ID Code and Revision Code ........................................................................................................5011.7 Power Supply, Grounding, and PCB layout .................................................................................5011.8 Synchronization of Multiple CS8420s ..........................................................................................5011.9 Extended Range Sample Rate Conversion .................................................................................5012. SOFTWARE MODE - PIN DESCRIPTION .........................................................................................5113. HARDWARE MODES .........................................................................................................................5513.1 Overall Description .......................................................................................................................55
13.1.1 Hardware Mode Definitions .................................................................................................5513.1.2 Serial Audio Port Formats ...................................................................................................5513.2 Hardware Mode 1 Description (DEFAULT Data Flow, AES3 Input) ............................................56
13.2.1 Pin Description - Hardware Mode 1 ....................................................................................5713.3 Hardware Mode 2 Description .....................................................................................................59
13.3.1 Pin Description - Hardware Mode 2 ....................................................................................6113.4 Hardware Mode 3 Description .....................................................................................................63
13.4.1 Pin Description - Hardware Mode 3 ....................................................................................6513.5 Hardware Mode 4 Description .....................................................................................................67
13.5.1 Pin Description - Hardware Mode 4 ....................................................................................6913.6 Hardware Mode 5 Description .....................................................................................................71
13.6.1 Pin Description - Hardware Mode 5 ....................................................................................7213.7 Hardware Mode 6 Description .....................................................................................................74
13.7.1 Pin Description - Hardware Mode 6 ....................................................................................76
14. EXTERNAL AES3/SPDIF/IEC60958 TRANSMITTER AND RECEIVER COMPONENTS ................7814.1 AES3 Transmitter External Components .....................................................................................7814.2 AES3 Receiver External Components .........................................................................................7914.3 Isolating Transformer Requirements ............................................................................................8015. CHANNEL STATUS AND USER DATA BUFFER MANAGEMENT ..................................................8115.1 AES3 Channel Status(C) Bit Management ..................................................................................81
15.1.1 Manually Accessing the E Buffer .........................................................................................8215.1.2 Reserving the First 5 Bytes in the E Buffer .........................................................................8315.1.3 Serial Copy Management System(SCMS) .........................................................................8315.1.4 Channel Status Data E Buffer Access .................................................................................8315.1.5 One-Byte Mode ...................................................................................................................8415.1.6 Two-Byte Mode ...................................................................................................................8415.2 AES3 User (U) Bit Management ..................................................................................................84
15.2.1 Mode 1: Transmit All Zeros .................................................................................................8415.2.2 Mode 2: Block Mode ............................................................................................................8415.2.3 IEC60958 Recommended U Data Format for Consumer Applications ...............................8515.2.4 Mode (3): Reserved .............................................................................................................8515.2.5 Mode (4): IEC Consumer B .................................................................................................85
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CS8420
16. PLL FILTER ........................................................................................................................................8716.1 General ........................................................................................................................................8716.2 External Filter Components .........................................................................................................87
16.2.1 General ................................................................................................................................8716.2.2 Capacitor Selection .............................................................................................................8816.2.3 Circuit Board Layout ............................................................................................................8816.3 Component Value Selection ........................................................................................................88
16.3.1 Identifying the Part Revision ................................................................................................8816.3.2 Locking to the RXP/RXN Receiver Inputs ...........................................................................8916.3.3 Locking to the ILRCK Input .................................................................................................8916.3.4 Jitter Tolerance ....................................................................................................................9016.3.5 Jitter Attenuation .................................................................................................................90
17. PARAMETER DEFINITIONS ..............................................................................................................9118. PACKAGE DIMENSIONS ..................................................................................................................92THERMAL CHARACTERISTICS AND SPECIFICATIONS .................................................................9219. ORDERING INFORMATION ..............................................................................................................9320. REVISION HISTORY ..........................................................................................................................93
LIST OF FIGURES
Figure 1.Audio Port Master Mode Timing ...................................................................................................9Figure 2.Audio Port Slave Mode and Data Input Timing .............................................................................9Figure 3.SPI Mode Timing ........................................................................................................................10Figure 4.I²C Mode Timing .........................................................................................................................11Figure 5.Recommended Connection Diagram for Software Mode ...........................................................12Figure 6.Software Mode Audio Data Flow Switching Options ...................................................................14Figure 7.CS8420 Clock Routing ................................................................................................................14Figure 8.Serial Audio Input, using PLL, SRCEnabled ..............................................................................16Figure 9.Serial Audio Input, No PLL, SRC Enabled ..................................................................................16Figure 10.AES3 Input, SRC Enabled ........................................................................................................16Figure 11.Serial Audio Input, AES3 Input Clock Source, SRC Enabled ...................................................16Figure 12.Serial Audio Input, SRC Output Clocked by AES3 Recovered Clock .......................................16Figure 13.AES3 Input, SRC to Serial Audio Output, Serial Audio Input to AES3 Out ...............................16Figure 14.AES3 Input to Serial Audio Output, Serial Audio Input to AES3 Out, No SRC .........................17Figure 15.AES3 Input to Serial Audio Output Only ...................................................................................17Figure 16.Input Serial Port to AES3 Transmitter .......................................................................................17Figure 17.Serial Audio Input Example Formats ........................................................................................20Figure 18.Serial Audio Output Example Formats ......................................................................................21Figure 19.AES3 Receiver Timing for C & U Pin Output Data ...................................................................23Figure 20.AES3 Transmitter Timing for C, U and V Pin Input Data ..........................................................26Figure 21.Mono Mode Operation Compared to Normal Stereo Operation ...............................................27Figure 22.Control Port Timing in SPI Mode ..............................................................................................30Figure 23.Control Port Timing in I²C Mode ...............................................................................................31Figure 24.Hardware Mode 1 - Default Data Flow, AES3 Input .................................................................56Figure 25.Hardware Mode 2 - Default Data Flow, Serial Audio Input .......................................................59Figure 26.Hardware Mode 3 - Transceive Data Flow, with SRC ..............................................................63Figure 27.Hardware Mode 4 - Transceive Data Flow, Without SRC .........................................................67Figure 28.Hardware Mode 5 - AES3 Receiver Only .................................................................................71Figure 29.Hardware Mode 6 - AES3 Transmitter Only .............................................................................74Figure 30.Professional Output Circuit .......................................................................................................78Figure 31.Consumer Output Circuit ..........................................................................................................78Figure 32.TTL/CMOS Output Circuit .........................................................................................................79Figure 33.Professional Input Circuit ..........................................................................................................79Figure 34.Transformerless Professional Input Circuit ...............................................................................79
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CS8420
Figure 35.Consumer Input Circuit .............................................................................................................80Figure 36.TTL/CMOS Input Circuit ............................................................................................................80Figure 37.Channel Status Data Buffer Structure .......................................................................................81Figure 38.Channel Status Block Handling When Fso is Not Equal to Fsi .................................................82Figure 39.Flowchart for Reading the E Buffer ...........................................................................................82Figure 40.Flowchart for Writing the E Buffer .............................................................................................83Figure 41.PLL Block Diagram ...................................................................................................................87Figure 42.Recommended Layout Example ...............................................................................................88Figure 43.Jitter Tolerance Template .........................................................................................................90Figure 44.Revision D Jitter Attenuation .....................................................................................................90Figure 45.Revision D1 Jitter Attenuation ...................................................................................................90
LIST OF TABLES
Table 1. Minimizing Group Delay Through Multiple CS8420s When Locking to RXP/RXN ......................28Table 2. Minimizing Group Delay Through Multiple CS8420s When Locking to ILRCK ...........................28Table 3. Non-SRC Delay ...........................................................................................................................29Table 4. Summary of all Bits in the Control Register Map ........................................................................33Table 5. Hardware Mode Definitions .........................................................................................................55Table 6. Serial Audio Output Formats Available in Hardware Mode .........................................................55Table 7. Serial Audio Input Formats Available in Hardware Mode ............................................................55Table 8. Hardware Mode 1 Start-Up Options ............................................................................................56Table 9. HW Mode 2A COPY/C and ORIG/U Pin Function ......................................................................60Table 10. HW Mode 2 Serial Audio Port Format Selection .......................................................................60Table 11. Hardware Mode 2 Start-Up Options ..........................................................................................60Table 12. Hardware Mode 3 Start-Up Options ..........................................................................................64Table 13. Hardware Mode 4 Start-Up Options ..........................................................................................68Table 14. Hardware Mode 5 Start-Up Options ..........................................................................................71Table 15. HW 6 COPY/C and ORIG Pin Function ....................................................................................75Table 16. HW 6 Serial Port Format Selection ...........................................................................................75Table 17. Second Line Part Marking .........................................................................................................88Table 18. Locking to RXP/RXN - Fs = 8 to 96 kHz ...................................................................................89Table 19. Locking to RXP/RXN - Fs = 32 to 96 kHz* ................................................................................89Table 20. Locking to the ILRCK Input .......................................................................................................89
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CS8420
1.
CHARACTERISTICS AND SPECIFICATIONS
All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at nominal supply voltages and TA = 25°C.
SPECIFIED OPERATING CONDITIONS
AGND, DGND = 0V, all voltages with respect to 0V.
Parameter
Power Supply Voltage
Ambient Operating Temperature:
Commercial GradeAutomotive Grade
Symbol Min TypVD+, VA+
TA
4.75-10-40
5.0--Max5.25+70+85
UnitsV°C°C
ABSOLUTE MAXIMUM RATINGS
AGND, DGND = 0V; all voltages with respect to 0V. Operation beyond these limits may result in permanent dam-age to the device. Normal operation is not guaranteed at these extremes.
Parameter
Power Supply Voltage
Input Current, Any Pin Except Supplies, RXP/RXN (Note 1)Input Voltage
Ambient Operating Temperature (power applied)Storage Temperature
Notes:
1.Transient currents of up to 100mA will not cause SCR latch-up.
SymbolVD+, VA+
IinVinTATstg
Min---0.3-55-65
Max6.0±10(VD+) + 0.3
125150
UnitsVmAV°C°C
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CS8420
PERFORMANCE SPECIFICATIONS
Parameter*
Dynamic Range
Input Sample Rate (serial input port)Output Sample Rate
Output to Input Sample Rate RatioTotal Harmonic Distortion + Noise 1kHz, -1dBFS, 0.33 < Fso/Fsi < 1.7 1kHz, -1dBFS, 0.33 < Fso/Fsi < 3 10kHz, -1dBFS, 0.33 < Fso/Fsi < 1.7 10kHz, -1dBFS, 0.33 < Fso/Fsi < 3Peak idle channel noise componentResolutionGain Error
THD+N
-----16-0.12
--------117-112-110-107-140240
dBdBdBdBdBFSbitsdB
FsiFso
Symbol Min Typ
120880.33
128---Max-1081083
UnitsdBkHzkHz
DIGITAL FILTER CHARACTERISTICS
Parameter*
PassbandPassband Ripple
Stopband (Downsampling)Stopband AttenuationGroup Delay
Group Delay Variation vs. FrequencyInterchannel Phase Deviation
2.See “AES3 Transmitter and Receiver” on page28.
(Note 2)
tgdΔtgd
UpsamplingDownsampling
Symbol Min Typ
00-0.5465*Fso
110----------Max0.4535*Fsi0.4535*Fso±0.007Fsi/2-0.00.0
UnitsHzHzdBHzdBmsμs°
- 1.75DC ELECTRICAL SPECIFICATIONS
AGND = DGND = 0V; all voltages with respect to 0V.
Parameters
Power Down Mode (Note 3)Supply Current in power downNormal Operation (Note 4)Supply Current at 48kHz Fso and FsiSupply Current at 96kHz Fso and Fsi
VA+VD+VA+VD+
----3.7667.0125
----mAmAmAmA
VA+VD+
--2020
--μAμA
Symbol
Min
Typ
Max
Units
3.Power Down Mode is defined as RST = LO with all clocks and data lines held static.4.Normal operation is defined as RST = HI.
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CS8420
DIGITAL INPUT CHARACTERISTICS
Parameters
Input Leakage Current
Differential Input Voltage, RXP to RXN
Symbol IinVTH
Min Typ-200
±10-±15- Max
UnitsμAmVpp
DIGITAL INTERFACE SPECIFICATIONS
AGND = DGND = 0 V; all voltages with respect to 0 V.
Parameters
High-Level Output Voltage (IOH = -3.2mA), except TXP/TXNLow-Level Output Voltage (IOH = 3.2mA), except TXP/TXNHigh-Level Output Voltage (IOH = -21mA), TXP, TXNLow-Level Output Voltage (IOH = 21mA), TXP, TXNHigh-Level Input Voltage, except RXP, RXNLow-Level Input Voltage, except RXP, RXN
VIHVIL
Symbol Min MaxVOHVOL
(VD+) - 1.0
-(VD+) - 0.7
-2.0-0.3
-0.4-0.7(VD+) + 0.3
0.8
UnitsVVVVVV
TRANSMITTER CHARACTERISTICS
Parameters
TXP Output ResistanceTXN Output Resistance
Symbol TypRTXPRTXN
2525
UnitsΩΩ
SWITCHING CHARACTERISTICS
Inputs: Logic 0 = 0V, Logic 1 = VD+; CL = 20pF.
Parameter
RST pin Low Pulse Width
OMCK Frequency for OMCK = 512 * Fso
OMCK Low and High Width for OMCK = 512 * FsoOMCK Frequency for OMCK = 384 * Fso
OMCK Low and High Width for OMCK = 384 * FsoOMCK Frequency for OMCK = 256 * Fso
OMCK Low and High Width for OMCK = 256 * FsoPLL Clock Recovery Sample Rate RangeRMCK output jitterRMCK output duty cycleRMCK Input Frequency
RMCK Input Low and High WidthAES3 Transmitter Output Jitter
5.Cycle-to-cycle jitter using 32-96kHz external PLL components.
6.PLL is bypassed (RXD1:0 bits in the Clock Source Control register set to 10b), clock is input to the RMCK
pin.8
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(Note 6) (Note 6) (Note 5)
Symbol Min Typ
2004.0968.23.07212.32.04816.48.0-402.04816.4---------20050---Max-55.3-41.5-27.7-108.0-6027.7-1
UnitsμsMHznsMHznsMHznskHzpsRMS%MHznsns
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CS8420
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORTS
Inputs: Logic 0 = 0V, Logic 1 = VD+; CL = 20pF.
Parameter
OSCLK Active Edge to SDOUT Output ValidSDIN Setup Time Before ISCLK Active EdgeSDIN Hold Time After ISCLK Active EdgeMaster Mode
O/RMCK to I/OSCLK active edge delay O/RMCK to I/OLRCK delayI/OSCLK and I/OLRCK Duty CycleSlave ModeI/OSCLK Period
I/OSCLK Input Low WidthI/OSCLK Input High Width
I/OSCLK Active Edge to I/OLRCK Edge
(Note 7, 9, 11)
I/OLRCK Edge Setup Before I/OSCLK Active Edge
(Note 7, 9, 12)
(Note 10)
tsckwtsckltsckhtlrckdtlrcks
3614142020
----------nsnsnsnsns
(Note 7, 8) (Note 9)
tsmdtlmd
00---50
1617-nsns%
(Note 7) (Note 7) (Note 7)
Symbol Min Typtdpdtdstdh
-2020
---Max25--Unitsnsnsns
7.The active edges of ISCLK and OSCLK are programmable.
8.When OSCLK, OLRCK, ISCLK, and ILRCK are derived from OMCK they are clocked from its rising edge.
When these signals are derived from RMCK, they are clocked from its falling edge.9.The polarity of ILRCK and OLRCK is programmable.10.No more than 128 SCLK per frame.
11.This delay is to prevent the previous I/OSCLK edge from being interpreted as the first one after I/OLRCK
has changed.12.This setup time ensures that this I/OSCLK edge is interpreted as the first one after I/OLRCK has changed.
ISCLKOSCLK(output)ILRCKOLRCK(output)tsmdRMCK(output)Hardware ModeRMCK(output)Software ModeOMCK(input)tlmdILRCKOLRCK(input)ISCLKOSCLK(input)tlrckdtlrckstsckhtsckltsckwSDINtdsSDOUTtdhtdpdFigure 1. Audio Port Master Mode TimingFigure 2. Audio Port Slave Mode and Data Input Timing
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CS8420
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI™ MODE
Inputs: Logic 0 = 0V, Logic 1 = VD+; CL = 20pF.
Parameter
CCLK Clock Frequency
CS High Time Between TransmissionsCS Falling to CCLK EdgeCCLK Low TimeCCLK High Time
CDIN to CCLK Rising Setup TimeCCLK Rising to DATA Hold TimeCCLK Falling to CDOUT StableRise Time of CDOUTFall Time of CDOUT
Rise Time of CCLK and CDINFall Time of CCLK and CDIN
(Note 15) (Note 15) (Note 14) (Note 13)
Symbol Min Typfscktcshtcsstscltschtdsutdhtpdtr1tf1tr2tf2
01.02066664018-----------------Max6.0------452525100100
UnitsMHzμsnsnsnsnsnsnsnsnsnsns
13.If Fso or Fsi is lower than 46.875kHz, the maximum CCLK frequency should be less than 128 Fso and
less than 128 Fsi. This is dictated by the timing requirements necessary to access the Channel Status andUser Bit buffer memory. Access to the control register file can be carried out at the full 6MHz rate. Theminimum allowable input sample rate is 8kHz, so choosing CCLK to be less than or equal to 1.024MHzshould be safe for all possible conditions.14.Data must be held for sufficient time to bridge the transition time of CCLK.15.For fsck < 1MHz.
CStcssCCLKtr2CDINtdsutdhtf2tscltschtcshtpdCDOUTFigure 3. SPI Mode Timing
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CS8420
SWITCHING CHARACTERISTICS - CONTROL PORT - I²C® MODE
Inputs: Logic 0 = 0V, Logic 1 = VD+; CL = 20pF.
Parameter
SCL Clock Frequency
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)Clock Low TimeClock High Time
Setup Time for Repeated Start ConditionSDA Hold Time from SCL FallingSDA Setup Time to SCL RisingRise Time of Both SDA and SCL LinesFall Time of Both SDA and SCL LinesSetup Time for Stop Condition
(Note 16)
Symbol Min Typfscltbufthdsttlowthightsustthddtsudtrtftsusp
-4.74.04.74.04.70250--4.7
-----------Max100-------2525-UnitskHzμsμsμsμsμsμsnsnsnsμs
16.Data must be held for sufficient time to bridge the 25ns transition time of SCL.
StopSDAtbufSCLtlowthddtsudtsusttrthdstthighthdsttftsuspStartRepeatedStartStopFigure 4. I²C Mode Timing
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CS8420
2.
TYPICAL CONNECTION DIAGRAM
+5VAnalogSupply*Ferrite*Bead0.1μF0.1μF+5VDigitalSupplyVA+AES3/SPDIFSourceCableTerminationRXPRXNCS84203-wireSerialAudioSourceILRCKISCLKSDINRMCKOMCKVD+TXPTXNCableInterfaceAES3/SPDIFEquipmentOLRCKOSCLKSDOUT3-wireSerialAudioInputDeviceClockSourceandControl47kΩHardwareControlSDA/CDOUTAD0/CSSCL/CCLKAD1/CDININTEMPH/AD2URERRRSTTCBLH/SAGNDFILTDGNDRFILTCFILTCRIPMicrocontrollerTootherCS8420's*AseparateanalogsupplyisonlynecessaryinapplicationswhereRMCKisusedforajittersensitivetask.ForapplicationswhereRMCKisnotusedforajittersensitivetask,connectVA+toVD+viaaferritebead.KeepthedecouplingcapacitorbetweenVA+andAGND.Figure 5. Recommended Connection Diagram for Software Mode
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CS8420
3.
GENERAL DESCRIPTION
The CS8420 is a fully asynchronous sample rate converter plus AES3 transceiver intended to be used in digital au-dio systems. Such systems include digital mixing consoles, effects processors, tape recorders, and computer mul-timedia systems. The CS8420 is intended for 16-, 20-, and 24-bit applications where the input sample rate isunknown, or is known to be asynchronous to the system sample rate.
On the input side of the CS8420, AES3 or 3-wire serial format can be chosen. The output side produces both AES3and 3-wire serial format. An I²C/SPI-compatible microcontroller interface allows full block processing of channel sta-tus and user data via block reads from the incoming AES3 data stream and block writes to the outgoing AES3 datastream. The user can also access information decoded from the input AES3 data stream, such as the presence ofnon-audio data and pre-emphasis, as well as control the various modes of the device. For users who prefer not touse a micro-controller, six hardware modes have been provided and documented towards the end of this data sheet.In these modes, flexibility is limited, with pins providing some programmability.
When used for AES3-input/AES3-output applications, the CS8420 can automatically transceive user data that con-forms to the IEC60958-recommended format. The CS8420 also allows access to the relevant bits in the AES3 datastream to comply with the serial copy management system (SCMS).
The diagram on the cover of this data sheet shows the main functional blocks of the CS8420. Figure5 shows thesupply and external connections to the device.
Familiarity with the AES3 and IEC60958 specifications are assumed throughout this document. Application Note 22:Overview of Digital Audio Interface Data Structures, contains a tutorial on digital audio specifications. The paper AnUnderstanding and Implementation of the SCMS Serial Copy Management System for Digital Audio Transmission,by ClifSanchez, is an excellent tutorial on SCMS. It may be obtained from Cirrus Logic, Inc., or from the AES. To guarantee system compliance, the proper standards documents should be obtained. The latest AES3 standardshould be obtained from the Audio Engineering Society (ANSI), the latest IEC60958 standard from the InternationalElectrotechnical Commission and the latest EIAJ CP-1201 standard from the Japanese Electronics Bureau.
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CS8420
4.
DATA I/O FLOW AND CLOCKING OPTIONS
The CS8420 can be configured for nine connectivity alternatives, referred to as data flows. Each data flow has anassociated clocking set-up. Figure6 shows the data flow switching, along with the control register bits which controlthe switches. This drawing only shows the audio data paths for simplicity. Figure 7 shows the internal clock routingand the associated control register bits. The clock routing constraints determine which data routing options are ac-tually usable.
SPD1-0ILRCKISCLKSDINSerialAudioInputSRCDSampleRateConverterSerialAudioOutputAESBPTXOFFAES3EncoderTXD1-0TXPTXNOLRCKOSCLKSDOUTRXNRXPAES3ReceiverFigure 6. Software Mode Audio Data Flow Switching Options
SDINISCLKILRCKSERIALAUDIOINPUTRXD00SIMSSAMPLERATECONVERTERSERIALAUDIOOUTPUTSDOUTOSCLKOLRCKRMCKFPLL1MUXINC0MUXRXP1÷CHANNELSTATUSMEMORYTXNAES3TRANSMITTXP10USERBITSWCLKUNLOCKMEMORYMUX01MUXOUTC0MUXRMCK1÷RXD1CLK[1:0]OMCK*Note: When SWCLK mode is enabled, signal input on OMCK is only output through RMCK and not routed back through the RXD1 multiplexer; RMCK is not bi-directional in this mode.
Figure 7. CS8420 Clock Routing
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CS8420
The AESBP switch allows a TTL level, bi-phase mark-encoded data stream connected to RXP to be routed to theTXP and TXN pin drivers. The TXOFF switch causes the TXP and TXN outputs to be driven to ground
In modes including the SRC function, there are two audio-data-related clock domains. One domain includes the in-put side of SRC, plus the attached data source. The second domain includes the output side of the SRC, plus anyattached output ports.
There are two possible clock sources. The first known as the recovered clock, is the output of a PLL, and is con-nected to the RCMK pin. The input to the PLL can be either the incoming AES3 data stream or the ILRCK word rateclock from the serial audio input port. The second clock is input via the OMCK pin, and would normally be a crystal-derived stable clock. The Clock Source Control Register bits determine which clock is connected to which domain.By studying the following drawings, and appropriately setting the Data Flow Control and Clock Source Control reg-ister bits, the CS8420 can be configured to fit a variety of application requirements.
The following drawings illustrate the possible valid data flows. The audio data flow is indicated by the thin lines; theclock routing is indicated by the bold lines. The register settings for the Data Flow Control register and the ClockSource Register are also shown for each data flow. Some of the register settings may appear to be not relevant tothe particular data flow in question, but have been assigned a particular state. This is done to minimize power con-sumption. The AESBP data path from the RXP pin to the AES3 output drivers, and the TXOFF control, have beenomitted for clarity, but are present and functional in all modes where the AES3 transmitter is in use.
Figures 8 and 9 show audio data entering via the serial audio input port, then passing through the sample rate con-verter, and then output both to the serial audio output port and to the AES3 transmitter. Figure8 shows the PLLrecovering the input clock from ILRCK word clock. Figure9 shows using a direct 256*Fsi clock input via the RMCKpin, instead of the PLL.
Figure10 shows audio data entering via the AES3 Receiver. The PLL locks onto the pre-ambles in the incomingaudio stream, and generates a 256*Fsi clock. The rate-converted data is then output via the serial audio output portand via the AES3 transmitter.
Figure11 shows the same data flow as Figure8. The input clock is derived from an incoming AES3 data stream.The incoming data must be synchronous to the AES3 data stream.
Figure12 shows the same data flow as Figure8. The input data must be synchronous to OMCK. The output datais clocked by the recovered PLL clock from an AES3 input stream. This may be used to implement a “house sync”architecture.
Figure8 shows audio data entering via the AES3 receiver, passing through the sample rate converter, and then ex-iting via the serial audio output port. Synchronous audio data may then be input via the serial audio input port andoutput via the AES3 transmitter.
Figure14 is the same as Figure13, but without the sample rate converter. The whole data path is clocked via thePLL generated recovered clock.
Figure15 illustrates a standard AES3 receiver function, with no rate conversion.Figure16 shows a standard AES3 transmitter function, with no rate conversion.
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CS8420
SDINISCLKILRCKSerialAudioOutputSerialAudioInputPLLSampleRateConverterOLRCKOSCLKSDOUTAES3Encoder&DriverTXPTXNSDINISCLKILRCKSerialAudioOutputSerialAudioInputSampleRateConverterOLRCKOSCLKSDOUTAES3Encoder&DriverTXPTXNRMCKDataFlowControlBitsTXD1-0:00SPD1-0:00SRCD:0OMCKClockSourceControlBitsOUTC:0INC:0RXD1-0:00RMCKDataFlowControlBitsTXD1-0:00SPD1-0:00SRCD:0OMCKClockSourceControlBitsOUTC:0INC:0RXD1-0:10Figure 8. Serial Audio Input, using PLL, SRCEnabled
SerialAudioOutputSampleRateConverterOLRCKOSCLKSDOUTFigure 9. Serial Audio Input, No PLL, SRC Enabled
SerialAudioOutputSerialAudioInputAES3RxSampleRateConverterOLRCKOSCLKSDOUTRXNRXPAES3Rx&DecodePLLAES3Encoder&DriverTXPTXNSDINISCLKILRCKRXNRXPAES3Encoder&DriverTXPTXNPLLRMCKOMCKRMCKDataFlowControlBitsTXD1-0:00SPD1-0:00SRCD:1OMCKClockSourceControlBitsOUTC:00INC:RXD1-0:01DataFlowControlBitsTXD1-0:00SPD1-0:00SRCD:0ClockSourceControlBitsOUTC:0INC:0RXD1-0:01Figure 10. AES3 Input, SRC EnabledFigure 11. Serial Audio Input, AES3 Input Clock Source,
SDOUTOSCLKOLRCKSDINISCLKILRCKSDINISCLKILRCKSerialAudioInputSampleRateConverterPLLAES3RxSerialAudioOutputOLRCKOSCLKSDOUTSerialSerialAudioAudioOutputInputRXNRXPAES3SampleRx&RateDecodeConverterPLLAES3Encoder&DriverTXPTXNAES3Encoder&DriverTXPTXNOMCKRXPRXNRMCKRMCKDataFlowControlBitsTXD1-0:01SPD1-0:00SRCD:1OMCKClockSourceControlBitsOUTC:0INC:0RXD1-0:01DataFlowControlBitsTXD1-0:00SPD1-0:00SRCD:0ClockSourceControlBitsOUTC:1INC:1RXD1-0:01Figure 12. Serial Audio Input, SRC Output Clocked by
AES3 Recovered ClockFigure 13. AES3 Input, SRC to Serial Audio Output, Serial
Audio Input to AES3 Out
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CS8420
SDOUTOSCLKOLRCKSDINISCLKILRCKSerialSerialAudioAudioOutputInputRXNRXPAES3Rx&DecodePLLAES3Encoder&DriverTXPRXNRXPAES3Rx&DecodePLLSerialAudioOutputOLRCKOSCLKSDOUTTXNRMCKRMCKDataFlowControlBitsTXD1-0:01SPD1-0:10SRCD:0ClockSourceControlBitsOUTC:1INC:0RXD1-0:01DataFlowControlBitsTXD1-0:10SPD1-0:10SRCD:0TXOFF:1ClockSourceControlBitsOUTC:1INC:0RXD1-0:01Figure 14. AES3 Input to Serial Audio Output, Serial Au-dio Input to AES3 Out, No SRC
Figure 15. AES3 Input to Serial Audio Output Only
SDINISCLKILRCKSerialAudioInputAES3Encoder&DriverTXPTXNOMCKDataFlowControlBitsTXD1-0:01SPD1-0:01SRCD:0ClockSourceControlBitsOUTC:0INC:1RXD1-0:00Figure 16. Input Serial Port to AES3 Transmitter
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CS8420
5.
SAMPLE RATE CONVERTER (SRC)
Multirate digital signal processing techniques are used to conceptually upsample the incoming data to very high rateand then downsample to the outgoing rate, resulting in a 24-bit output, regardless of the width of the input. The fil-tering is designed so that a full input audio bandwidth of 20kHz is preserved if the input sample and output samplerates are greater than 44.1kHz. When the output sample rate becomes less than the input sample rate, the input isautomatically band limited to avoid aliasing products in the output. Careful design ensures minimum ripple and dis-tortion products are added to the incoming signal. The SRC also determines the ratio between the incoming andoutgoing sample rates, and sets the filter corner frequencies appropriately. Any jitter in the incoming signal has littleimpact on the dynamic performance of the rate converter and has no influence on the output clock.
5.1Dither
When using the AES3 input, and when using the serial audio input port in Left-Justified and I²S modes, allinput data is treated as 24 bits wide. Any truncation that has been done prior to the CS8420 to less than 24bits should have been done using an appropriate dither process. If the serial audio input port is used to feedthe SRC, and the port is in Right-Justified mode, then the input data will be truncated to the SIRES bit settingvalue. If SIRES bits are set to 16 or 20 bits, and the input data is 24 bits wide, truncation distortion will occur.Similarly, in any serial audio input port mode, if an inadequate number of bit clocks are entered (say 16 in-stead of 20), the input words will be truncated, causing truncation distortion at low levels. In summary, thereis no dithering mechanism on the input side of the CS8420, and care must be taken to ensure that no trun-cation occurs.
Dithering is used internally where appropriate inside the SRC block.
The output side of the SRC can be set to 16, 20, or 24 bits. Optional dithering can be applied, and is auto-matically scaled to the selected output word length. This dither is not correlated between left and right chan-nels. It is recommended that the dither control bit be left in its default ON state.
5.2SRC Locking, Varispeed and the Sample Rate Ratio Register
The SRC calculates the ratio between the input sample rate and the output sample rate and uses this infor-mation to set up various parameters inside the SRC block. The SRC takes some time to make this calcula-tion. For a worst case 3:1 to 1:3 input sample rate transition, the SRC will take 9400/Fso to settle (195msat Fso of 48kHz). For a power-up situation, the SRC will start from 1:1; the worst case time becomes8300/Fso (172ms at Fso of 48kHz).
If the PLL is in use (either AES3 or serial input port), the worst case locking time for the PLL and the SRCis the sum of each locking time.
If Fsi is changing, for example in a varispeed application, the REUNLOCK interrupt will occur, and the SRCwill track the incoming sample rate. During this tracking mode, the SRC will still rate convert the audio data,but at increased distortion levels. Once the incoming sample rate is stable, the REUNLOCK interrupt willbecome false, and the SRC will return to normal levels of audio quality.
The VFIFO interrupt occurs if the data buffer in the SRC overflows, which can occur if the input sample ratechanges at >10%/second.
Varispeed at Fsi slew rates approaching 10%/sec is only supported when the input is via the serial audioinput port. When using the AES3 input, high frame rate slew rates will cause the PLL to lose lock.The sample rate ratio is also made available as a register, accessible via the control port. The upper 2 bitsof this register form the integer part of the ratio, while the lower 6 bits form the fractional part. Since, in manyinstances Fso is known, this allows the calculation of the incoming sample rate by the host microcontroller.
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CS8420
6.
THREE-WIRE SERIAL AUDIO PORTS
A 3-wire serial audio input port and a 3-wire serial audio output port is provided. Each port can be adjusted to suitthe attached device via control registers. The following parameters are adjustable: master or slave, serial clock fre-quency, audio data resolution, left or right justification of the data relative to left/right clock, optional 1-bit cell delayof the 1st data bit, the polarity of the bit clock and the polarity of the left/right clock. By setting the appropriate controlbits, many formats are possible.
Figure17 shows a selection of common input formats, along with the control bit settings. The clocking of the inputsection of the CS8420 may be derived from the incoming ILRCK word rate clock, using the on-chip PLL. The PLLoperation is described in the AES receiver description on page22. In the case of use with the serial audio input port,the PLL locks onto the leading edges of the ILRCK clock.
Figure18 shows a selection of common output formats, along with the control bit settings. A special AES3 directoutput format is included, which allows serial output port access to the V, U, and C bits embedded in the serial audiodata stream. The P bit is replaced by a bit indicating the location of the start of a block. This format is only availablewhen the serial audio output port is being clocked by the AES3 receiver-recovered clock. Also, the received-channelstatus block start signal is only available in Hardware mode 5, as the RCBL pin.
In Master mode, the left/right clock and the serial bit clock are outputs, derived from the appropriate clock domainmaster clock.
In Slave mode, the left/right clock and the serial bit clock are inputs. The left/right clock must be synchronous to theappropriate master clock, but the serial bit clock can be asynchronous and discontinuous if required. By appropriatephasing of the left/right clock and control of the serial clocks, multiple CS8420’s can share one serial port. Theleft/right clock should be continuous, but the duty cycle does not have to be 50%, provided that enough serial clocksare present in each phase to clock all the data bits. When in Slave mode, the serial audio output port must be set toleft-justified or I²S data.
When using the serial audio output port in Slave mode with an OLRCK input which is asynchronous to the port’sdata source, then an interrupt bit is provided to indicate when repeated or dropped samples occur.The CS8420 allows immediate mute of the serial audio output port audio data via a control register bit.
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CS8420
ILRCKISCLKSDINMSBLSBMSBLSBMSBChannel AChannel BLeft Justified(In)ILRCKI²S(In)Channel AChannel BISCLKSDINMSBLSBMSBLSBMSBRight Justified(In)ILRCKISCLKSDINChannel AChannel BMSBLSBMSBLSBSIMS
Left-Justified
I²S
XX
SISFXX
SIRES1/0
0000+
SIJUST00
SIDEL010
SISPOL
000
SILRPOL
010
Right-JustifiedXXXX*1
X = don’t care to match format, but does need to be set to the desired setting+ I²S can accept an arbitrary number of bits, determined by the number of ISCLK cycles
* not 11 - See Serial Input Port Data Format Register Bit Descriptions for an explanation of the meaning of each bit
Figure 17. Serial Audio Input Example Formats
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CS8420
Left OLRCKChannel AChannel BJustifiedOSCLK(Out)SDOUTMSBLSBMSBLSBMSBOLRCKI²S(Out)Channel AChannel BOSCLKSDOUTMSBLSBMSBLSBMSBRight JustifiedOSCLK(Out)SDOUTOLRCKChannel AChannel BMSB ExtendedMSBLSBMSB ExtendedMSBLSBAES3Direct (Out)OLRCKOSCLKSDOUTLSBChannel AChannel BChannel AChannel BMSBVUCLSBMSBVUCLSBMSBVUCZLSBMSBVUCZFrame 191Frame 0SOMS
Left-Justified
I²SRight-JustifiedAES3Direct
XX1X
SOSFXXXX
SORES1/0
XX*XX*XX*11
SOJUST
0010
SODEL0100
SOSPOL
0000
SOLRPOL
0100
X = don’t care to match format, but does need to be set to the desired setting
* not 11 - See Serial Output Data Format Register Bit Descriptions for an explanation of the meaning of each bit
Figure 18. Serial Audio Output Example Formats
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CS8420
7.
AES3 TRANSMITTER AND RECEIVER
The CS8420 includes an AES3-type digital audio receiver and an AES3-type digital audio transmitter. A compre-hensive buffering scheme provides read/write access to the channel status and user data. This buffering scheme isdescribed in “Channel Status and User Data Buffer Management” on page81.
7.1AES3 Receiver
The AES3 receiver accepts and decodes audio and digital data according to the AES3, IEC60958 (S/PDIF),and EIAJ CP-1201 interface standards. The receiver consists of a differential input stage, accessed via pinsRXP and RXN, a PLL based clock recovery circuit, and a decoder which separates the audio data from thechannel status and user data.
External components are used to terminate and isolate the incoming data cables from the CS8420. Thesecomponents are detailed in “External AES3/SPDIF/IEC60958 Transmitter and Receiver Components” onpage78.
7.1.1PLL, Jitter Attenuation, and Varispeed
Please see “PLL Filter” on page87 for general description of the PLL, selection of recommended PLL filtercomponents, and layout considerations. Figure5 shows the recommended configuration of the two ca-pacitors and one resistor that comprise the PLL filter.
7.1.2OMCK Out On RMCK
A special mode is available that allows the clock that is being input through the OMCK pin to be outputthrough the RMCK pin. This feature is controlled by the SWCLK bit in register4 of the control registers.When the PLL loses lock, the frequency of the VCO drops to 300kHz. The SWCLK function allows theclock from RMCK to be used as a clock in the system without any disruption when input is removed fromthe Receiver.
7.1.3Error Reporting and Hold Function
While decoding the incoming AES3 data stream, the CS8420 can identify several kinds of error, indicatedin the Receiver Error register. The UNLOCK bit indicates whether the PLL is locked to the incoming AES3data. The V bit reflects the current validity bit status. The CONF (confidence) bit indicates the amplitudeof the eye pattern opening, indicating a link that is close to generating errors. The BIP (bi-phase) error bitindicates an error in incoming bi-phase coding. The PAR (parity) bit indicates a received parity error. The error bits are “sticky” - they are set on the first occurrence of the associated error and will remain setuntil the user reads the register via the control port. This enables the register to log all unmasked errorsthat occurred since the last time the register was read.
The Receiver Error Mask register allows masking of individual errors. The bits in this register serve asmasks for the corresponding bits of the Receiver Error Register. If a mask bit is set to 1, the error is con-sidered unmasked, meaning that its occurrence will be reported in the receiver error register, will affectthe RERR pin, will invoke the occurrence of a RERR interrupt, and will affect the current audio sampleaccording to the status of the HOLD bits. The HOLD bits allow a choice of holding the previous sample,replacing the current sample with zero (mute), or do not change the current audio sample. If a mask bit isset to 0, the error is considered masked, meaning that its occurrence will not be reported in the receivererror register, will not induce a pulse on RERR or generate a RERR interrupt, and will not affect the currentaudio sample. The QCRC and CCRC errors do not affect the current audio sample, even if unmasked.
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CS8420
7.1.4
Channel Status Data Handling
The first 2 bytes of the Channel Status block are decoded into the Receiver Channel Status register. Thesetting of the CHS bit in the Channel Status Data Buffer Control register determines whether the channelstatus decodes are from the A channel (CHS = 0) or B channel (CHS = 1).
The PRO (professional) bit is extracted directly. Also, for consumer data, the COPY (copyright) bit is ex-tracted, and the category code and L bits are decoded to determine SCMS status, indicated by the ORIG(original) bit. Finally, the AUDIO bit is extracted, and used to set an AUDIO indicator, as described in theNon-Audio Auto Detection section below.
If 50/15 µs pre-emphasis is detected, then this is reflected in the state of the EMPH pin.
The encoded sample word length channel status bits are decoded according to AES3-1992 or IEC 60958.If the AES3 receiver is the data source for the SRC, then the SRC audio input data is truncated accordingto the channel status word length settings. Audio data routed to the serial audio output port is unaffectedby the word length settings; all 24 bits are passed on as received.
“Channel Status and User Data Buffer Management” on page81 describes the overall handling of CS andU data.
7.1.5User Data Handling
The incoming user data is buffered in a user-accessible buffer. Various automatic modes of re-transmit-ting received U data are provided. “Channel Status and User Data Buffer Management” on page81 de-scribes the overall handling of CS and U data.
Received U data may also be output to the U pin, under the control of a control register bit. Depending onthe data flow and clocking options selected, there may not be a clock available to qualify the U data output.Figure19 illustrates the timing.
If the incoming user data bits have been encoded as Q-channel subcode, the data is decoded and pre-sented in 10 consecutive register locations. An interrupt may be enabled to indicate the decoding of a newQ-channel block, which may be read via the control port.
RCBLoutVLRCKC,UOutputRCBLandCoutputareonlyavailableinhardwaremode5.RCBLgoeshigh2framesafterreceiptofaZpre-amble,andishighfor16frames.VLRCKisavirtualwordclock,whichmaynotexist,butisusedtoillustratetheCUtiming.VLRCKdutycycleis50%.VLRCKfrequencyisalwaysequaltotheincomingframerate.IfnoSRCisused,andtheserialaudiooutputportisinmastermode,VLRCK=OLRCK.Iftheserialaudiooutputportisinslavemode,thenVLRCKneedstobeexternallycreated,ifrequired.C,Utransitionsarealignedwithin±1%ofVLRCKperiodtoVLRCKedgesFigure 19. AES3 Receiver Timing for C & U Pin Output Data
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CS8420
7.1.6
Non-Audio Auto Detection
Since it is possible to convey non-audio data in an AES3 data stream, it is important to know whether theincoming AES3 data stream is digital audio or other data. This information is typically conveyed in channelstatus bit 1 (AUDIO), which is extracted automatically by the CS8420. However, certain non-audio sourc-es, such as AC-3® or MPEG encoders, may not adhere to this convention, and the bit may not be properlyset. The CS8420 AES3 receiver can detect such non-audio data. This is accomplished by looking for a96-bit sync code, consisting of 0x0000, 0x0000, 0x0000, 0x0000, 0xF872, and 0x4E1F. When the synccode is detected, an internal AUTODETECT signal will be asserted. If no additional sync codes are de-tected within the next 4096 frames, AUTODETECT will be de-asserted until another sync code is detect-ed. The AUDIO bit in the Receiver Channel Status register is the logical OR of AUTODETECT and thereceived channel status bit 1. If non-audio data is detected, the data is still processed exactly as if it werenormal audio. It is up to the user to mute the outputs as required.
7.2AES3 Transmitter
The AES3 transmitter encodes and transmits audio and digital data according to the AES3, IEC60958(S/PDIF), and EIAJ CP-1201 interface standards. Audio and control data are multiplexed together andbi-phase mark-encoded. The resulting bit stream is then driven directly, or through a transformer, to anoutput connector.
The transmitter is usually clocked from the output side clock domain of the sample rate converter. Thisclock may be derived from the clock input pin OMCK, or from the incoming data. In data flows with noSRC, and where OMCK is asynchronous to the data source, an interrupt bit is provided that will go highevery time a data sample is dropped or repeated.
The channel status (C) and user channel (U) bits in the transmitted data stream are taken from storageareas within the CS8420. The user can manipulate the contents of the internal storage with a microcon-troller. The CS8420 will also run in one of several automatic modes. “Channel Status and User Data BufferManagement” on page81 provides detailed descriptions of each automatic mode, and describes methodsfor accessing the storage areas. The transmitted user data can optionally be input via the U pin, under thecontrol of a control port register bit. Figure20 shows the timing requirements for inputting U data via theU pin.
7.2.1Transmitted Frame and Channel Status Boundary Timing
The TCBL pin may be an input or an output, and is used to control or indicate the start of transmitted chan-nel status block boundaries.
In some applications, it may be necessary to control the precise timing of the transmitted AES3 frameboundaries. This may be achieved in 3 ways:
1) With TCBL configured as an input, and TCBL transitions high for >3 OMCK clocks, it will cause a framestart, and a new channel status block start.
2) If the AES3 output comes from the AES3 input, while there is no SRC, setting TCBL as output will causeAES3 output frame boundaries to align with AES3 input frame boundaries.
3) If the AES3 output comes from the serial audio input port while the port is in Slave mode, and TCBL isset to output, then the start of the A channel sub-frame will be aligned with the leading edge of ILRCK.
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CS8420
7.2.2
TXN and TXP Drivers
The line drivers are low-skew, low-impedance, differential outputs capable of driving cables directly. Bothdrivers are set to ground during reset (RST = low), when no AES3 transmit clock is provided, and option-ally under the control of a register bit. The CS8420 also allows immediate mute of the AES3 transmitteraudio data via a control register bit.
External components are used to terminate and isolate the external cable from the CS8420. These com-ponents are detailed in “External AES3/SPDIF/IEC60958 Transmitter and Receiver Components” onpage78.
7.3Mono Mode Operation
Currently, the AES3 standard is being updated to include options for 96-kHz sample rate operation. Onemethod is to double the frame rate of the current format. This results in a
96-kHz sample rate, stereo signal carried over a single twisted pair cable. An alternate method is where the2 sub-frames in a 48-kHz frame rate AES3 signal are used to carry consecutive samples of a mono signal,resulting in a 96-kHz sample rate stream. This allows older equipment, whose AES3 transmitters and re-ceivers are not rated for 96-kHz frame rate operation, to handle 96-kHz sample rate information. In this“mono mode”, 2 AES3 cables are needed for stereo data transfer. The CS8420 offers mono mode opera-tion, both for the AES3 receiver and for the AES3 transmitter. Figure21 shows the operation of mono modein comparison with normal stereo mode. The receiver and transmitter sections may be independently set tomono mode via the MMR and MMT control bits.
The receiver mono mode effectively doubles Fsi compared to the input frame rate. The clock output on theRMCK pin tracks Fsi, and so is doubled in frequency compared to stereo mode. In mono mode, A and Bsub-frames are routed to the SRC inputs as consecutive samples.
When the transmitter is in mono mode, either A or B SRC consecutive outputs are routed alternately to Aand B sub-frames in the AES3 output stream. Which channel status block is transmitted is also selectable.For the AES3 input to serial audio port output data flow, in receiver mono mode, then the receiver will runat a frame rate of Fsi/2, and the serial audio output port will run at Fsi. Identical data will appear in both leftand right data fields on the SDOUT pin.
For the serial audio input port to AES3 transmitter data flow, in transmitter mono mode, then the input portwill run at Fso audio sample rate, while the AES3 transmitter frame rate will be at Fso/2. The data from eitherconsecutive left, or right, positions will be selected for transmitting in A and B sub-frames.
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CS8420
TCBLIn or OutVLRCKTthTsetupVCUInputSDINInputTXP(N)TholdVCU[0]VCU[1]VCU[2]VCU[3]VCU[4]Data [4]Data [5]Data [6]Data [7]Data [8]ZData [0]YData [1]XData [2]YData [3]XData [4]AES3 Transmitter in Stereo ModeTCBLIn or OutVLRCKUInputSDINInputTXP(N)OutputZTthTsetup=> 7.5% AES3 frame timeThold= 0Tth > 3OMCK if TCBL is InputU[0]U[2]Data [4]Data [5]Data [6]Data [7]Data [8]Data [0]*YData [2]*XData [4]**Assume MMTLR = 0TXP(N)ZData [1]*Output*Assume MMTLR = 1YData [3]*XData [5]*AES3 Transmitter in Mono ModeTsetup=> 15% AES3 frame timeThold= 0Tth > 3OMCK if TCBL is InputVLRCK is a virtual word clock, which may not exist, and is used to illustrate CUV timing.VLRCK duty cycle is 50% In stereo mode, VLRCK frequency = AES3 frame rate. In mono mode, ALRCK frequency = 2xAES3 frame rate..If the serial audio input port is in slave mode and TCBL is an output, the VLRCK=ILRCK if SILRPOL=0 andVLRCK= ILRCK if SILRPOL = 1.If the serial audio input port is in master mode and TCBL is an input, the VLRCK=ILRCK if SILRPOL=0 andVLRCK= ILRCK if SILRPOL = 1.Figure 20. AES3 Transmitter Timing for C, U and V Pin Input Data
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CS8420
RECEIVERSTEREOMODE96kHzFsiABABInSRC96kHzFsoOutABTRANSMITTERSTEREOMODE96kHzstereo96kHzframerateAES3ReceiverA96kHzstereo96kHzframerateAES3BTransmitterPLL256x96kHzOMCK(256,384,or512x96kHz)RECEIVERMONOMODE96kHzmono48kHzframerateAES3Receiver96kHzFsiAB*ABInSRC96kHzFsoOutMMTLRA+BTRANSMITTERMONOMODE96kHzmono48kHzframerateAAES3BTransmitterPLL(x2)256x96kHzOMCK(256,384,or512x96kHz)*A&Bsub-framesdataaretime-multiplexedintoconsecutivesamples+ConsecutivesamplesarealternatelyroutedtoA&Bsub-famesTRANSMITTERTIMINGSRCAoutA1B1STEREOA2B2FrameA1MONOA1B1A2A2B2RECEIVERTIMINGFrameIncomingAES3SRCAinSRCBinMONOAin&BinSRCA1B1A2B2A1B1A2A1B1B2A2B2SRCBoutOutgoingAES3OutgoingAES3AselectedOutgoingAES3BselectedSTEREOFrameB1B2Figure 21. Mono Mode Operation Compared to Normal Stereo Operation
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CS8420
8.
8.1
AES3 TRANSMITTER AND RECEIVER
Sample Rate Converter
The equation for the group delay through the sample rate converter, with the serial ports in Master mode is:((inputinterfacedelay + 43) / Fsi) + ((43 + outputinterfacedelay ± 0.5) / Fso)
The unit of delay depends on the frame rate (samplerate) Fs. The AES receiver has a interface delay of 2frames. The AES transmitter, the serial input port, and the serial output port each have an interface delayof 1 frame. The ± 0.5 frame delay in the second half of the equation is due to the start-up uncertainty of thelogic within the part.
When using multiple parts together, it is possible to start the parts simultaneously in a fashion that minimizesthe relative group delay between the parts. When multiple parts are started together in the proper way, thevariation in signal delay through the parts is ±1.5μs.
To start the parts simultaneously, set up each one so that the PLL will lock, with the active input port drivingboth output ports. Then simultaneously enable the RUN bits in all of the parts. TCBL on one of the CS8420parts should be set as an output, while the remaining TCBL pins should be set as inputs. This synchronizesthe AES transmitter on all of the parts.
Depending upon software considerations, it may be advantageous to configure the registers so that an in-terrupt is generated on the INT pin when lock occurs. The control logic should either poll the unlock bits untilall PLL’s are locked or wait for the interrupts to indicate that all are locked, depending on which approachyou’ve chosen.
When all of the PLL’s are locked, the CS8420’s should be advanced to the next state together. Drive all theserial control ports together with the same clock and data. Change the configuration in register 03h accord-ing to Table1 or Table2.
Register (HEX)01030411
Initial Value (HEX)01 or 00954110
Value After Advancing to the Running State, After the PLL’s are Locked (HEX)
01 or 00814110
Table 1. Minimizing Group Delay Through Multiple CS8420s When Locking to RXP/RXN
Register (HEX)01030411
Initial Value (HEX)01 or 008A4010
Value After Advancing to the Running State, After the PLL’s are Locked (HEX)
01 or 00804010
Table 2. Minimizing Group Delay Through Multiple CS8420s When Locking to ILRCK
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CS8420
8.2
Non-SRC Delay
The unit of delay depends on the frame rate (samplerate) Fs. The AES receiver has a interface delay of twoframes. The AES transmitter, the serial input port, and the serial output port each have an interface delayof 1 frame. The ± 0.5 frame delay in the second half of the equation is due to the startup uncertainty of thelogic within the part.
1.All inputs are slaves and all outputs are masters, both with respect to the outside world.2.The inputs and outputs are synchronous to one another.
PathRX to TXSerial Input to TXRX to Serial OutputSerial Input to Serial Output
Table 3. Non-SRC Delay
Delay (in units of a frame)
3 ± 1/1282 ± 1/1283 ± 1/1282 ± 1/128
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CS8420
9.
CONTROL PORT DESCRIPTION AND TIMING
The control port is used to access the registers, allowing the CS8420 to be configured for the desired operationalmodes and formats. In addition, Channel Status and User data may be read and written via the control port. Theoperation of the control port may be completely asynchronous with respect to the audio sample rates. However, toavoid potential interference problems, the control port pins should remain static if no operation is required.The control port has two modes: SPI and I²C, with the CS8420 acting as a slave device. SPI mode is selected ifthere is a high-to-low transition on the AD0/CS pin after the RST pin has been brought high. I²C mode is selectedby connecting the AD0/CS pin to VD+ or DGND, thereby permanently selecting the desired AD0 bit address state.
9.1SPI Mode
In SPI mode, CS is the CS8420 chip select signal. CCLK is the control port bit clock (input into the CS8420from the microcontroller), CDIN is the input data line from the microcontroller, CDOUT is the output data lineto the microcontroller. Data is clocked in on the rising edge of CCLK and out on the falling edge.
Figure22 shows the operation of the control port in SPI mode. To write to a register, bring CS low. The first7 bits on CDIN form the chip address and must be 0010000b. The eighth bit is a read/write indicator (R/W),which should be low to write. The next 8 bits form the Memory Address Pointer (MAP), which is set to theaddress of the register that is to be updated. The next 8 bits are the data which will be placed into the registerdesignated by the MAP. During writes, the CDOUT output stays in the Hi-Z state. It may be externally pulledhigh or low with a 47kΩ resistor, if desired.
CSCCLKCHIPADDRESSCDIN0010000R/WCHIPADDRESSLSBbytenMSBLSBMSBLSBMAPMSBDATA0010000R/Wbyte1HighImpedanceCDOUTMAP=MemoryAddressPointer,8bits,MSBfirstFigure 22. Control Port Timing in SPI Mode
There is a MAP auto-increment capability, enabled by the INCR bit in the MAP register. If INCR is a zero,then the MAP will stay constant for successive read or writes. If INCR is set to a 1, then the MAP will auto-increment after each byte is read or written, allowing block reads or writes of successive registers.To read a register, the MAP has to be set to the correct address by executing a partial write cycle whichfinishes (CS high) immediately after the MAP byte. The MAP auto-increment bit (INCR) may be set or not,as desired. To begin a read, bring CS low, send out the chip address and set the read/write bit (R/W) high.The next falling edge of CCLK will clock out the MSB of the addressed register (CDOUT will leave the high-impedance state). If the MAP auto-increment bit is set to 1, the data for successive registers will appearconsecutively.
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CS8420
9.2
I²C Mode
In I²C mode, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL, withthe clock to data relationship as shown in Figure23. There is no CS pin. Each individual CS8420 is given aunique address. Pins AD[1:0] form the two least significant bits of the chip address and should be connectedto VD+ or DGND as desired. The EMPH pin is used to set the AD2 bit, by connecting a resistor from theEMPH pin to VD+ or to DGND. The state of the pin is sensed while the CS8420 is being reset. The upperfour bits of the 7-bit address field are fixed at 0010b. To communicate with a CS8420, the chip address field,which is the first byte sent to the CS8420, should match 0010b followed by the settings of the EMPH, AD1,and AD0. The eighth bit of the address is the R/W bit. If the operation is a write, the next byte is the MemoryAddress Pointer (MAP) which selects the register to be read or written. If the operation is a read, the con-tents of the register pointed to by the MAP will be output. Setting the auto-increment bit in MAP allows suc-cessive reads or writes of consecutive registers. Each byte is separated by an acknowledge bit. The ACKbit is output from the CS8420 after each input byte is read and is input to the CS8420 from the microcon-troller after each transmitted byte.
Note1SDA0010AD2-0R/WACKNote2DATA7-0ACKDATA7-0Note3ACKSCLStartStopNotes:1.AD2 is derived from a resistor attached to the EMPH pin
AD1, and AD0 are determined by the state of the corresponding pins.
2.If operation is a write, this byte contains the Memory Address Pointer, MAP.3.If operation is a read, the last bit of the read should be NACK (high).
Figure 23. Control Port Timing in I²C Mode
9.3Interrupts
The CS8420 has a comprehensive interrupt capability. The INT output pin is intended to drive the interruptinput pin on the host microcontroller. The INT pin may be set to be active-low, active-high, or active-low withno active pull-up transistor. This last mode is used for active-low, wired-OR hook-ups, with multiple periph-erals connected to the microcontroller interrupt input pin.
Many conditions can cause an interrupt, as listed in the interrupt status register descriptions. Each sourcemay be masked via mask registers. In addition, each source may be set to rising-edge, falling-edge, or level-sensitive. Combined with the option of level-sensitive or edge-sensitive modes within the microcontroller,many different set-ups are possible, depending on the needs of the equipment designer.
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CS8420
10.CONTROL PORT REGISTER BIT DEFINITIONS
10.1
Memory Address Pointer (MAP)
6MAP6
5MAP5
4MAP4
3MAP3
2MAP2
1MAP1
0MAP0
7INCR
This register defaults to 01
INCR
Auto-Increment Address Control Bit0 -Auto-increment address off
1 -Auto-increment address on
Register address and function list0 - Reserved1 - Misc. Control 12 - Misc. Control 23 - Data Flow Control4 - Clock Source Control5 - Serial Audio Input Port Data Format6 - Serial Audio Output Port Data Format7 - Interrupt Register 1 Status8 - Interrupt Register 2 Status9 - Interrupt Register 1 Mask10 - Interrupt Register1 Mode (MSB)11 - Interrupt Register 1 Mode (LSB)12 -Interrupt Register 2 Mask
13 -Interrupt Register 2 Mode (MSB)
14 - Interrupt Register 2 Mode (LSB)15 - Receiver Channel Status Bits16 - Receiver Error Status17 - Receiver Error Mask18 - Channel Status Data Buffer Control19 - User Data Buffer Control
20 to 29 - Q-channel Subcode Bytes 0 to 930 - Sample Rate Ratio31 - Reserved
32 to 55 - C-bit or U-bit Data Buffer56 to 126 - Reserved127 - Chip ID and version register
MAP6-MAP0
Reserved registers must not be written to during normal operation. Some reserved registers are used for
test modes, which can completely alter the normal operation of the CS8420.
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CS8420
Addr(HEX)0102030405060708090A0B0C0D0E0F1011121314-1D1E20-377F
Function
Control 1Control 2
Data Flow ControlClock Source ControlSerial Input FormatSerial Output FormatInterrupt 1 StatusInterrupt 2 StatusInterrupt 1 Mask
Interrupt 1 Mode (MSB)Interrupt 1 Mode (LSB)Interrupt 2 Mask
Interrupt 2 Mode (MSB)Interrupt 2 Mode (LSB)Receiver CS DataReceiver Errors
Receiver Error MaskCS Data Buffer ControlU Data Buffer ControlQ Sub-Code DataSample Rate RatioC or U Data BufferID and Version
7
SWCLKTRUNCAMLL0SIMSSOMSTSLIP0TSLIP1TSLIP0000AUX30000SRR7ID3
6
VSETHOLD1TXOFFRUNSISFSOSFOSLIP0OSLIP1OSLIP0000AUX2QCRCQCRCM
00SRR6ID2
5
MUTESAOHOLD0AESBPCLK1SIRES1SORES1SREVFIFOSREMSRE1SRE0VFIFOMVFIFO1VFIFO0AUX1CCRCCCRCMBSEL0SRR5ID1
4
MUTEAESRMCKFTXD1CLK0SIRES0SORES0OVRGLREUNLOCKOVRGLMOVRGL1OVRGL0REUNLOCKMREUNLOCK1REUNLOCK0
AUX0UNLOCKUNLOCKMCBMRUDSRR4ID0
3
DITHMMRTXD0OUTCSIJUSTSOJUSTOVRGRDETUOVRGR1OVRGR0DETUMDETU1DETU0PROVVMDETCIUBM1SRR3VER3
2
INT1MMTSPD1INCSIDELSODELDETCEFTUDETC1DETC0EFTUMEFTU1EFTU0AUDIOCONFCONFMEFTCIUBM0SRR2VER2
1
INT0MMTCSSPD0RXD1SISPOLEFTCQCHEFTCMEFTC1EFTC0QCHMQCH1QCH0COPYBIPBIPMCAMDETUISRR1VER1
0
TCBLDMMTLRSRCDRXD0SILRPOLRERRUOVWRERRMRERR1RERR0UOVWMUOVW1UOVW0ORIGPARPARMCHSEFTUISRR0VER0
SOSPOLSOLRPOL
TSLIPMOSLIPMOVRGRMDETCM
Table 4. Summary of all Bits in the Control Register Map
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CS8420
10.2
Miscellaneous Control 1 (01h)
6VSET
5
MUTESAO
4
MUTEAES
3DITH
2INT1
1INT0
0TCBLD
7SWCLK
SWCLK
Causes OMCK to be output through the RMCK pin when the PLL is unlocked0 - RMCK is driven by the PLL VCO (default)
1 - OMCK is switched to output through the RMCK pin when the PLL is unlocked. Circuitry driv-en by the PLL is driven by OMCK.
Transmitted V bit level
0 - Transmit a 0 for the V bit, indicating that the data is valid, and is normally linear PCM audio (default)
1 - Transmit a 1 for the V bit, indicating that the data is invalid or is not linear PCM audio dataMute control for the serial audio output port0 - Normal output (default)
1 - Mute the serial audio output portMute control for the AES3 transmitter output0 - Normal output (default)
1 - Mute the AES3 transmitter output
Dither Control
0 - Triangular PDF dither applied to output data. The level of the dither is automatically adjusted to be appropriate for the output word length selected by the SORES bits (default)1 - No dither applied to output data.
Interrupt (INT) output pin control
00 - Active high, high output indicates an interrupt condition has occurred (default)01 - Active low, low output indicates an interrupt condition has occurred
10 - Open drain, active low. This setting requires an external pull up resistor on the INT pin.11 - Reserved
Transmit Channel Status Block pin (TCBL) direction specifier0 - TCBL is an input (default)1 - TCBL is an output
VSET
MUTESAO
MUTEAES
DITH
INT[1:0]
TCBLD
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CS8420
10.3
Miscellaneous Control 2 (02h)
6HOLD1
5HOLD0
4RMCKF
3MMR
2MMT
1MMTCS
0MMTLR
7TRUNC
TRUNC
Determines whether the word length is set according to the incoming Channel Status data0 - Data to the SRC is not truncated (default)
1 - Data to the SRC is set according to the AUX field in the incoming data streamThe HOLD bits determine how the received audio sample is affected when a receivererror occurs.
00 - Hold the last valid audio sample (default)
01 - Replace the current audio sample with 00 (mute)10 - Do not change the received audio sample11 - Reserved
Select recovered master clock output pin frequency. 0 - RMCK is equal to 256 * Fsi (default)1 - RMCK is equal to 128 * Fsi
Select AES3 receiver mono or stereo operation
0 - Interpret A and B subframes as two independent channels (normal stereo operation, default)1 - Interpret A and B subframes as consecutive samples of one channel of data.This data is duplicated to both left and right parallel outputs of the AES receiver block. The input sample rate (Fsi) is doubled compared to MMR=0
Select AES3 transmitter mono or stereo operation
0 - Outputs left channel input into A subframe and right channel input into B subframe (normal stereo operation, default).
1 - Output either left or right channel inputs into consecutive subframe outputs (mono mode, left or right is determined by MMTLR bit)
Select A or B channel status data to transmit in mono mode
0 - Use channel A CS data for the A sub-frame slot and use channel B CS data for the B sub-frame slot (default)
1 - Use the same CS data for both the A and B sub-frame output slots. If MMTLR = 0, use the left channel CS data. If MMTLR = 1, use the right channel CS data.Channel Selection for AES Transmitter mono mode
0 - Use left channel input data for consecutive sub-frame outputs (default)1 - Use right channel input data for consecutive sub-frame outputs
HOLD[1:0]
RMCKF
MMR
MMT
MMTCS
MMTLR
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CS8420
10.4
Data Flow Control (03h)
6TXOFF
5AESBP
4TXD1
3TXD0
2SPD1
1SPD0
0SRCD
7AMLL
The Data Flow Control register configures the flow of audio data to/from the following blocks: Serial Audio Input Port, Serial Audio Output Port, AES3 receiver, AES3 transmitter, and Sample Rate Converter. In conjunction with the Clock Source Control register, multiple Receiver/Trans-mitter/Transceiver modes may be selected. The output data should be muted prior to changing bits in this register to avoid transients.
AMLL
Auto Mutes the SRC data sink when Receiver lock is lost, zero data is transmitted. The SRC data sink may be either, or both, the Transmitter and the Serial Audio Output Port.0 - Disables Auto Mute on loss of lock (default)1 - Enables Auto Mute on loss of lock
AES3 Transmitter Output Driver Control
0 - AES3 transmitter output pin drivers normal operation (default)1 - AES3 transmitter output pin drivers drive to 0V.
AES3 bypass mode selection0 - normal operation
1 - Connect the AES3 transmitter driver input directly to the RXP pin, which become a normal TTL threshold digital input.AES3 Transmitter Data Source00 - SRC output (default)01 - Serial audio input port10 - AES3 receiver11 - Reserved
Serial Audio Output Port Data Source00 - SRC output (default)01 - Serial Audio Input Port10 - AES3 receiver11 - Reserved
Input Data Source for SRC
0 - Serial Audio Input Port (default)1 - AES3 Receiver
TXOFF
AESBP
TXD[1:0]
SPD[1:0]
SRCD
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CS8420
10.5
70
Clock Source Control (04h)
6RUN
5CLK1
4CLK0
3OUTC
2INC
1RXD1
0RXD0
This register configures the clock sources of various blocks. In conjunction with the Data Flow Control register, various Receiver/Transmitter/Transceiver modes may be selected.
RUN
The RUN bit controls the internal clocks, allowing the CS8420 to be placed in a “powered down”, low current consumption, state.
0 - Internal clocks are stopped. Internal state machines are reset. The fully staticcontrol port is operational, allowing registers to be read or changed. Reading andwriting the U and C data buffers is not possible. Power consumption is low (default).1 - Normal part operation. This bit must be written to the 1 state to allow the CS8420to begin operation. All input clocks should be stable in frequency and phase whenRUN is set to 1.
Output side master clock input (OMCK) frequency to output sample rate (Fso) ratio selector. If these bits are changed during normal operation, then always stop the CS8420 first (RUN = 0), then write the new value, then start the CS8420 (RUN = 1).00 - OMCK frequency is 256*Fso(default)01 - OMCK frequency is 384*Fso10 - OMCK frequency is 512*Fso11 - reserved
Output Time Base
0 - OMCK input pin (modified by the selected divide ratio bits CLK1 & CLK0,(default)
1 - Recovered Input Clock
Input Time Base Clock Source
0 - Recovered Input Clock (default)
1 - OMCK input pin (modified by the selected divide ratio bits CLK1 & CLK0)
Recovered Input Clock Source
00 - 256*Fsi, where Fsi is derived from the ILRCK pin (only possible when theserial audio input port is in Slave mode, default)
01 - 256*Fsi, where Fsi is derived from the AES3 input frame rate
10 - Bypass the PLL and apply an external 256*Fsi clock via the RMCK pin. The AES3receiver is held in synchronous reset. This setting is useful to prevent UNLOCKinterrupts when using an external RMCK and inputting data via the serial audio input port.11 - Reserved
CLK[1:0]
OUTC
INC
RXD[1:0]
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CS8420
10.6
Serial Audio Input Port Data Format (05h)
6SISF
5SIRES1
4SIRES0
3SIJUST
2SIDEL
1SISPOL
0SILRPOL
7SIMS
SIMS
Master/Slave Mode Selector
0 - Serial audio input port is in Slave mode (default)1 - Serial audio input port is in Master modeISCLK frequency (for Master mode)0 - 64*Fsi (default)1 - 128*Fsi
Resolution of the input data, for right-justified formats00 - 24 bit resolution (default)01 - 20 bit resolution10 - 16 bit resolution11 - Reserved
Justification of SDIN data relative to ILRCK0 - Left-Justified (default)1 - Right-Justified
Delay of SDIN data relative to ILRCK, for left-justified data formats
0 - MSB of SDIN data occurs in the first ISCLK period after the ILRCK edge (default)1 - MSB of SDIN data occurs in the second ISCLK period after the ILRCK edgeISCLK clock polarity
0 - SDIN sampled on rising edges of ISCLK (default)1 - SDIN sampled on falling edges of ISCLK
ILRCK clock polarity
0 - SDIN data is for the left channel when ILRCK is high (default)1 - SDIN data is for the right channel when ILRCK is high
SISF
SIRES[1:0]
SIJUST
SIDEL
SISPOL
SILRPOL
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CS8420
10.7
Serial Audio Output Port Data Format (06h)
6SOSF
5SORES1
4SORES0
3SOJUST
2SODEL
1SOSPOL
0
SOLRPOL
7SOMS
SOMS
Master/Slave Mode Selector
0 - Serial audio output port is in Slave mode (default)1 - Serial audio output port is in Master modeOSCLK frequency (for Master mode)0 - 64*Fso (default)1 - 128*Fso
Resolution of the output data on SDOUT and AES3 output when the sample rate converter is set as the source
00 - 24 bit resolution (default)01 - 20 bit resolution10 - 16 bit resolution
11 - Direct copy of the received NRZ data from the AES3 receiver (including C, U, andV bits, the time slot normally occupied by the P bit is used to indicate the locationof the block start, SDOUT pin only, serial audio output port clock must be derivedfrom the AES3 receiver recovered clock)Justification of SDOUT data relative to OLRCK0 - Left-Justified (default)
1 - Right-Justified (Master mode only)
Delay of SDOUT data relative to OLRCK, for left-justified data formats
0 - MSB of SDOUT data occurs in the first OSCLK period after the OLRCK edge (default)
1 - MSB of SDOUT data occurs in the second OSCLK period after the OLRCK edgeOSCLK clock polarity
0 - SDOUT transitions occur on falling edges of OSCLK (default)1 - SDOUT transitions occur on rising edges of OSCLK
OLRCK clock polarity
0 - SDOUT data is for the left channel when OLRCK is high (default)1 - SDOUT data is for the right channel when OLRCK is high
SOSF
SORES[1:0]
SOJUST
SODEL
SOSPOL
SOLRPOL
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CS8420
10.8
Interrupt 1 Register Status (07h) (Read Only)
6OSLIP
5SRE
4OVRGL
3OVRGR
2DETC
1EFTC
0RERR
7TSLIP
For all bits in this register, a “1” means the associated interrupt condition has occurred at least once since the register was last read. A”0” means the associated interrupt condition has NOT occurred since the last reading of the register. Reading the register resets all bits to 0, unless the interrupt mode is set to level and the interrupt source is still true. Status bits that are masked off in the associated mask register will always be “0” in this register. This register defaults to 00.
TSLIP
AES3 transmitter source data slip interrupt. In data flows with no SRC, and where OMCK, which clocks the AES3 transmitter, is asynchronous to the data source, this bit will go high every time a data sample is dropped or repeated. Also, when TCBL is an input, and when the SRC is not in use, this bit will go high on receipt of a new TCBL signal.
Serial audio output port data slip interrupt. When the serial audio output port is in Slave mode, and OLRCK is asynchronous to the port data source, this bit will go high every time a data sam-ple is dropped or repeated. Also, when the SRC is used, and the SRC output goes to the output serial port configured in Slave mode, this bit will indicate if the ratio of OMCK frequency to OL-RCK frequency does not match what is set in the CLK1 and CLK0 bits.Sample rate range exceeded indicator. Occurs if Fsi/Fso or Fso/Fsi exceeds 3.
Over-range indicator for left (A) channel SRC output. Occurs on internal over-range for left channel data. Note that the CS8420 automatically clips over-ranges to plus or minus full scale.Over-range indicator for right (B) channel SRC output. Occurs on internal over-range for right channel data. Note that the CS8420 automatically clips over-ranges to plus or minus full scaleD to E C-buffer transfer interrupt. The source for this bit is true during the D to E buffer transfer in the C bit buffer management process.
E to F C-buffer transfer interrupt. The source for this bit is true during the E to F buffer transfer in the C bit buffer management process.
A receiver error has occurred. The Receiver Error register may be read to determine the nature of the error which caused the interrupt.
OSLIP
SREOVRGLOVRGRDETCEFTCRERR
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CS8420
10.9
7
0
Interrupt Register 2 Status (08h) (Read Only)
6
0
5
VFIFO
4
REUNLOCK
3
DETU
2
EFTU
1
QCH
0
UOVW
For all bits in this register, a “1” means the associated interrupt condition has occurred at least once since the register was last read. A”0” means the associated interrupt condition has NOT occurred since the last reading of the register. Reading the register resets all bits to 0, unless the interrupt mode is set to level and the interrupt source is still true. Status bits that are masked off in the associated mask register will always be “0” in this register. This register defaults to 00.
VFIFOREUNLOCKDETUEFTUQCHUOVW
Varispeed FIFO overflow indicator. Occurs if the data buffer in the SRC overflows. This will oc-cur if the input sample rate slows too fast.
Sample rate converter unlock indicator. This interrupt occurs if the SRC is still tracking a chang-ing input or output sample rate.
D to E U-buffer transfer interrupt. The source of this bit is true during the D to E buffer transfer in the U bit buffer management process (block mode only).
E to F U-buffer transfer interrupt. The source of this bit is true during the E to F buffer transfer in the U bit buffer management process (block mode only).
A new block of Q-subcode data is available for reading. The data must be completely read with-in 588 AES3 frames after the interrupt occurs to avoid corruption of the data by the next block.U-bit FIFO Overwrite. This interrupt occurs on an overwrite in the U-bit FIFO.
10.10Interrupt 1 Register Mask (09h)
7TSLIPM
6OSLIPM
5SREM
4OVRGLM
3OVRGRM
2DETCM
1EFTCM
0RERRM
The bits of this register serve as a mask for the Interrupt 1 Register. If a mask bit is set to 1, the error isconsidered unmasked, meaning that its occurrence will affect the INT pin and the status register. If a maskbit is set to 0, the error is considered masked, meaning that its occurrence will not affect the INT pin or thestatus register. The bit positions align with the corresponding bits in Interrupt Register 1. This register de-faults to 00.
10.11Interrupt Register 1 Mode Registers MSB & LSB (0Ah,0Bh)
7TSLIP1TSLIP0
6OSLIP1OSLIP0
5SRE1SRE0
4OVRGL1OVRGL0
3OVRGR1OVRGR0
2DETC1DETC0
1EFTC1EFTC0
0RERR1RERR0
The two Interrupt Mode registers form a 2-bit code for each Interrupt Register 1 function. This code deter-mines whether the INT pin is set active on the arrival of the interrupt condition, on the removal of the interruptcondition, or on the continuing occurrence of the interrupt condition. These registers default to 00.00 - Rising edge active01 - Falling edge active10 - Level active11 - Reserved
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CS8420
10.12Interrupt 2 Register Mask (0Ch)
70
60
5VFIFOM
4
REUNLOCKM
3DETUM
2EFTUM
1QCHM
0UOVWM
The bits of this register serve as a mask for the Interrupt 2 Register. If a mask bit is set to 1, the error isconsidered unmasked, meaning that its occurrence will affect the INT pin and the status register. If a maskbit is set to 0, the error is considered masked, meaning that its occurrence will not affect the INT pin or thestatus register. The bit positions align with the corresponding bits in Interrupt Register 2. This register de-faults to 00.
10.13Interrupt Register 2 Mode Registers MSB & LSB (0Dh,0Eh)
700
600
5VFIFO1VFIFO0
4
REUNLOCK1REUNLOCK0
3DETU1DETU0
2EFTU1EFTU0
1QCH1QCH0
0UOVW1UOVW0
The two Interrupt mode registers form a 2-bit code for each Interrupt 2 register function. This code deter-mines whether the INT pin is set active on the arrival of the interrupt condition, on the removal of the interruptcondition, or on the continuing occurrence of the interrupt condition. These registers default to 00.00 - Rising edge active01 - Falling edge active10 - Level active11 - Reserved
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CS8420
10.14Receiver Channel Status (0Fh) (Read Only)
7AUX3
6AUX2
5AUX1
4AUX0
3PRO
2AUDIO
1COPY
0ORIG
The bits in this register can be associated with either channel A or B of the received data. The desired channel is selected with the CHS bit of the Channel Status Data Buffer Control Regis-ter.
AUX[3:0]
The AUX3-0 bits indicate the width of the incoming auxiliary data field, as indicated by the in-coming channel status bits, decoded according to IEC60958 and AES3.0000 - Auxiliary data is not present0001 - Auxiliary data is 1 bit long0010 - Auxiliary data is 2 bits long0011 - Auxiliary data is 3 bits long0100 - Auxiliary data is 4 bits long 0101 - Auxiliary data is 5 bits long0110 - Auxiliary data is 6 bits long0111 - Auxiliary data is 7 bits long1000 - Auxiliary data is 8 bits long1001 - 1111 Reserved
Channel status block format indicator
0 - Received channel status block is in consumer format1 - Received channel status block is in professional formatAudio indicator
0 - Received data is linearly coded PCM audio1 - Received data is not linearly coded PCM audioSCMS copyright indicator0 - Copyright asserted1 - Copyright not asserted
SCMS generation indicator. This is decoded from the category code and the L bit.0 - Received data is 1st generation or higher1 - Received data is original
COPY and ORIG will both be set to 1 if the incoming data is flagged as professional or if the receiver is not in use.
PRO
AUDIO
COPY
ORIG
Note:
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CS8420
10.15Receiver Error (10h) (Read Only)
70
6QCRC
5CCRC
4UNLOCK
3V
2CONF
1BIP
0PAR
This register contains the AES3 receiver and PLL status bits. Unmasked bits will go high on occurrence of the error, and will stay high until the register is read. Reading the register resets all bits to 0, unless the error source is still true. Bits that are masked off in the receiver error mask register will always be 0 in this register. This register defaults to 00.
QCRC
Q-subcode data CRC error has occurred. Updated on Q-subcode block boundaries.0 - No error1 - Error
Channel Status Block Cyclic Redundancy Check bit. Updated on CS block boundaries.This bit is valid in Professional mode only.0 - No error1 - Error
PLL lock status bit. Updated on CS block boundaries.0 - PLL locked1 - PLL out of lock
Received AES3 Validity bit status. Updated on sub-frame boundaries.0 - Data is valid and is normally linear coded PCM audio1 - Data is invalid, or may be valid compressed audio
Confidence bit. Updated on sub-frame boundaries.0 - No error
1 - Confidence error. This indicates that the received data eye opening is less thanhalf a bit period, indicating a poor link that is not meeting specifications.Bi-phase error bit. Updated on sub-frame boundaries.0 - No error
1 - Bi-phase error. This indicates an error in the received bi-phase coding.Parity bit. Updated on sub-frame boundaries.0 - No error1 - Parity error
CCRC
UNLOCK
V
CONF
BIP
PAR
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CS8420
10.16Receiver Error Mask (11h)
70
6QCRCM
5CCRCM
4
UNLOCKM
3VM
2CONFM
1BIPM
0PARM
The bits in this register serve as masks for the corresponding bits of the Receiver Error Regis-ter. If a mask bit is set to 1, the error is considered unmasked, meaning that its occurrence will appear in the receiver error register, will affect the RERR pin, will affect the RERR interrupt, and will affect the current audio sample according to the status of the HOLD bit. If a mask bit is set to 0, the error is considered masked, meaning that its occurrence will not appear in the receiver error register, will not affect the RERR pin, will not affect the RERR interrupt, and will not affect the current audio sample. The CCRC and QCRC bits behave differently from the other bits: they do not affect the current audio sample even when unmasked. This register defaults to 00.
10.17Channel Status Data Buffer Control (12h)
70
60
5BSEL
4CBMR
3DETCI
2EFTCI
1CAM
0CHS
BSEL
Selects the data buffer register addresses to contain User data or Channel Status data0 - Data buffer address space contains Channel Status data (default)1 - Data buffer address space contains User data
Control for the first 5 bytes of channel status “E” buffer
0 - Allow D to E buffer transfers to overwrite the first 5 bytes of channel status data(default)
1 - Prevent D to E buffer transfers from overwriting first 5 bytes of channel status dataD to E C-data buffer transfer inhibit bit.
0 - Allow C-data D to E buffer transfers (default)1 - Inhibit C-data D to E buffer transfersE to F C-data buffer transfer inhibit bit.
0 - Allow C-data E to F buffer transfers (default)1 - Inhibit C-data E to F buffer transfersC-data buffer control port access mode bit0 - One byte mode1 - Two byte mode
Channel select bit
0 - Channel A information is displayed at the EMPH pin and in the receiver channelstatus register. Channel A information is output during control port reads whenCAM is set to 0 (One Byte Mode)
1 - Channel B information is displayed at the EMPH pin and in the receiver channelstatus register. Channel B information is output during control port reads whenCAM is set to 0 (One Byte Mode)
CBMR
DETCI
EFTCI
CAM
CHS
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CS8420
10.18User Data Buffer Control (13h)
70
60
50
4UD
3UBM1
2UBM0
1DETUI
0EFTUI
UD
User data pin (U) direction specifier
0 - The U pin is an input. The U data is latched in on both rising and falling edges ofOLRCK. This setting also chooses the U pin as the source for transmittedU data (default).
1 - The U pin is an output. The received U data is clocked out on both rising and falling edgesof ILRCK. This setting also chooses the U data buffer as the source of transmittedU data.
Sets the operating mode of the AES3 U bit manager00 - Transmit all zeros mode (default)01 - Block mode10 - Reserved
11 - IEC consumer mode B
D to E U-data buffer transfer inhibit bit (valid in block mode only). 0 - Allow U-data D to E buffer transfers (default)1 - Inhibit U-data D to E buffer transfers
E to F U-data buffer transfer inhibit bit (valid in block mode only). 0 - Allow U-data E to F buffer transfers (default)1 - Inhibit U-data E to F buffer transfer
UBM[1:0]
DETUI
EFTUI
Q-Channel Subcode Bytes 0 to 9 (14h - 1Dh) (Read Only)
The following 10 registers contain the decoded Q-channel subcode data
76543210CONTROLCONTROLCONTROLCONTROLADDRESSADDRESSADDRESSADDRESSTRACKTRACKTRACKTRACKTRACKTRACKTRACKTRACKINDEXINDEXINDEXINDEXINDEXINDEXINDEXINDEXMINUTEMINUTEMINUTEMINUTEMINUTEMINUTEMINUTEMINUTESECONDSECONDSECONDSECONDSECONDSECONDSECONDSECONDFRAMEFRAMEFRAMEFRAMEFRAMEFRAMEFRAMEFRAMEZEROZEROZEROZEROZEROZEROZEROZEROABS MINUTEABS MINUTEABS MINUTEABS MINUTEABS MINUTEABS MINUTEABS MINUTEABS MINUTEABS SECONDABS SECONDABS SECONDABS SECONDABS SECONDABS SECONDABS SECONDABS SECONDABS FRAMEABS FRAMEABS FRAMEABS FRAMEABS FRAMEABS FRAMEABS FRAMEABS FRAME
Each byte is LSB first with respect to the 80 Q-subcode bits Q[79:0]. Thus bit 7 of address 14h is Q[0] whilebit 0 of address 14h is Q[7]. Similarly bit 0 of address 1Dh corresponds to Q[79].
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CS8420
10.19Sample Rate Ratio (1Eh) (Read Only)
7SRR7
6SRR6
5SRR5
4SRR4
3SRR3
2SRR2
1SRR1
0SRR0
The Sample Rate Ratio is Fso divided by Fsi. This value is represented as an integer and a fractional part. The value is meaningful only after the both the PLL and SRC have reached lock, and the SRC output is being used
SRR[7:6SRR[5:0]
The integer part of the sample rate ratioThe fractional part of the sample rate ratio
10.20C-Bit or U-Bit Data Buffer (20h - 37h)
Either channel status data buffer E or user data buffer E (provided UBM bits are set to block mode) is ac-cessible via these register addresses.
10.21CS8420 I.D. and Version Register (7Fh) (Read Only)
7ID3
6ID2
5ID1
4ID0
3VER3
2VER2
1VER1
ID3VER0
ID[3:0]VER[3:0]
ID code for the CS8420. Permanently set to 0001CS8420 Revision Level: Revision B is coded as 0001Revision C is coded as 0011Revision D is coded as 0100
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CS8420
11.SYSTEM AND APPLICATIONS ISSUES
11.1
Reset, Power Down and Start-up Options
When RST is low, the CS8420 enters a low-power mode. All internal states are reset, including the controlport and registers, and the outputs are muted. When RST is high, the control port becomes operational, andthe desired settings should be loaded into the control registers. Writing a 1 to the RUN bit will then causethe part to leave the low-power state and begin operation. After the PLL and the SRC have settled, the AES3and serial audio outputs will be enabled.
Some options within the CS8420 are controlled by a start-up mechanism. During the reset state, some ofthe output pins are reconfigured internally to be inputs. Immediately upon exiting the reset state, the levelof these pins is sensed. The pins are then switched to be outputs. This mechanism allows output pins to beused to set alternative modes in the CS8420 by connecting a 47kΩ resistor between the pin and either VD+(High) or DGND (Low). For each mode, every start-up option select pin MUST have an external pull-up orpull-down resistor. In software mode, the only start-up option pin is EMPH, which is used to set a chip ad-dress bit for the control port in I²C mode. Hardware modes use many start-up options, which are detailed inthe hardware definition section at the end of this data sheet.
11.2Transmitter Startup
When the CS8420 is taken out of power-down and the AES3 receiver is configured to be in-circuit, the partuses the clock recovered from the AES3 input stream to advance its internal state machine to run. This canbe a problem if no valid AES3 stream is present at the RXP/RXN pins and data input through the serial audioport needs to be output through the AES3 transmitter.
To complete initialization and begin operation when the AES3 receiver is in-circuit and no valid AES3 inputstream is presented to the RXP/RXN pins, the user must execute the following sequence:1.Place the CS8420 in power-down (RUN=0).
2.Set the serial audio input and output ports to Slave mode (SIMS=0, SOMS=0).3.Set the input and output time base to the OMCK input pin (OUTC=0, INC=1).4.Configure the SRC to receive its input from the serial audio input port (SRCD=0).
5.Configure the serial audio output port to receive its input from the serial audio input port (SPD[1:0]=01).6.Configure the AES3 transmitter to receive its input from the serial audio input port (TXD[1:0]=01).7.Set the RUN bit (RUN=1).
After completing steps 1-7, the transmitter will function properly, and the data flow can be altered for theapplication without powering down.
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CS8420
11.3
SRC Invalid State
Occasionally the CS8420 SRC will enter an invalid state. This can happen after the RUN bit has been setwhen an AES3 stream is first plugged into the part or when a source device interrupts the SRC input stream.When this happens, two symptoms may be noticeable: notches occurring in the frequency response andspurious tones being generated in response to some input frequencies.
To avoid this problem in Software mode, use the microcontroller to monitor the UNLOCK bit in control reg-ister 10h. When the part achieves lock, clear the RUN bit in register 4 and then set it again. This will resetall internal state machines. Alternately, the user may use the following sequence:1.Power on CS8420.
2.Write the following register sequence:
Register04h03h04h
3.Wait for PLL to lock.4.Wait 250ms for SRC to lock.
5.Write the following register sequence:
Register03h04h
6.If PLL goes out of lock, start at step 2 and repeat.
When synchronizing multiple CS8420s, wait for all PLLs to lock before continuing to the next step. Theseactions clear the invalid state if it has occurred.
In Hardware mode, monitor the RERR pin for receiver lock status. When the part achieves lock, set the RSTpin low for at least 200μs and then set it high again. This action clears the invalid state if it has occurred.When polling the RERR pin again, the user must account for the fact that the RERR pin will be high duringreset and remain high until the PLL has reachieved lock.
In either Software or Hardware mode, when clearing the invalid state, it is advisable to mute any devicesconnected to the output of the CS8420.
Value81h41hValue09h95h49h
11.4C/U Buffer Data Corruption
Occasionally the C/U buffer data may be corrupted. This can happen after the RUN bit has been set anddata has been written to the C/U buffer (20h-37h). If no further data is written to the C buffer after the initialwrite and the receiver input is interrupted multiple times, the contents of the buffer may be reset to all zeros.The buffer will not be corrupted if the buffer data is being updated, only when the data is static and the re-ceiver input has been interrupted multiple times.
To avoid this problem in Software mode when the C/U buffer contents should remain static, use the micro-controller to monitor the UNLOCK bit in control register 10h or the RERR pin. If the part indicates the PLLhas lost lock, rewrite the C/U buffer data. Repeat this action every time the PLL goes out of lock.
In Hardware mode, this limitation does not exist as the serial C/U data is being fed directly to the transmitter.
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CS8420
11.5
Block-Mode U-Data D-to-E Buffer Transfers
When Fsi≠Fso, Block-Mode U-data transfers from the D buffer to the E buffer are not synchronous to theinput clock domain. D-to-E buffer transfers can always be detected by the activation of the DETU bit (bit 3in register 08h) when Fsi≠Fso or Fsi=Fso. IEC Consumer B mode, serial U-data output, and the Q-channel subcode bytes (registers 14h - 1Dh) are unaffected by the input/output sample rate relationship.
11.6ID Code and Revision Code
The CS8420 has a register that contains a 4-bit code to indicate that the addressed device is a CS8420.This is useful when other CS84xx family members are resident in the same system, allowing common soft-ware modules.
The CS8420 4-bit revision code is also available. This allows the software driver for the CS8420 to identifywhich revision of the device is in a particular system, and modify its behavior accordingly. To allow for futurerevisions, it is strongly recommend that the revision code is read into a variable area within the microcon-troller, and used wherever appropriate as revision details become known.
11.7Power Supply, Grounding, and PCB layout
For most applications, the CS8420 can be operated from a single +5V supply, following normal supply de-coupling practice (see Figure 5. “Recommended Connection Diagram for Software Mode” on page 12). Forapplications where the recovered input clock, output on the RMCK pin, is required to be low-jitter, then usea separate, quiet, analog +5V supply for VA+, decoupled to AGND. In addition, a separate region of analogground plane around the FILT, AGND, VA+, RXP and RXN pins is recommended.
The VD+ supply should be well-decoupled with a 0.1μF capacitor to DGND to minimize AES3 transmitterinduced transients.
Extensive use of power and ground planes, ground plane fill in unused areas and surface mount decouplingcapacitors are recommended. Make sure decoupling capacitors are mounted on the same side of the boardas the CS8420, to minimize via inductance effects. All decoupling capacitors should be as close to theCS8420 as possible.
11.8Synchronization of Multiple CS8420s
The serial audio output ports of multiple CS8420s can be synchronized by sharing the same master clock,OSCLK, OLRCK, and RST line and ensuring that all devices leave the reset state on the same master clockfalling edge. Either all the ports need to be in Slave mode, or one can be set as a master.
The AES3 transmitters may be synchronized by sharing the same master clock, TCBL, and RST signals,and ensuring all devices leave the reset state on the same master clock falling edge. The TCBL pin is usedto synchronize multiple CS8420 AES3 transmitters at the channel status block boundaries. One CS8420must have its TCBL set to master; the others must be set to slave TCBL. Alternatively, TCBL can be derivedfrom some external logic, in which case all the CS8420 devices should be set to slave TCBL.
11.9Extended Range Sample Rate Conversion
For handling sampling rate conversion ratios greater than 3:1 or less than 1:3, the user can use a cascadeof two devices. The product of the conversion ratio of the two devices should equal the target conversionratio.
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CS8420
12.SOFTWARE MODE - PIN DESCRIPTION
The above diagram and the following pin descriptions apply to Software mode. In Hardware mode, some pinschange their function as described in subsequent sections of this data sheet. Fixed function pins are marked with a*, and will be described once in this section. Pins marked with a + are used upon reset to select various start-upoptions, and require a pull-up or pull-down resistor.
Power Supply Connections:VD+ - Positive Digital Power *
Positive supply for the digital section. Nominally +5.0V.VA+ - Positive Analog Power *
Positive supply for the analog section. Nominally +5.0V. This supply should be as quiet as possible since noise onthis pin will directly affect the jitter performance of the recovered clock.DGND - Digital Ground *
Ground for the digital section. DGND should be connected to the same ground as AGND.AGND - Analog Ground *
Ground for the analog section. AGND should be connected to the same ground as DGND.
Clock-Related Pins:OMCK - Output Section Master Clock Input
Output section master clock input. The frequency must be 256x, 384x, or 512x the output sample rate (Fso).RMCK - Input Section Recovered Master Clock Output
Input section recovered master clock output. Will be at a frequency of 128x or 256x the input sample rate (Fsi).
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CS8420
FILT - PLL Loop Filter *
An RC network should be connected between this pin and ground. Recommended schematic and component val-ues are given in “PLL Filter” on page87.
Overall Device Control:H/S - Hardware or Software Control Mode Select *
The H/S pin determines the method of controlling the operation of the CS8420, and the method of accessing CSand U data. In Software mode, device control and CS and U data access is primarily via the control port, using amicrocontroller. In Hardware mode, alternate modes and access to CS and U data is provided by pins. This pinshould be permanently tied to VD+ or DGND.RST - Reset Input *
When RST is low, the CS8420 enters a low-power mode and all internal states are reset. On initial power-up, RSTmust be held low until the power supply is stable, and all input clocks are stable in frequency and phase. This isparticularly true in Hardware mode with multiple CS8420 devices, where synchronization between devices is impor-tant.
INT - Interrupt Output
The INT output pin indicates errors and key events during the operation of the CS8420. All bits affecting INT aremaskable via control registers. The condition(s) that initiated interrupt are readable via a control register. The polarityof the INT output, as well as selection of a standard or open-drain output, is set via a control register. Once set true,the INT pin goes false only after the interrupt status registers have been read, and the interrupt status bits have re-turned to zero.
Audio Input Interface:SDIN - Serial Audio Input Port Data InputAudio data serial input pin.
ISCLK - Serial Audio Input Port Bit Clock Input or OutputSerial bit clock for audio data on the SDIN pin.
ILRCK - Serial Audio Input Port Left/Right Clock Input or Output
Word rate clock for the audio data on the SDIN pin. The frequency will be at the input sample rate (Fsi)
AES3/SPDIF Receiver Interface:RXP, RXN - Differential Line Receiver Inputs
Differential line receiver inputs, carrying AES3-type data.RERR - Receiver Error Indicator
When high, indicates a problem with the operation of the AES3 receiver. The status of this pin is updated once persub-frame of incoming AES3 data. Conditions that can cause RERR to go high are: validity, parity error, bi-phasecoding error, confidence, QCRC and CCRC errors, as well as loss of lock in the PLL. Optionally, each condition maybe masked from affecting the RERR pin using the Receiver Error Mask Register. The RERR pin tracks the statusof the unmasked errors: the pin goes high as soon as an unmasked error occurs and goes low immediately whenall unmasked errors go away.
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CS8420
EMPH - Pre-Emphasis Indicator Output
EMPH is low when the incoming AES3 data indicates the presence of 50/15μs pre-emphasis. When the AES3 dataindicates the absence of pre-emphasis or the presence of other than 50/15μs pre-emphasis EMPH is high. This isalso a start-up option pin, and requires a 47kΩ resistor to either VD+ or DGND, which determines the AD2 addressbit for the control port in I²C mode.
Audio Output Interface:SDOUT - Serial Audio Output Port Data OutputAudio data serial output pin.
OSCLK - Serial Audio Output Port Bit Clock Input or OutputSerial bit clock for audio data on the SDOUT pin.
OLRCK - Serial Audio Output Port Left/Right Clock Input or Output
Word rate clock for the audio data on the SDOUT pin. The frequency will be at the output sample rate (Fso)
AES3/SPDIF Transmitter Interface:TCBL - Transmit Channel Status Block Start
This pin can be configured as an input or output. When operated as output, TCBL is high during the first sub-frameof a transmitted channel status block, and low at all other times. When operated as input, driving TCBL high for atleast three OMCK (or RMCK, depending on which clock is operating the AES3 encoder block) clocks will cause thenext transmitted sub-frame to be the start of a channel status block.TXN, TXP - Differential Line Driver Outputs
Differential line driver outputs, transmitting AES3 type data. Drivers are pulled to low while the CS8420 is in the resetstate.
Control Port Signals:SCL/CCLK - Control Port Clock
SCL/CCLK is the serial control interface clock, and is used to clock control data bits into and out of the CS8420.AD0/CS - Address Bit 0 (I²C) / Control Port Chip Select (SPI)
A falling edge on this pin puts the CS8420 into SPI Control Port mode. With no falling edge, the CS8420 defaults toI²C mode. In I²C mode, AD0 is a chip address pin. In SPI mode, CS is used to enable the control port interface onthe CS8420.
AD1/CDIN - Address Bit 1 (I²C) / Serial Control Data In (SPI)
In I²C mode, AD1 is a chip address pin. In SPI mode, CDIN is the input data line for the control port interfaceSDA/CDOUT - Serial Control Data I/O (I²C) / Data Out (SPI)
In I²C mode, SDA is the control I/O data line. SDA is open drain and requires an external pull-up resistor to VD+. InSPI mode, CDOUT is the output data from the control port interface on the CS8420.
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CS8420
Miscellaneous Pins:U - User Data
The U pin may optionally be used to input User data for transmission by the AES3 transmitter (see Figure20 fortiming information). Alternatively, the U pin may be set to output User data from the AES3 receiver (see Figure19for timing information). If not driven, a 47kΩ pull-down resistor is recommended for the U pin since the default stateof the UD direction bit sets the U pin as an input. The pull-down resistor ensures that the transmitted user data willbe zero. If the U pin is always set to be an output, thereby causing the U bit manager to be the source of the U data,the resistor is not necessary. The U pin should not be tied directly to ground in case it is programmed to be an outputand subsequently tries to output a logic high. This situation may affect the long-term reliability of the device. If the Upin is driven by a logic level output, a 100Ω series resistor is recommended.
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CS8420
13.HARDWARE MODES
13.1
Overall Description
The CS8420 has six Hardware modes, which allow use of the device without using a micro-controller to ac-cess the device control registers and CS & U data. The flexibility of the CS8420 is necessarily limited inHardware mode. Various pins change function in Hardware mode, and various data paths are also possible.These alternatives are identified by Hardware mode numbers 1 through 6. The following sections describethe data flows and pin definitions for each Hardware mode.
13.1.1Hardware Mode Definitions
Hardware mode is selected by connecting the H/S pin to ‘1’. In Hardware mode, 3 pins (DFC0, DFC1 &S/AES) determine the Hardware mode number, according to Table5. Start-up options are used exten-sively in Hardware mode. Options include whether the serial audio output ports are master or slave, theserial audio ports’ format and whether TCBL is an input or an output. Which output pins are used to setwhich modes depends on which Hardware mode is being used.
DFC1DFC0S/AES
000111
001011
01--01
Hardware Mode Number
1 - Default Data Flow, AES3 input2 - Default Data Flow, serial input3 - Transceive Flow, with SRC4 - Transceive Flow, no SRC5 - AES3 Rx only, AES3 input6 - AES3 Tx only, serial input
Table 5. Hardware Mode Definitions
13.1.2Serial Audio Port Formats
In Hardware mode, only a limited number of alternative serial audio port formats are available. These for-mats are described by Tables 6 and 7, which define the equivalent Software mode bit settings for eachformat. Timing diagrams are shown in Figures 17 and 18.
For each Hardware mode, the following pages contain a data flow diagram, a pin-out drawing, a pin de-scriptions list and a definition of the available start-up options.
SOSF00000
SORES1/0
000000
1011
SOJUST
001
00
SODEL01010
SOSPOL
100
01
SOLRPOL
010
10
OF1 - Left-JustifiedOF2 - I²S 24-bit data
OF3 - Right-Justified, Master mode only
OF4 - I²S 16-bit dataOF5 - Direct AES3 data
Table 6. Serial Audio Output Formats Available in Hardware Mode
IF1 - Left-JustifiedIF2 - I²S
IF3 - Right-Justified 24-bit dataIF4 - Right-Justified 16-bit data
SISF0000SIRES1/0
00000010SIJUST0011SIDEL0100SISPOL
1000SILRPOL
0100
Table 7. Serial Audio Input Formats Available in Hardware Mode
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CS8420
13.2
Hardware Mode 1 Description (DEFAULT Data Flow, AES3 Input)
Hardware Mode 1 data flow is shown in Figure24. Audio data is input via the AES3 receiver, and rate con-verted. The audio data at the new rate is then output both via the serial audio output port and via the AES3transmitter.The channel status data, user data and validity bit information are handled in four alternative modes: 1A and1B, determined by a start-up resistor on the COPY pin. In mode 1A, the received PRO, COPY, ORIG, EM-PH, and AUDIO channel status bits are output on pins. The transmitted channel status bits are copied fromthe received channel status data, and the transmitted U and V bits are 0.
In mode 1B, only the COPY and ORIG pins are output, and reflect the received channel status data. Thetransmitted channel status bits, user data and validity bits are input serially via the PRO/C, EMPH/U andAUDIO/V pins. Figure20 shows the timing requirements.
Start-up options are shown in Table8, and allow choice of the serial audio output port as a master or slave,choice of four serial audio output port formats, and the source for transmitted C, U and V data. The followingpages contain the detailed pin descriptions for Hardware mode 1.
If a validity, parity, bi-phase, or lock receiver error occurs, the current audio sample will be held.
VD+OutputClockSourceOMCKDFC0DFC1S/AESH/SClockedbyOutputClockClockedbyInputDerivedClockRXPRXNAES3Rx&DecoderSampleRateConverterSerialAudioOutputAES3Encoder&TxOLRCKOSCLKSDOUTTXPTXNTCBLDC&UbitDataBufferRMCKRERRMUTEPRO/CCOPYORIGEMPH/UAUDIO/VTCBLPowersupplypins(VD+,VA+,DGND,AGND),theresetpin(RST)andthePLLfilterpin(FILT)areomittedfromthisdiagram.PleaserefertotheTypicalConnectionDiagramforhook-updetails.Figure 24. Hardware Mode 1 - Default Data Flow, AES3 Input
SDOUT
LOHI------
RMCK
----LOLOHIHI
RERR
----LOHILOHI
COPY
--LOHI
Function
Serial Output Port is SlaveSerial Output Port is Master
Mode1A: C transmitted data is copied from received data, U & V = 0, received PRO, EMPH, AUDIO are visible.
Mode 1B: CUV transmitted data is input serially on pins, received PRO, EMPH, AUDIO are not visibleSerial Output Format OF1Serial Output Format OF2Serial Output Format OF3Serial Output Format OF4
Table 8. Hardware Mode 1 Start-Up Options
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CS8420
13.2.1Pin Description - Hardware Mode 1
Overall Device Control:DFC0, DFC1 - Data Flow Control Inputs
DFC0 and DFC1 inputs determine the major data flow options available in Hardware mode, as shown in Table 5.S/AES - Serial Audio or AES3 Input Select
S/AES is connected to ground in Hardware mode 1 in order to select the AES3 input.MUTE - Mute Output Data Input
If MUTE is low, audio data is passed normally. If MUTE is high, both the AES3 transmitted audio data and the serialaudio output port data is set to digital zero.OMCK - Output Section Master Clock Input
Output section master clock input. The frequency must be 256x the output sample rate (Fso).
AES3/SPDIF Receiver Interface:RXP, RXN - Differential Line Receiver Inputs
Differential line receiver inputs, carrying AES3 type data.RMCK - Input Section Recovered Master Clock Output
Input section recovered master clock output. Will be at a frequency of 256x the input sample rate (Fsi). This is alsoa start-up option pin and requires a pull-up or pull-down resistor.
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CS8420
RERR - Receiver Error Indicator
When high, indicates a problem with the operation of the AES3 receiver. The status of this pin is updated once persub-frame of incoming AES3 data. Conditions that cause RERR to go high are: parity error, and bi-phase codingerror, as well as loss of lock in the PLL. This is also a start-up option pin, and requires a pull-up or pull-down resistor.EMPH/U - Pre-Emphasis Indicator Output or U-Bit Data Input
The EMPH/U pin reflects either the state of the EMPH channel status bits in the incoming AES3 type data stream,or is the serial U-bit input for the AES3 type transmitted data, clocked by OLRCK. When indicating emphasis,EMPH/U is low if the incoming data indicates 50/15 μs pre-emphasis and high otherwise.COPY - Copy Channel Status Bit Output
The COPY pin reflects the state of the COPY Channel Status bit in the incoming AES3 type data stream. This isalso a start-up option pin, and requires a pull-up or pull-down resistor.ORIG - Original Channel Status Output
SCMS generation indicator. This is decoded from the incoming category code and the L bit. A low output indicatesthat the audio data stream is 1st generation or higher. A high indicates that the audio data stream is original.PRO/C - Professional Channel Status Bit Output or C-Bit Data Input
The PRO/C pin either reflects the state of the Professional/Consumer Channel Status bit in the incoming AES3 typedata stream, or is the serial C-bit input for the AES3 type transmitted data, clocked by OLRCK.AUDIO/V - Audio Channel Status Bit Output or V-Bit Data Input
The AUDIO/V pin either reflects the state of the audio/non audio Channel Status bit in the incoming AES3 type datastream, or is the V-bit data input for the AES3 type transmitted data stream, clocked by OLRCK.
Audio Output Interface:SDOUT - Serial Audio Output Port Data Output
Audio data serial output pin. This is also a start-up option pin, and requires a pull-up or pull-down resistor.OSCLK - Serial Audio Output Port Bit Clock Input or OutputSerial bit clock for audio data on the SDOUT pin.
OLRCK - Serial Audio Output Port Left/Right Clock Input or Output
Word rate clock for the audio data on the SDOUT pin. The frequency will be at the output sample rate (Fso)
AES3/SPDIF Transmitter Interface:TCBL - Transmit Channel Status Block Start
When operated as output, TCBL is high during the first sub-frame of a transmitted channel status block, and low atall other times. When operated as input, driving TCBL high for at least three OMCK clocks will cause the currenttransmitted sub-frame to be the start of a channel status block.TCBLD - Transmit Channel Status Block Direction Input
Connect TCBLD to VD+ to set TCBL as an output. Connect TCBLD to DGND to set TCBL as an input.TXN, TXP - Differential Line Driver Outputs
Differential line driver outputs, transmitting AES3 type data. Drivers are pulled to low while the CS8420 is in the resetstate.58
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CS8420
13.3
Hardware Mode 2 Description
(DEFAULT Data Flow, Serial Input)
Hardware Mode 2 data flow is shown in Figure25. Audio data is input via the serial audio input port, andrate converted. The audio data at the new rate is then output both via the serial audio output port and viathe AES3 transmitter.
The C, U, and V bits in the AES3 output stream may be set in two methods, selected by the CUVENpin.When CUVEN is low, mode 2A is selected, where COPY/C, ORIG/U, and EMPH/Vpins allow selectedchannel status data bits to be set. The COPY and ORIG pins are used to set the pro bit, the copy bit, andthe L bit, as shown in Table9. In consumer mode, the transmitted category code shall be 0101100b, whichindicates sample rate converter. The transmitted U and V bits are zero.When the CUVEN pin is high, mode2B is selected, where COPY/C, ORIG/U, and EMPH/V become serial bit inputs for C, U, and V data. Thisdata is clocked by both edges of OLRCK, and the channel status block start is indicated or determined byTCBL. Figure 20 shows the timing requirements.
Audio serial port data formats are selected as shown in Tables 6, 7 and 10.
Start-up options are shown in Table11, and allow choice of the serial audio output port as a master or slaveand whether TCBL is an input or an output. The serial audio input port is always a slave.
VD+VD+OutputClockSourceOMCKDFC0DFC1S/AESH/SClockedbyOutputClockClockedbyInputDerivedClockILRCKISCLKSDINSerialAudioInputSampleRateConverterSerialAudioOutputAES3Encoder&TxOLRCKOSCLKSDOUTTXPTXNC&UbitDataBufferRMCKLOCKSFMT1SFMT0COPY/CORIG/UEMPH/VCUVENTCBLPowersupplypins(VD+,VA+,DGND,AGND)&theresetpin(RST)andthePLLfilterpin(FILT)areomittedfromthisdiagram.PleaserefertotheTypicalConnectionDiagramforhook-updetails.Figure 25. Hardware Mode 2 - Default Data Flow, Serial Audio Input
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CS8420
COPY/C
0011
ORIG/U
0101Function
PRO=0, COPY=0, L=0PRO=0, COPY=0, L=1PRO=0, COPY=1, L=0PRO=1
Table 9. HW Mode 2A COPY/C and ORIG/U Pin Function
SFMT1
0011
SFMT0
0101Function
Serial Input & Output Format IF1&OF1Serial Input & Output Format IF2&OF2Serial Input & Output Format IF3&OF3Serial Input & Output Format IF4&OF3
Table 10. HW Mode 2 Serial Audio Port Format Selection
SDOUT
LOHI--LOCK--LOHIFunction
Serial Output Port is SlaveSerial Output Port is MasterTCBL is an inputTCBL is an output
Table 11. Hardware Mode 2 Start-Up Options
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CS8420
13.3.1Pin Description - Hardware Mode 2
Overall Device Control:DFC0, DFC1 - Data Flow Control Inputs
DFC0 and DFC1 inputs determine the major data flow options available in Hardware mode, according to Table 5.S/AES - Serial Audio or AES3 Input Select
S/AES is connected to VD+ in Hardware mode 2, in order to select the serial audio input.SFMT0, SFMT1 - Serial Audio Port Data Format Select Inputs
SFMT0 and SFMT1 select the serial audio input and output ports’ format. See Table10.OMCK - Output Section Master Clock Input
Output section master clock input. The frequency must be 256x the output sample rate (Fso).
Audio Input Interface:SDIN - Serial Audio Input Port Data InputAudio data serial input pin.
ISCLK - Serial Audio Input Port Bit Clock Input or OutputSerial bit clock for audio data on the SDIN pin.
ILRCK - Serial Audio Input Port Left/Right Clock Input or Output
Word rate clock for the audio data on the SDIN pin. The frequency will be at the input sample rate (Fsi)
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CS8420
RMCK - Input Section Recovered Master Clock Output
Input section recovered master clock output. Will be at a frequency of 256x the input sample rate (Fsi).LOCK - PLL Lock Indicator Output
LOCK low indicates that the PLL is locked. This is also a start-up option pin, and requires a pull-up or pull-downresistor.
Audio Output Interface:SDOUT - Serial Audio Output Port Data Output
Audio data serial output pin. This is also a start-up option pin, and requires a pull-up or pull-down resistor.OSCLK - Serial Audio Output Port Bit Clock Input or OutputSerial bit clock for audio data on the SDOUT pin.
OLRCK - Serial Audio Output Port Left/Right Clock Input or Output
Word rate clock for the audio data on the SDOUT pin. The frequency will be at the output sample rate (Fso).
AES3/SPDIF Transmitter Interface:TXN, TXP - Differential Line Driver Outputs
Differential line driver outputs, transmitting AES3 type data. Drivers are pulled to low while the CS8420 is in the resetstate.
TCBL - Transmit Channel Status Block Start
When operated as output, TCBL is high during the first sub-frame of a transmitted channel status block, and low atall other times. When operated as input, driving TCBL high for at least three OMCK clocks will cause the currenttransmitted sub-frame to be the start of a channel status block.CUVEN - C, U and V bit Input Enable Mode Input
The CUVEN pin determines how the channel status data, user data and validity bit is input. When CUVEN is low,Hardware mode 2A is selected, where the EMPH/V, COPY/C and ORIG/U pins are used to enter selected channelstatus data. When CUVEN is high, hardware 2B is selected, where the EMPH/V, COPY/C and ORIG/U pins areused to enter serial C, U and V data.
EMPH/V - Pre-Emphasis Indicator Input or V Bit Input
In mode 2A, EMPH/V low sets the 3 EMPH channel status bits to indicate 50/15 μs pre-emphasis. EMPH/V highsets the 3 EMPH bits to 000 indicating no pre-emphasis. In mode 2B, EMPH/V low sets the V bit to indicate validaudio. EMPH/V high sets the V-bit to indicate non-valid audio.COPY/C - COPY Channel Status Bit Input or C Bit Input
In mode 2A, the COPY/C pin determines the state of the COPY, PRO and L Channel Status bits in the outgoingAES3 type data stream (See Table9). In mode 2B, COPY/C becomes the direct C bit input data pin.ORIG/U - ORIG Channel Status Bit Input or U Bit Input
In mode 2A, the ORIG/U pin determines the state of the COPY, PRO and L Channel Status bits in the outgoing AES3type data stream. (See Table9). In mode 2B, ORIG/U becomes the direct U bit input data pin.
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CS8420
13.4
Hardware Mode 3 Description
(Transceive Data Flow, with SRC)
Hardware Mode 3 data flow is shown in Figure26. Audio data is input via the AES3 receiver, and rate con-verted. The audio data at the new rate is then output via the serial audio output port. Different audio data,synchronous to OMCK, may be input into the serial audio input port, and output via the AES3 transmitter. The channel status data, user data, and validity bit information are handled in two alternative modes: 3Aand 3B, determined by a start-up resistor on the COPY pin. In mode 3A, the received PRO, COPY, ORIG,and AUDIO channel status bits are output on pins. The transmitted channel status bits are copied from thereceived channel status data, and the transmitted U and V bits are zero.
In mode 3B, only the COPY, and ORIG pins are output, and reflect the received channel status data. Thetransmitted channel status bits, user data, and validity bits are input serially via the PRO/C, EMPH/U, andAUDIO/V pins. Figure20 shows the timing requirements.The serial audio input port is always a slave.
If a validity, parity, bi-phase, or lock receiver error occurs, the current audio sample will be held.
Start-up options are shown in Table12, and allow choice of the serial audio output port as a master or slave,whether TCBL is an input or an output, the serial audio ports formats, and the source of the transmitted C,U, and V data. The following pages contain the detailed pin descriptions for Hardware mode 3.
VD+VD+OSCLKISCLKSDOUTOLRCKILRCKSDINOutputClockSourceOMCKDFC0DFC1H/SClockedbyInputDerivedClockClockedbyOutputClockSerialAudioOutputSerialAudioInputAES3Encoder&TxTXPTXNRXPRXNAES3Rx&DecoderSampleRateConverterC&UbitDataBufferRMCKRERRPRO/CCOPYORIGEMPH/UAUDIO/VTCBLPowersupplypins(VD+,VA+,DGND,AGND)&theresetpin(RST)andthePLLfilterpin(FILT)areomittedfromthisdiagram.PleaserefertotheTypicalConnectionDiagramforhook-updetails.Figure 26. Hardware Mode 3 - Transceive Data Flow, with SRC
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CS8420
SDOUTRMCKRERRORIGCOPYFunctionLO----Serial Output Port is SlaveHI----Serial Output Port is Master----LOMode 3A: C transmitted data is copied from received data, U & V =0,
received PRO, EMPH, AUDIO is visible
----HIMode 3B: CUV transmitted data is input serially on pins, received PRO,
EMPH and AUDIO is not visible
-LOLO--Serial Input & Output Format IF1&OF1
-LOHI--Serial Input & Output Format IF2&OF2
-HILO--Serial Input & Output Format IF3&OF3
-HIHI--Serial Input & Output Format IF2&OF4
---LO-TCBL is an input
---HI-TCBL is an output
Table 12. Hardware Mode 3 Start-Up Options
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CS8420
13.4.1Pin Description - Hardware Mode 3
Overall Device Control:DFC0, DFC1 - Data Flow Control Inputs
DFC0 and DFC1 inputs determine the major data flow options available in Hardware mode, according to Table5.OMCK - Output Section Master Clock Input
Output section master clock input. The frequency must be 256x the output sample rate (Fso).
Audio Input Interface:SDIN - Serial Audio Input Port Data Input
Audio data serial input pin. This data will be transmitted out the AES3 port.ISCLK - Serial Audio Input Port Bit Clock InputSerial bit clock for audio data on the SDIN pin.
ILRCK - Serial Audio Input Port Left/Right Clock Input
Word rate clock for the audio data on the SDIN pin. The frequency will be at the output sample rate (Fso)
Audio Output Interface:SDOUT - Serial Audio Output Port Data Output
Audio data serial output pin. This is also a start-up option pin, and requires a pull-up or pull-down resistor.OSCLK - Serial Audio Output Port Bit Clock Input or OutputSerial bit clock for audio data on the SDOUT pin.
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CS8420
OLRCK - Serial Audio Output Port Left/Right Clock Input or Output
Word rate clock for the audio data on the SDOUT pin. The frequency will be at the output sample rate (Fso).
AES3/SPDIF Transmitter Interface:TXN, TXP - Differential Line Driver Outputs
Differential line driver outputs, transmitting AES3 type data. Drivers are pulled to low while the CS8420 is in the resetstate.
TCBL - Transmit Channel Status Block Start
When operated as output, TCBL is high during the first sub-frame of a transmitted channel status block, and low atall other times. When operated as input, driving TCBL high for at least three OMCK clocks will cause the currenttransmitted sub-frame to be the start of a channel status block.
AES3/SPDIF Receiver Interface:RXP, RXN - Differential Line Receiver Inputs
Differential line receiver inputs, carrying AES3 type data.RMCK - Input Section Recovered Master Clock Output
Input section recovered master clock output. Will be at a frequency of 256x the input sample rate (Fsi). This is alsoa start-up option pin, and requires a pull-up or pull-down resistor.RERR - Receiver Error Indicator Output
When high, indicates a problem with the operation of the AES3 receiver. The status of this pin is updated once persub-frame of incoming AES3 data. Conditions that cause RERR to go high are: parity error, and bi-phase codingerror, as well as loss of lock in the PLL. This is also a start-up option pin, and requires a pull-up or pull-down resistor.EMPH/U - Pre-emphasis Indicator Output or U-Bit Data Input
The EMPH/U pin either reflects the state of the EMPH channel status bits in the incoming AES3 type data stream,or is the serial U-bit input for the AES3 type transmitted data, clocked by OLRCK. If indicating emphasis EMPH/Uis low when the incoming data indicates 50/15 μs pre-emphasis and high otherwise.COPY - Copy Channel Status Bit Output
The COPY pin reflects the state of the COPY Channel Status bit in the incoming AES3 type data stream. This isalso a start-up option pin, and requires a pull-up or pull-down resistor.ORIG - Original Channel Status Output
SCMS generation indicator. This is decoded from the incoming category code and the L bit. A low output indicatesthat the audio data stream is 1st generation or higher. A high indicates that the audio data stream is original. This isalso a start-up option pin, and requires a pull-up or pull-down resistor.PRO/C - Professional Channel Status Bit Output or C-Bit Data Input
The PRO/C pin either reflects the state of the Professional/Consumer Channel Status bit in the incoming AES3 typedata stream, or is the serial C-bit input for the AES3 type transmitted data, clocked by OLRCK.AUDIO/V - Audio Channel Status Bit Output or V-Bit Data Input
The AUDIO/V pin either reflects the state of the audio/non audio Channel Status bit in the incoming AES3 type datastream, or is the V-bit data input for the AES3 type transmitted data stream, clocked by OLRCK.
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CS8420
13.5
Hardware Mode 4 Description
(Transceive Data Flow, No SRC)
Hardware mode 4 data flow is shown in Figure27. Audio data is input via the AES3 receiver, and routed tothe serial audio output port. Different audio data synchronous to RMCK may be input into the serial audioinput port, and output via the AES3 transmitter.
The channel status data, user data, and validity bit information are handled in two alternative modes: 4Aand 4B, determined by a start-up resistor on the COPY pin. In mode 4A, the received PRO, COPY, ORIG,EMPH, and AUDIOchannel status bits are output on pins. The transmitted channel status bits are copiedfrom the received channel status data, and the transmitted U and V bits are 0.
In mode 4B, only the COPY and ORIG pins are output, and reflect the received channel status data. Thetransmitted channel status bits, user data, and validity bits are input serially via the PRO/C, EMPH/U, andAUDIO/V pins. Figure20 shows the timing requirements.
The APMS pin allows the serial audio input port to be set to master or slave.
If a validity, parity, bi-phase, or lock receiver error occurs, the current audio sample is passed unmodifiedto the serial audio output port.
Start-up options are shown in Table13, and allow choice of the serial audio output port as a master or slave,whether TCBL is an input or an output, the audio serial ports formats, and the source of the transmitted C,U, and V data.
The following pages contain the detailed pin descriptions for Hardware mode 4.
VD+VD+OSCLKISCLKSDOUTOLRCKILRCKSDINDFC0DFC1H/SSerialAudioOutputRXPRXNAES3Rx&DecoderSerialAudioInputAES3Encoder&TxAPMSTXPTXNC&UbitDataBufferRMCKRERRPRO/CCOPYORIGEMPH/UAUDIO/VTCBLPowersupplypins(VD+,VA+,DGND,AGND)&theresetpin(RST)andthePLLfilterpin(FILT)areomittedfromthisdiagram.PleaserefertotheTypicalConnectionDiagramforhook-updetails.Figure 27. Hardware Mode 4 - Transceive Data Flow, Without SRC
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CS8420
SDOUTRMCKRERRORIGCOPYFunctionLO----Serial Output Port is SlaveHI----Serial Output Port is Master----LOMode 4A: C transmitted data is copied from received data, U & V =0,
received PRO, EMPH, AUDIO is visible
----HIMode 4B: CUV transmitted data is input serially on pins, received PRO,
EMPH and AUDIO is not visible
-LOLO--Serial Input & Output Format IF1&OF1
-LOHI--Serial Input & Output Format IF2&OF2
-HILO--Serial Input & Output Format IF3&OF3
-HIHI--Serial Input & Output Format IF1&OF5
---LO-TCBL is an input
---HI-TCBL is an output
Table 13. Hardware Mode 4 Start-Up Options
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CS8420
13.5.1Pin Description - Hardware Mode 4
Overall Device Control:DFC0, DFC1 - Data Flow Control Inputs
DFC0 and DFC1 inputs determine the major data flow options available in Hardware mode, according to Table5.
Audio Input Interface:SDIN - Serial Audio Input Port Data Input
Audio data serial input pin. This data will be transmitted out the AES3 port.ISCLK - Serial Audio Input Port Bit Clock Input or OutputSerial bit clock for audio data on the SDIN pin.
ILRCK - Serial Audio Input Port Left/Right Clock Input or Output
Word rate clock for the audio data on the SDIN pin. The frequency will be at the input sample rate (Fsi)APMS - Serial Audio Input Port Master or Slave
APMS should be connected to VD+ to set serial audio input port as a master, or connected to DGND to set the portas a slave.
Audio Output Interface:SDOUT - Serial Audio Output Port Data Output
Audio data serial output pin. This is also a start-up option pin, and requires a pull-up or pull-down resistor.
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CS8420
OSCLK - Serial Audio Output Port Bit Clock Input or OutputSerial bit clock for audio data on the SDOUT pin.
OLRCK - Serial Audio Output Port Left/Right Clock Input or Output
Word rate clock for the audio data on the SDOUT pin. The frequency will be at the input sample rate (Fsi).
AES3/SPDIF Transmitter Interface:TXN, TXP - Differential Line Driver Outputs
Differential line driver outputs, transmitting AES3 type data. Drivers are pulled to low while the CS8420 is in the resetstate.
TCBL - Transmit Channel Status Block Start
When operated as output, TCBL is high during the first sub-frame of a transmitted channel status block, and low atall other times. When operated as input, driving TCBL high for at least three RMCK clocks will cause the currenttransmitted sub-frame to be the start of a channel status block.
AES3/SPDIF Receiver Interface:RXP, RXN - Differential Line Receiver Inputs
Differential line receiver inputs, carrying AES3 type data.RMCK - Input Section Recovered Master Clock Output
Input section recovered master clock output. Will be at a frequency of 256x the input sample rate (Fsi). This is alsoa start-up option pin, and requires a pull-up or pull-down resistor.RERR - Receiver Error Indicator Output
When high, indicates a problem with the operation of the AES3 receiver. The status of this pin is updated once persub-frame of incoming AES3 data. Conditions that cause RERR to go high are: parity error, and bi-phase codingerror, as well as loss of lock in the PLL. This is also a start-up option pin, and requires a pull-up or pull-down resistor.EMPH/U - Pre-emphasis Indicator Output or U-Bit Data Input
The EMPH/U pin either reflects the state of the EMPH channel status bit in the incoming AES3 type data stream, oris the serial U-bit input for the AES3 type transmitted data, clocked by OLRCK. If indicating emphasis EMPH/U ishigh when the incoming data indicates 50/15μs pre-emphasis and low otherwise.COPY - Copy Channel Status Bit Output
The COPY pin reflects the state of the COPY Channel Status bit in the incoming AES3 type data stream. This isalso a start-up option pin, and requires a pull-up or pull-down resistor.ORIG - Original Channel Status Output
SCMS generation indicator. This is decoded from the incoming category code and the L bit. A low output indicatesthat the audio data stream is 1st generation or higher. A high indicates that the audio data stream is original. This isalso a start-up option pin, and requires a pull-up or pull-down resistor.PRO/C - Professional Channel Status Bit Output or C-Bit Data Input
The PRO/C pin either reflects the state of the Professional/Consumer Channel Status bit in the incoming AES3 typedata stream, or is the serial C-bit input for the AES3 type transmitted data, clocked by OLRCK.AUDIO/V - Audio Channel Status Bit Output or V-Bit Data Input
The AUDIO/V pin either reflects the state of the audio/non audio Channel Status bit in the incoming AES3 type datastream, or is the V-bit data input for the AES3 type transmitted data stream, clocked by OLRCK.70
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CS8420
13.6
Hardware Mode 5 Description
(AES3 Receiver Only)
Hardware Mode 5 data flow is shown in Figure28. Audio data is input via the AES3 receiver, and routed tothe serial audio output port. The PRO, COPY, ORIG, EMPH, and AUDIO channel status bits are output onpins. The decoded C and U bits are also output, clocked by both edges of OLRCK (Master mode only, seeFigure19).
If a validity, parity, bi-phase, or lock receiver error occurs, the current audio sample is passed unmodifiedto the serial audio output port.
Start-up options are shown in Table14, and allow choice of the serial audio output port as a master or slave,and the serial audio port format. The following pages contain the detailed pin descriptions for Hardwaremode 5.
VD+VD+VD+DFC0DFC1S/AESH/SOMCKRXPRXNAES3Rx&DecoderSerialAudioOutputOLRCKOSCLKSDOUTC&UbitDataBufferCURMCKRERRNVERRCHSCOPYORIGEMPHPROAUDIORCBLPowersupplypins(VD+,VA+,DGND,AGND)&theresetpin(RST)andthePLLfilterpin(FILT)areomittedfromthisdiagram.PleaserefertotheTypicalConnectionDiagramforhook-updetails.Figure 28. Hardware Mode 5 - AES3 Receiver Only
SDOUT
LOHI----
ORIG
--LOLOHIHI
EMPH
--LOHILOHI
Function
Serial Output Port is SlaveSerial Output Port is MasterSerial Output Format OF1Serial Output Format OF2Serial Output Format OF3Serial Output Format OF5
Table 14. Hardware Mode 5 Start-Up Options
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CS8420
13.6.1Pin Description - Hardware Mode 5
Overall Device Control:DFC0, DFC1 - Data Flow Control Inputs
DFC0 and DFC1 inputs determine the major data flow options available in Hardware mode, according to Table5.S/AES - Serial Audio or AES3 Input Select
S/AES is connected to DGND in Hardware mode 5, in order to select the AES3 input.OMCK - Output Section Master Clock Input
Output section master clock input. This pin is not used in this mode and should be connected to DGND.
Audio Output Interface:SDOUT - Serial Audio Output Port Data Output
Audio data serial output pin. This is also a start-up option pin, and requires a pull-up or pull-down resistor.OSCLK - Serial Audio Output Port Bit Clock Input or OutputSerial bit clock for audio data on the SDOUT pin.
OLRCK - Serial Audio Output Port Left/Right Clock Input or Output
Word rate clock for the audio data on the SDOUT pin. The frequency will be at the input sample rate (Fsi).
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CS8420
AES3/SPDIF Receiver Interface:RXP, RXN - Differential Line Receiver Inputs
Differential line receiver inputs, carrying AES3 type data.RMCK - Input Section Recovered Master Clock Output
Input section recovered master clock output. Will be at a frequency of 256x the input sample rate (Fsi).RERR - Receiver Error Indicator
When high, indicates a problem with the operation of the AES3 receiver. The status of this pin is updated once persub-frame of incoming AES3 data. Conditions that cause RERR to go high are: validity, parity error, and bi-phasecoding error, as well as loss of lock in the PLL.NVERR - No Validity Receiver Error Indicator
When high, indicates a problem with the operation of the AES3 receiver. The status of this pin is updated once perframe of incoming AES3 data. Conditions that cause NVERR to go high are: parity error, and bi-phase coding error,as well as loss of lock in the PLL.EMPH - Pre-emphasis Indicator Output
EMPH is low when the incoming AES3 data indicates the presence of 50/15μs pre-emphasis. When the AES3 dataindicates the absence of pre-emphasis or the presence of non 50/15μs pre-emphasis EMPH is high. This is also astart-up option pin, and requires a pull-up or pull-down resistor.COPY - Copy Channel Status Bit Output
The COPY pin reflects the state of the COPY Channel Status bit in the incoming AES3 type data stream.ORIG - Original Channel Status Output
SCMS generation indicator. This is decoded from the incoming category code and the L bit. A low output indicatesthat the audio data stream is 1st generation or higher. A high indicates that the audio data stream is original. This isalso a start-up option pin, and requires a pull-up or pull-down resistor.PRO - Professional Channel Status Bit Output
The PRO pin reflects the state of the Professional/Consumer Channel Status bit in the incoming AES3 type datastream.
AUDIO - Audio Channel Status Bit Output
The AUDIO pin reflects the state of the audio/non audio Channel Status bit in the incoming AES3 type data stream.RCBL - Receiver Channel Status Block Output
RCBL indicates the beginning of a received channel status block. RCBL goes high 2 frames after the reception of aZ preamble, remains high for 16 frames while COPY, ORIG, AUDIO, EMPH and PRO are updated, and returns lowfor the remainder of the block. RCBL changes on rising edges of RMCK.CHS - Channel Select Input
Selects which sub-frame’s channel status data is output on the EMPH, COPY, ORIG, PRO and AUDIO pins. Chan-nel A is selected when CHS is low, channel B is selected when CHS is high.U - User Data Output
The U pin outputs user data from the AES3 receiver, clocked by rising and falling edges of OLRCK. C - Channel Status Data Output
The C pin outputs channel status data from the AES3 receiver, clocked by rising and falling edges of OLRCK. DS245F4
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CS8420
13.7
Hardware Mode 6 Description
(AES3 Transmitter Only)
Hardware Mode 6 data flow is shown in Figure29. Audio data is input via the serial audio input port androuted to the AES3 transmitter.
The transmitted channel status, user, and validity data may be input in two alternative methods, determinedby the state of the CEN pin. Mode 6A is selected when the CEN pin is low. In mode 6A, the user data andvalidity bit are input via the U and V pins, clocked by both edges of ILRCK. The channel status data is de-rived from the state of the COPY/C, ORIG, EMPH, and AUDIO pins. Table15 shows how the COPY/C andORIG pins map to channel status bits. In consumer mode, the transmitted category code shall be set toSample Rate Converter (0101100b).
Mode 6B is selected when the CEN pin is high. In mode 6B, the channel status, user data and validity bitare input serially via the COPY/C, U, and V pins. These pins are clocked by both edges of ILRCK (if the portis in Master mode). Figure20 shows the timing requirements.
The channel status block pin (TCBL) may be an input or an output, determined by the state of the TCBLDpin. The serial audio input port data format is selected as shown in Table15, and may be set to master orslave by the state of the APMS input pin.
The following pages contain detailed pin descriptions for Hardware mode 6.
VD+VD+VD+VD+OutputClockSourceFILTOMCKDFC0DFC1S/AESH/SILRCKISCLKSDINSerialAudioInputAES3Encoder&TxTXPTXNC,U,VDataBufferCENUVAPMSSFMT1SFMT0COPY/CORIGEMPHAUDIOTCBLTCBLDPowersupplypins(VD+,VA+,DGND,AGND)&theresetpin(RST)areomittedfromthisdiagram.PleaserefertotheTypicalConnectionDiagramforhook-updetails.Figure 29. Hardware Mode 6 - AES3 Transmitter Only
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CS8420
COPY/C
0011
ORIG
0101Function
PRO=0, COPY=0, L=0PRO=0, COPY=0, L=1PRO=0, COPY=1, L=0PRO=1
Table 15. HW 6 COPY/C and ORIG Pin Function
SFMT1
0011
SFMT0
0101Function
Serial Input Format IF1Serial Input Format IF2Serial Input Format IF3Serial Input Format IF4
Table 16. HW 6 Serial Port Format Selection
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13.7.1Pin Description - Hardware Mode 6
COPY/CDFC0EMPHSFMT0SFMT1VA+AGNDFILTRSTAPMSTCBLDILRCKISCLKSDIN123456*7*8*9*101112131428272625*24*23*2221201918171615ORIGDFC1TXPTXNH/SVD+DGNDOMCKS/AESAUDIOUVCENTCBL*Pinswhichremainthesamefunctioninallmodes.Overall Device Control:DFC0, DFC1 - Data Flow Control Inputs
DFC0 and DFC1 inputs determine the major data flow options available in Hardware mode, according to Table5.S/AES - Serial Audio or AES3 Input Select
S/AES is connected to VD+ in Hardware mode 6, in order to select the serial audio input.SFMT0, SFMT1 - Serial Audio Input Port Data Format Select InputsSFMT0 and SFMT1 select the serial audio input port format. See Table15.OMCK - Output Section Master Clock Input
Output section master clock input. The frequency must be 256x the output sample rate (Fso).
Audio Input Interface:SDIN - Serial Audio Input PortData Input Audio data serial input pin.ISCLK - Serial Audio Input Port Bit Clock
Input or Output Serial bit clock for audio data on the SDIN pin.
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CS8420
ILRCK - Serial Audio Input Port Left/Right Clock
Input or Output Word rate clock for the audio data on the SDIN pin. APMS - Serial Audio Input Port Master or Slave.
APMS should be connected to VD+ to set serial audio input port as a master, or connected to DGND to set the port as a slave.
AES3/SPDIF Transmitter Interface:TXN, TXP - Differential Line Driver Outputs
Differential line driver outputs, transmitting AES3 type data. Drivers are pulled to low while the CS8420 is in the resetstate.
TCBL - Transmit Channel Status Block Start
When operated as output, TCBL is high during the first sub-frame of a transmitted channel status block, and low atall other times. When operated as input, driving TCBL high for at least three OMCK clocks will cause the currenttransmitted sub-frame to be the start of a channel status block.TCBLD - Transmit Channel Status Block Direction Input
Connect TCBLD to VD+ to set TCBL as an output. Connect TCBLD to DGND to set TCBL as an input.EMPH - Pre-Emphasis Indicator Input
In mode 6B, EMPH pin low sets the 3 EMPH channel status bits to indicate 50/15μs pre-emphasis. If EMPH is highthe 3 EMPH channel status bits are set to 000 indicating no pre-emphasis.COPY/C - COPY Channel Status Bit Input or C Bit Input
In mode 6B, the COPY/C pin determines the state of the COPY, PRO and L Channel Status bits in the outgoingAES3 type data stream (See Table15). In mode 6A, the COPY/C pin becomes the direct C bit input data pin.ORIG - ORIG Channel Status Bit Input
In mode 6B, the ORIG pin determines the state of the COPY, PRO and L Channel Status bits in the outgoing AES3type data stream. See Table15.
AUDIO - Audio Channel Status Bit Input
In mode 6B, the AUDIO pin determines the state of the audio/non audio Channel Status bit in the outgoing AES3type data stream. V - Validity Bit Input
In modes 6A and 6B, the V pin input determines the state of the validity bit in the outgoing AES3 transmitted data.This pin is sampled on both edges of the ILRCK.U - User Data Bit Input
In modes 6A and 6B, the U pin input determines the state of the user data bit in the outgoing AES3 transmitted data.This pin is sampled on both edges of the ILRCK.CEN - C Bit Input Enable Mode Input
The CEN pin determines how the channel status data bits are input. When CEN is low, Hardware mode 6A is se-lected, where the COPY/C, ORIG, EMPH and AUDIO pins are used to enter selected channel status data. WhenCEN is high, Hardware mode 6B is selected, where the COPY/C pin is used to enter serial channel status data.DS245F4
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14.EXTERNAL AES3/SPDIF/IEC60958 TRANSMITTER AND RECEIVER
COMPONENTS
This section details the external components required to interface the AES3 transmitter and receiver to cables andfiber-optic components.
14.1AES3 Transmitter External Components
The output drivers on the CS8420 are designed to drive both the professional and consumer interfaces. TheAES3 specification for professional/broadcast use calls for a 110Ω source impedance and a balanced drivecapability. Since the transmitter output impedance is very low, a 110Ω resistor should be placed in serieswith one of the transmit pins. The specifications call for a balanced output drive of 2-7 volts peak-to-peakinto a 110Ω load with no cable attached. Using the circuit in Figure30, the output of the transformer is short-circuit protected, has the proper source impedance, and provides a 5volts peak-to-peak signal into a 110Ωload. Lastly, the two output pins should be attached to an XLR connector with male pins and a female shell,and with pin 1 of the connector grounded.
CS8420TXPXLRTXN110-(RTXP+RTXN)1Figure 30. Professional Output Circuit
In the case of consumer use, the IEC60958 specifications call for an unbalanced drive circuit with an outputimpedance of 75Ω and a output drive level of 0.5V peak-to-peak ±20% when measured across a 75Ω loadusing no cable. The circuit shown in Figure31 only uses the TXP pin and provides the proper output imped-ance and drive level using standard 1% resistors. The connector for a consumer application would be anRCA phono socket. This circuit is also short circuit protected.
CS8420TXP90.9ΩTXNRCAPhono374-RTXPFigure 31. Consumer Output Circuit
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CS8420
The TXP pin may be used to drive TTL or CMOS gates as shown in Figure32. This circuit may be used foroptical connectors for digital audio since they usually have TTL or CMOS compatible inputs. This circuit isalso useful when driving multiple digital audio outputssince RS422 line drivers have TTL compatible inputs.
CS8420TXPTTLorCMOSGateTXNFigure 32. TTL/CMOS Output Circuit
14.2AES3 Receiver External Components
The CS8420 AES3 receiver is designed to acceptboth the professional and consumer interfaces. The dig-ital audio specifications for professional use call for a balanced receiver, using XLR connectors, with 110Ω±20% impedance.The XLR connector on the receiver should have female pins with a male shell. Since thereceiver has a very high input impedance, a 110Ω resistor should be placed across the receiver terminalsto match the line impedance, as shown in Figure33. Although transformers are not required by the AES,they are, however, strongly recommended.
XLR110ΩTwistedPair1110ΩRXN*SeeTextCS8420RXPFigure 33. Professional Input Circuit
If some isolation is desired without the use of transformers, a 0.01μF capacitor should be placed in serieswith each input pin (RXP and RXN) as shown in Figure34. However, if a transformer is not used, highfrequency energy could be coupled into the receiver, causing degradation in analog performance.
XLR110ΩTwistedPair1110Ω0.01μFRXNCS8420*SeeText0.01μFRXPFigure 34. Transformerless Professional Input Circuit
Figures 33 and 34 show an optional DC blocking capacitor (0.1μF to 0.47μF) in series with the cable input.This improves the robustness of the receiver, preventing the saturation of the transformer, or any DC currentflow, if a DC voltage is present on the cable.
In the configuration of systems, it is important to avoid ground loops and DC current flowing down the shieldof the cable that could result when boxes with different ground potentials are connected. Generally, it isgood practice to ground the shield to the chassis of the transmitting unit, and connect the shield through acapacitor to chassis ground at the receiver. However, in some cases it is advantageous to have the groundof two boxes held to the same potential, and the cable shield might be depended upon to make that electrical
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CS8420
connection. Generally, it may be a good idea to provide the option of grounding or capacitively coupling theshield to the chassis.
In the case of the consumer interface, the standards call for an unbalanced circuit having a receiver imped-ance of 75Ω ±5%. The connector for the consumer interface is an RCA phono socket. The receiver circuitfor the consumer interface is shown in Figure35.
RCAPhono75ΩCoax75ΩRXN0.01μF0.01μFCS8420RXPFigure 35. Consumer Input Circuit
The circuit shown in Figure36 may be used when external RS422 receivers, optical receivers or otherTTL/CMOS logic outputs drive the CS8420 receiver section.
TTL/CMOSGateCS84200.01μFRXP0.01μFRXNFigure 36. TTL/CMOS Input Circuit14.3Isolating Transformer Requirements
The transformer should be capable of operating from 1.5 to 14MHz, which is equivalent to an audio datarate of 25kHz to 108kHz after bi-phase mark encoding. Transformers provide isolation from ground loops,60Hz noise, and common mode noise and interference. One of the important considerations when choos-ing transformers is minimizing shunt capacitance between primary and secondary windings. The higher theshunt capacitance, the lower the isolation between primary and secondary, and the more coupling of highfrequencyenergy. This energy appears in the form of common mode noise on the receive side ground andhas the potential to degrade analog performance. Therefore, for best performance, shielded transformersoptimized for minimum shunt capacitance should be used. See Application Note 134 for a selection of man-ufacturers and their part numbers.
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15.CHANNEL STATUS AND USER DATA BUFFER MANAGEMENT
The CS8420 has a comprehensive channel status (C) and user (U) data buffering scheme, which allows automaticmanagement of channel status blocks and user data. Alternatively, sufficient control and access is provided to allowthe user to completely manage the C and U data via the control port.
15.1AES3 Channel Status(C) Bit Management
The CS8420 contains sufficient RAM to store a full block of C data for both A and B channels (192x2 = 384bits), and also 384 bits of U information. The user may read from or write to these RAMs via the control port. Unlike the audio data, it is not possible to 'sample-rate'convert the C bits. This is because specific meaningsare associated with fixed-length data patterns, which should not be altered. Since the output data rate of theCS8420 will differ from the input rate when sample-rate conversion is done, it is not feasible to directly trans-fer incoming C data to the output. The CS8420 manages the flow of channel status data at the block level,meaning that entire blocks of channel status information are buffered at the input, synchronized to the outputtimebase, and then transmitted. The buffering scheme involves a cascade of three block-sized buffers,named D,E, and F as shown in Figure37. The MSB of each byte represents the first bit in the serial C datastream. For example, the MSB of byte 0 (which is at control port address 20h) is the consumer/professionalbit for channel status block A.
A8-bitsFromAES3ReceiverB8-bitsDReceivedDataBufferE24wordsFTransmitDataBufferToAES3TransmitterControlPortFigure 37. Channel Status Data Buffer Structure
The first buffer, D, accepts incoming C data from the AES receiver. The 2nd buffer, E, accepts entire blocksof data from the D buffer. The E buffer is also accessible from the control port, allowing read and writing ofthe C data. The 3rd buffer (F) is used as the source of C data for the AES3 transmitter. The F buffer acceptsblock transfers from the E buffer.
If the input rate is slower than the output rate (so that in a given time interval, more channel status blocksare transmitted than received), some buffered C blocks will be transmitted multiple times. If the input rate isfaster than the output rate, some will not be transmitted at all. This is illustrated in (Figure 38). In this manner,channel status block integrity is maintained. If the transmitted sample count bits are important in the appli-cation, then they will need to be updated via the control port by the microcontroller for every outgoing block.
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15.1.1Manually Accessing the E Buffer
The user can monitor the data being transferred by reading the E buffer, which is mapped into the registerspace of the CS8420, via the control port. The user can modify the data to be transmitted by writing to theE buffer.Fso>Fsi(3/2)Causesblocks1and3tobetransmittedtwiceContentsofEbufferUpdatedatFsirateContentsofFbufferUpdatedfromEOutputatFsorateblock1block1block2block1block2block3block3block3block4block4block5block5Fso Flowcharts for reading and writing to the E buffer are shown in Figures 39 and 40. For reading, since a D-to-E interrupt just occurred, then there a substantial time interval until the next D-to-E transfer (approxi-mately 192 frames worth of time). This is usually plenty of time to access the E data without having toinhibit the next transfer. For writing, the sequence starts after a E-to-F transfer, which is based on the out-put timebase. Since a D-to-E transfer could occur at any time (this is based on the input timebase), thenit is important to inhibit D-to-E transfers while writing to the E buffer until all writes are complete. Then waituntil the next E-to-F transfer occurs before enabling D-to-E transfers. This ensures that the data writtento the E buffer actually gets transmitted and not overwritten by a D-to-E transfer. If the channel status block to transmit indicates PRO mode, then the CRCC byte is automatically calcu-lated by the CS8420, and does not have to be written into the last byte of the block by the host microcon-troller. DtoEinterruptoccursOptionallysetDtoEinhibitReadEdataIfset,clearDtoEinhibitReturnFigure 39. Flowchart for Reading the E Buffer 82DS245F4 元器件交易网www.cecb2b.com CS8420 . EtoFinterruptoccursOptionallysetEtoFinhibitSetDtoEinhibitWriteEdataIfset,clearEtoFinhibitWaitforEtoFtransferClearDtoEinhibitReturnFigure 40. Flowchart for Writing the E Buffer 15.1.2Reserving the First 5 Bytes in the E Buffer D-to-E buffer transfers periodically overwrite the data stored in the E buffer. This can be a problem forusers who want to transmit certain channel status settings which are different from the incoming settings.In this case, the user would have to superimpose his settings on the E buffer after every D-to-E overwrite.To avoid this problem, the CS8420 has the capability of reserving the first 5 bytes of the Ebuffer for userwrites only. When this capability is in use, internal D-to-E buffer transfers will NOT affect the first 5 bytesof the E buffer. Therefore, the user can set values in these first 5 E bytes once, and the settings will persistuntil the next user change. This mode is enabled via the Channel Status Data Buffer Control register. 15.1.3Serial Copy Management System(SCMS) In Software mode, the CS8420 allows read/modify/write access to all the channel status bits. For Con-sumer mode SCMS compliance, the host microcontroller needs to read and manipulate the CategoryCode, Copy bit and L bit appropriately. In Hardware mode, the SCMS protocol can be followed by either using the COPY and ORIG input pins,or by using the C bit serial input pin. These options are documented in the Hardware mode section of thisdata sheet (See “Hardware Modes” on page55) 15.1.4Channel Status Data E Buffer Access The E buffer is organized as 24 x 16-bit words. For each word the MS Byte is the A channel data, and theLS Byte is the B channel data (see Figure37). There are two methods of accessing this memory, known as one-byte mode and two-byte mode. The de-sired mode is selected via a control register bit. DS245F483 元器件交易网www.cecb2b.com CS8420 15.1.5One-Byte Mode In many applications, the channel status blocks for the A and B channels will be identical. In this situation,if the user reads a byte from one of the channel's blocks, the corresponding byte for the other channel willbe the same. Similarly, if the user wrote a byte to one channel's block, it would be necessary to write thesame byte to the other block. One-Byte mode takes advantage of the often identical nature of A and Bchannel status data. When reading data in one-byte mode, a single byte is returned, which can be from channel A or B data,depending on a register control bit. If a write is being done, the CS8420 expects a single byte to be inputto its control port. This byte will be written to both the A and B locations in the addressed word. One-Byte mode saves the user substantial control port access time, as it effectively accesses 2 bytes’worth of information in 1 byte's worth of access time. If the control port's auto-increment addressing isused in combination with this mode, multi-byte accesses such as full-block reads or writes can be doneespecially efficiently. 15.1.6Two-Byte Mode There are those applications in which the A and B channel status blocks will not be the same, and theuser is interested in accessing both blocks. In these situations, Two-Byte mode should be used to accessthe E buffer. In this mode, a read will cause the CS8420 to output two bytes from its control port. The first byte out willrepresent the A channel status data, and the 2nd byte will represent the B channel status data. Writing issimilar, in that two bytes must now be input to the CS8420's control port. The A channel status data isfirst, Bchannel status data second. 15.2AES3 User (U) Bit Management The CS8420 U bit manager has four operating modes:Mode 1. Transmit all zerosMode 2. Block modeMode 3. ReservedMode 4. IEC Consumer B 15.2.1Mode 1: Transmit All Zeros Mode 1 causes only zeros to be transmitted in the output U data, regardless of E buffer contents or U dataembedded in an input AES3 data stream. This mode is intended for the user who does not want to trans-ceive U data, and simply wants the output U channel to contain no data. 15.2.2Mode 2: Block Mode Mode 2 is very similar to the scheme used to control the C bits. Entire blocks of U data are buffered frominput to output, using a cascade of three block-sized RAMs to perform the buffering. The user has accessto the second of these three buffers, denoted the E buffer, via the control port. Block mode is designedfor use in AES3 in, AES3 out situations in which input Udata is decoded using a microcontroller via thecontrol port. It is also the only mode in which the user can merge his/her own U data into the transmittedAES3 data stream. The U buffer access only operates in Two-Byte mode, since there is no concept of A and B blocks for userdata. The arrangement of the data in the each byte is that the MSB is the first received bit and is the first 84 DS245F4 元器件交易网www.cecb2b.com CS8420 transmitted bit. The first byte read is the first byte received, and the first byte sent is the first byte trans-mitted. 15.2.3IEC60958 Recommended U Data Format for Consumer Applications Modes (3) and (4) are intended for use in AES3 in, AES3 out situations, in which the input U data is for-matted as recommended in the “IEC60958 Digital Audio Interface, part 3: Consumer applications” docu-ment. In this format, “messages” are formed in the Udata from Information Units or IUs. An IU is 8 bits long, andthe MSB is always 1, and is called the start bit, or 'P' bit. The remaining 7-bits are called Q, R, S, T, U, V,& W, and carry the desired data. A “message” consists of 3 to 129 IUs. Multiple IUs are considered to be in the same message if they areseparated by 0 to 8 zeros, denoted here as filler. A filler sequence of nine or more zeros indicates an inter-message gap. The desired information is normally carried in the sequence of corresponding bits in theIUs. For example, the sequential Q bits from each IU make up the Q sub-code data that is used to indicateCompact Disk track information. This data is automatically extracted from the received IEC60958 stream,and is presented in the control port register map space. Where incoming U data is coded in the above format, and needs to be re-transmitted, the data transfercannot be done using shift registers, because of the different Fsi and Fso sampling clocks. Instead, inputdata must be buffered in a FIFO structure, and then read out by the AES3 transmitter at appropriate times.Each bit of each IU must be transceived; unlike the audio samples, there can be no sample rate conver-sion of the U data. Therefore, there are two potential problems:(1) Message Partitioning When Fso > Fsi, more data is transmitted than received per unit time. The FIFO will frequently be com-pletely emptied. Sensible behavior must occur when the FIFO is empty, otherwise, a single incoming mes-sage may be erroneously partitioned into multiple, smaller, messages.(2) Overwriting When Fso < Fsi, more data is received than transmitted per unit time. There is a danger of the FIFO be-coming completely full, allowing incoming data to overwrite data that has not yet been output through theAES3 transmitter. 15.2.4Mode (3): Reserved This mode has been removed. Use IEC Consumer mode B. 15.2.5Mode (4): IEC Consumer B In this mode, the partitioning problem is solved by buffering an entire message before starting to transmitit. In this scheme, zero-segments between messages will be expanded when Fso > Fsi, but the integrityof individual messages is preserved. The overwriting problem (when Fso < Fsi) is solved by only storing a portion of the input U data in theFIFO. Specifically, only the IUs themselves are stored (and not the zeros that provide inter-IU and inter-message “filler”). An inter-IU filler segment of fixed length (OF) will be added back to the messages at theFIFO output, where the length of OF is equal to the shortest observed input filler segment (IF). Storing only IUs (and not filler) within the FIFO makes it possible for the slower AES3 transmitter to “catchup” to the faster AES3 receiver as data is read out of the FIFO. This is because nothing is written into theFIFO when long strings of zeros are input to the AES-EBU receiver. During this time of no writing, the DS245F4 85 元器件交易网www.cecb2b.com CS8420 transmitter can read out data that had previously accumulated, allowing the FIFO to empty out. If the FIFObecomes completely empty, zeros are transmitted until a complete message is written into the FIFO.Mode 4 is not fail-safe; the FIFO can still get completely full if there isn't enough “zero-padding” betweenincoming messages. It is up to the user to provide proper padding, as defined below:Minimum padding = (Fsi/Fso - 1)*[8N + (N-1)*IF +9] + 9 where N is the number of IUs in the message, IF is the number of filler bits between each IU, and Fso ≤ Fsi.Example 1: Fsi/Fso = 2, N=4, IF=1: minimum proper padding is 53 bits.Example 2: Fsi/Fso = 1, N=4, IF=7: min proper padding is 9 bits. The CS8420 detects when an overwrite has occurred in the FIFO, and synchronously resets the entireFIFO structure to prevent corrupted U data from being merged into the transmitted AES3 data stream.The CS8420 can be configured to generate an interrupt when this occurs. Mode 4 is recommended for properly formatted U data where mode 3 cannot provide acceptable perfor-mance, either because of a too-extreme Fsi/Fso ratio, or because it's unacceptable to change the lengthsof filler segments. Mode 4 provides error-free performance over the complete range of Fsi/Fso ratios (pro-vided that the input messages are properly zero-padded for Fsi > Fso). 86DS245F4 元器件交易网www.cecb2b.com CS8420 16.PLL FILTER 16.1 General An on-chip Phase Locked Loop (PLL) is used to recover the clock from the incoming data stream. Figure41 is a simplified diagram of the PLL in CS8420 devices. When the PLL is locked to an AES3 input stream,it is updated at each preamble in the AES3 stream. This occurs at twice the sampling frequency, FS. Whenthe PLL is locked to ILRCK, it is updated at FS so that the duty cycle of the input doesn’t affect jitter.There are some applications where low jitter in the recovered clock, presented on the RMCK pin, is impor-tant. For this reason, the PLL has been designed to have good jitter attenuation characteristics, as shownin Figure44 and Figure45. In addition, the PLL has been designed to use only the preambles of the AES3stream to provide lock update information to the PLL. This results in the PLL being immune to data-depen-dent jitter effects because the AES3 preambles do not vary with the data. The PLL has the ability to lock onto a wide range of input sample rates with no external component changes.If the sample rate of the input subsequently changes, for example in a varispeed application, the PLL willonly track up to ±12.5% from the nominal center sample rate. The nominal center sample rate is the samplerate that the PLL first locks onto upon application of an AES3 data stream or after enabling the CS8420clocks by setting the RUN control bit. If the 12.5% sample rate limit is exceeded, the PLL will return to itswide lock range mode and re-acquire a new nominal center sample rate. INPUTPhaseComparatorand Charge PumpVCORfiltCfiltCripRMCK÷NFigure 41. PLL Block Diagram 16.2External Filter Components 16.2.1General The PLL behavior is affected by the external filter component values. Figure 5 on page 12 shows the rec-ommended configuration of the two capacitors and one resistor that comprise the PLL filter. In Table19and Table20, the component values shown for the 32to96kHz range have the highest corner frequencyjitter attenuation curve, takes the shortest time to lock, and offers the best output jitter performance. Thecomponent values shown in Table18 and Table20forthe8to96kHzrangeallows the lowest input sam-ple rate to be 8kHz, and increases the lock time of the PLL. Lock times are worst case for an Fsi transitionof 96kHz. DS245F4 87 元器件交易网www.cecb2b.com CS8420 16.2.2Capacitor Selection The type of capacitors used for the PLL filter can have a significant effect on receiver performance. Largeor exotic film capacitors are not necessary as their leads and the required longer circuit board traces addundesirable inductance to the circuit. Surface mount ceramic capacitors are a good choice because theirown inductance is low, and they can be mounted close to the FILT pin to minimize trace inductance. ForCRIP, a C0G or NPO dielectric is recommended, and for CFILT, an X7R dielectric is preferred. Avoid ca-pacitors with large temperature coefficients, or capacitors with high dielectric constants, that are sensitiveto shock and vibration. These include the Z5U and Y5V dielectrics. 16.2.3Circuit Board Layout Board layout and capacitor choice affect each other and determine the performance of the PLL. Figure42 contains a suggested layout for the PLL filter components and for bypassing the analog supply voltage.The 0.1µF bypass capacitor is in a 1206 form factor. RFILT and the other three capacitors are in an 0805form factor. The traces are on the top surface of the board with the IC so that there is no via inductance.The traces themselves are short to minimize the inductance in the filter path. The VA+ and AGND tracesextend back to their origin and are shown only in truncated form in the drawing. AGND1000pFCripRfilt.1µFCfiltFigure 42. Recommended Layout Example 16.3Component Value Selection When transitioning from one revision of the part another, component values need to be changed. It is man-datory for customers to change the external PLL component values when transitioning from revision D torevision D1. 16.3.1Identifying the Part Revision The first line of the part marking on the package indicates the part number and package type CS8420-xx. Table17 shows a list of part revisions and their corresponding second line part marking,which indicates what revision the part is. Revision DD1 Pre-October 2002 (10-Digit) ZxxxxxxxxxRxxxxxxxxx Table 17. Second Line Part Marking FILTVA+New (12-Digit)ZFBADXxxxxxxRFBAD1xxxxxx 88DS245F4 元器件交易网www.cecb2b.com CS8420 16.3.2Locking to the RXP/RXN Receiver Inputs CS8420 parts that are configured to lock to only the RXP/RXN receiver inputs should use the externalPLL component values listed in Table18 and Table19. Values listed for the 32to96kHz Fs range willhave the highest corner frequency jitter attenuation curve, take the shortest time to lock, and offer the bestoutput jitter performance. Revision DD1 RFILT (kΩ)0.9090.4 CFILT (μF) 1.80.47 CRIP (nF) 3347 PLL Lock Time (ms) 5660 Table 18. Locking to RXP/RXN - Fs = 8 to 96 kHz Revision DD1 RFILT (kΩ) 3.01.6 CFILT (μF)0.0470.33 CRIP (nF)2.24.7 PLL Lock Time (ms) 3535 Table 19. Locking to RXP/RXN - Fs = 32 to 96 kHz* * Parts used in applications that are required to pass the AES3 or IEC60958-4 specification for receiverjitter tolerance should use these component values. Please note that the AES3 and IEC60958 specifica-tions do not have allowances for locking to sample rates less than 32 kHz or for locking to the ILRCK input.Also note that many factors can affect jitter performance in a system. Please follow the circuit and layoutrecommendations outlined previously. 16.3.3Locking to the ILRCK Input CS8420 parts that are configured to lock to the ILRCK input should use the external PLL component val-ues listed in Table20. Note that parts that need to lock to both ILRCK and RXP/RXN should usethese values. Values listed for the 32to96kHz Fs range will have the highest corner frequency jitter at-tenuation curve, take the shortest time to lock, and offer the best output jitter performance. Fs Range RFILT (kΩ)CFILT (μF)CRIP (nF)PLL Lock Time (ms)Revision(kHz) D8 to 961.32.762120 DD1D1 32-968 to 9632-96 5.10.30.6 0.151.00.22 3.910022 7012070 Table 20. Locking to the ILRCK Input DS245F489 元器件交易网www.cecb2b.com CS8420 16.3.4Jitter Tolerance Shown in Figure43 is the Receiver Jitter Tolerance template as illustrated in the AES3 and IEC60958-4specification. CS8420 parts used with the appropriate external PLL component values (as noted inTable19) have been tested to pass this template. Figure 43. Jitter Tolerance Template 16.3.5Jitter Attenuation Shown in Figure44 and Figure45 are jitter attenuation plots for the various revisions of the CS8420 whenused with the appropriate external PLL component values (as noted in Table19). The AES3 andIEC60958-4 specifications do not have allowances for locking to sample rates less than 32kHz or for lock-ing to the ILRCK input. These specifications state a maximum of 2dB jitter gain or peaking. 5500−5Jitter Attenuation (dB)−5Jitter Attenuation (dB)100−10−10−15−15−20−20−11010110Jitter Frequency (Hz)2103104105−25−11010010110Jitter Frequency (Hz)2103104105Figure 44. Revision D Jitter AttenuationFigure 45. Revision D1 Jitter Attenuation 90DS245F4 元器件交易网www.cecb2b.com CS8420 17.PARAMETER DEFINITIONS Input Sample Rate (Fsi) The sample rate of the incoming digital audio. Input Frame Rate The frame rate of the received AES3 format data. Output Sample Rate (Fso) The sample rate of the outgoing digital audio. Output Frame Rate The frame rate of the transmitted AES3 format data. Dynamic Range The ratio of the maximum signal level to the noise floor. Total Harmonic Distortion and Noise The ratio of the noise and distortion to the test signal level. Normally referenced to 0dBFS. Peak Idle Channel Noise Component With an all-zero input, what is the amplitude of the largest frequency component visible with a 16K pointFFT. The value is in dB ratio to full-scale. Input Jitter Tolerance The amplitude of jitter on the AES3 stream, or in the ILRCK clock, that will cause measurable artifacts in theSRC output. Test signal is full scale 9kHz, Fsi is 48kHz, Fso is different 48kHz, jitter is 2kHz sinusoidal,and audio band white noise. AES3 Transmitter Output Jitter With a jitter free OMCK clock, what is the jitter added by the AES3 transmitter. Gain Error The difference in amplitude between the output and the input signal level, within the passband of the digitalfilter in the SRC. DS245F491 元器件交易网www.cecb2b.com CS8420 18.PACKAGE DIMENSIONS 28L SOIC (300 MIL BODY) PACKAGE DRAWING EH 1b c D SEATINGPLANE e A1L A ∝INCHES DIM MIN MAX0.1040.0120.0200.0130.7130.2990.0600.4190.0508° A 0.093A10.004B0.013C0.009D0.697E0.291e0.040H0.394L0.016 0°∝MILLIMETERS MINMAX2.350.100.330.2317.707.401.0210.000.400° 2.650.300.510.3218.107.601.5210.651.278° THERMAL CHARACTERISTICS AND SPECIFICATIONS Parameter Junction to Ambient thermal impedance (28 pin SOIC)Allowable Junction Temperature Symbol Min TypθJATJ --65- Max-135 Units°C/W°C 92DS245F4 元器件交易网www.cecb2b.com CS8420 19.ORDERING INFORMATION Product Description PackagePb-Free No CS8420 Digital Audio Sample 28-SOIC Rate Converter Grade Temp Range ContainerRailRailRail Order#CS8420-CSCS8420-CSZCS8420-DSZ Commercial-10º to +70ºCCommercial-10º to +70ºC Yes Automotive-40º to +85ºC CDB8420 Evaluation Board for CS8420 ---- Tape and ReelCS8420-CSRTape and ReelCS8420-CSZRTape and ReelCS8420-DSZR -CDB8420 20.REVISION HISTORY Release PP1PP2PP3PP4 1st Preliminary Release2nd Preliminary Release3rd Preliminary Release Changes -Added IS package to front page. -Added IS package to “Ambient Operating Temperature:” on page6. -Corrected “Minimizing Group Delay Through Multiple CS8420s When Locking to ILRCK” on page28.-Revised “SRC Invalid State” on page49. -Added DS package to front page. -Added DS package to “Ambient Operating Temperature:” on page6.-Corrected “tdpd” on page9.-Corrected “tlmd” on page9.-Corrected “tsmd” on page9.-Corrected “tdh” on page10. -Added “C/U Buffer Data Corruption” on page49-Added lead-free ordering information. Final Release 1 -Changed format of Figure 17 on page 20 and Figure 18 on page 21. -Changed SORES description to refer to sample rate converter as data source in “Serial Audio Output Port Data Format (06h)” on page39. -Added “Transmitter Startup” on page48. -Integrated D1 Errata in Section 16.2 on page87 . Final Release 2 -Updated Ordering Information. -Added “Block-Mode U-Data D-to-E Buffer Transfers” on page50.Final Release 3 -Updated Ordering Information. Final Release 4 -Updated Leaded/Lead-Free information in “Ordering Information” on page93. PP5 PP6 F1 F2F3F4 DS245F493 元器件交易网www.cecb2b.com CS8420 Contacting Cirrus Logic Support For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find the one nearest you, go to www.cirrus.com IMPORTANT NOTICECirrus Logic, Inc. and its subsidiaries (\"Cirrus\") believe that the information contained in this document is accurate and reliable. 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All other brand and product names in this document may be trademarksor service marks of their respective owners.SPI is a trademark of Motorola Inc.AC-3 is a registered trademark of Dolby Laboratories, Inc.I²C is a registered trademark of Philips Semiconductor.94DS245F4 因篇幅问题不能全部显示，请点此查看更多更全内容