元器件交易网www.cecb2b.comMC74HC4040A12-StageBinaryRippleCounterHigh–Performance Silicon–Gate CMOSThe MC74C4040A is identical in pinout to the standard CMOSMC14040. The device inputs are compatible with standard CMOSoutputs; with pullup resistors, they are compatible with LSTTLoutputs.This device consists of 12 master–slave flip–flops. The output ofeach flip–flop feeds the next and the frequency at each output is half ofthat of the preceding one. The state counter advances on thenegative–going edge of the Clock input. Reset is asynchronous andactive–high.State changes of the Q outputs do not occur simultaneously becauseof internal ripple delays. Therefore, decoded output signals are subjectto decoding spikes and may have to be gated with the Clock of theHC4040A for some designs.http://onsemi.comMARKINGDIAGRAMS16161PDIP–16N SUFFIXCASE 8MC74HC4040ANAWLYYWW116161SO–16D SUFFIXCASE 751B1HC4040AAWLYWW•••••••Output Drive Capability: 10 LSTTL LoadsOutputs Directly Interface to CMOS, NMOS, and TTLOperating Voltage Range: 2 to 6 VLow Input Current: 1 µAHigh Noise Immunity Characteristic of CMOS DevicesIn Compliance With JEDEC Standard No. 7A RequirementsChip Complexity: 398 FETs or 99.5 Equivalent GatesLOGIC DIAGRAM9765Clock10324131214151Reset11Q1Q2Q3Q4Q5Q6Q7Q8Q9Q10Q11Q1216TSSOP–16DT SUFFIXCASE 948F1AWLYYWW= Assembly Location= Wafer Lot= Year= Work WeekHC4040AALYW161FUNCTION TABLEClockResetLLHOutput StateNo ChargeAdvance to Next StateAll Outputs Are LowXORDERING INFORMATIONDeviceMC74HC4040ANMC74HC4040ADQ19MC74HC4040ADR2MC74HC4040ADTMC74HC4040ADTR2PackagePDIP–16SOIC–16SOIC–16TSSOP–16TSSOP–16Shipping2000 / Box48 / Rail2500 / Reel96 / Rail2500 / ReelPin 16 = VCCPin 8 = GNDQ813Q912ResetClock1110VCC16Q1115Q1014Pinout: 16–Lead Plastic Package(Top View)1Q122Q63QQ75Q46Q37Q28GND© Semiconductor Components Industries, LLC, 20001May, 2000 – Rev. 3Publication Order Number:MC74HC4040A/D元器件交易网www.cecb2b.comMC74HC4040AMAXIMUM RATINGS*SymbolVCCVinIinVoutIoutParameterValueUnitVVVDC Supply Voltage (Referenced to GND)DC Input Voltage (Referenced to GND)– 0.5 to + 7.0– 0.5 to VCC + 0.5– 0.5 to VCC + 0.5±20±25±50750500450DC Output Voltage (Referenced to GND)DC Input Current, per PinmAmAmADC Output Current, per PinICCPDDC Supply Current, VCC and GND PinsPower Dissipation in Still Air,Plastic DIP†SOIC Package†TSSOP Package†mWThis device contains protectioncircuitry to guard against damagedue to high static voltages or electricfields. However, precautions mustbe taken to avoid applications of anyvoltage higher than maximum ratedvoltages to this high–impedance cir-cuit. For proper operation, Vin andVout should be constrained to therange GND v (Vin or Vout) v VCC.Unused inputs must always betied to an appropriate logic voltagelevel (e.g., either GND or VCC).Unused outputs must be left open.TstgTLStorage Temperature Range– 65 to + 150260_C_CLead Temperature, 1 mm from Case for 10 SecondsPlastic DIP, SOIC or TSSOP Package*Maximum Ratings are those values beyond which damage to the device may occur.Functional operation should be restricted to the Recommended Operating Conditions.†Derating—Plastic DIP: – 10 mW/_C from 65_ to 125_CSOIC Package: – 7 mW/_C from 65_ to 125_CTSSOP Package: – 6.1 mW/_C from 65_ to 125_CFor high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).RECOMMENDED OPERATING CONDITIONSSymbolVCCVin, VoutTAtr, tfParameterDC Supply Voltage (Referenced to GND)DC Input Voltage, Output Voltage (Referenced to GND)Operating Temperature Range, All Package TypesInput Rise and Fall Time(Figure 1)VCC = 2.0 VVCC = 3.0 VVCC = 4.5 VVCC = 6.0 VMin2.00– 550000Max6.0VCC+ 1251000600500400UnitVV_CnsDC CHARACTERISTICS (Voltages Referenced to GND)SymbolVIHParameterMinimum High–Level InputVoltageConditionVout = 0.1V or VCC –0.1V|Iout| ≤ 20µAVCCV2.03.04.56.02.03.04.56.02.04.56.0|Iout| ≤ 2.4mA|Iout| ≤ 4.0mA|Iout| ≤ 5.2mA3.04.56.02.04.56.0Guaranteed Limit–55 to 25°C1.502.103.1.200.500.901.351.801.94.45.92.483.985.480.10.10.1≤85°C1.502.103.1.200.500.901.351.801.94.45.92.343.845.340.10.10.1≤125°C1.502.103.1.200.500.901.351.801.94.45.92.203.705.200.10.10.1VUnitVVILMaximum Low–Level InputVoltageVout = 0.1V or VCC – 0.1V|Iout| ≤ 20µAVVOHMinimum High–Level OutputVoltageVin = VIH or VIL|Iout| ≤ 20µAVin =VIH or VILVVOLMaximum Low–Level OutputVoltageVin = VIH or VIL|Iout| ≤ 20µAhttp://onsemi.com2元器件交易网www.cecb2b.comMC74HC4040ADC CHARACTERISTICS (Voltages Referenced to GND)SymbolParameterConditionVin = VIH or VIL|Iout| ≤ 2.4mA|Iout| ≤ 4.0mA|Iout| ≤ 5.2mAVCCV3.04.56.06.06.0Guaranteed Limit–55 to 25°C0.260.260.26±0.14≤85°C0.330.330.33±1.040≤125°C0.400.400.40±1.0160µAµAUnitIinICCMaximum Input Leakage CurrentMaximum Quiescent SupplyCurrent (per Package)Vin = VCC or GNDVin = VCC or GNDIout = 0µANOTE:Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book(DL129/D).AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)SymbolfmaxParameterMaximum Clock Frequency (50% Duty Cycle)(Figures 1 and 4)VCCV2.03.04.56.02.03.04.56.02.03.04.56.02.03.04.56.02.03.04.56.0Guaranteed Limit–55 to 25°C1015305096633125303026694017147527151310≤85°C9.014284510671363052363532804521159532191510≤125°C8.012201158840356040359050282211036221910UnitMHztPLH,tPHLMaximum Propagation Delay, Clock to Q1*(Figures 1 and 4)nstPHLMaximum Propagation Delay, Reset to Any Q(Figures 2 and 4)nstPLH,tPHLMaximum Propagation Delay, Qn to Qn+1(Figures 3 and 4)nstTLH,tTHLMaximum Output Transition Time, Any Output(Figures 1 and 4)nsCinMaximum Input CapacitancepFNOTE:For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ONSemiconductor High–Speed CMOS Data Book (DL129/D).*For TA = 25°C and CL = 50 pF, typical propagation delay from Clock to other Q outputs may be calculated with the following equations:VCC = 2.0 V: tP = [93.7 + 59.3 (n–1)] nsVCC = 4.5 V: tP = [30.25 + 14.6 (n–1)] nsVCC = 3.0 V: tP = [61.5 + 34.4 (n–1)] nsVCC = 6.0V: tP = [24.4 + 12 (n–1)] nsTypical @ 25°C, VCC = 5.0 VCPDPower Dissipation Capacitance (Per Package)*31pF*Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of theON Semiconductor High–Speed CMOS Data Book (DL129/D).http://onsemi.com3元器件交易网www.cecb2b.comMC74HC4040ATIMING REQUIREMENTS (Input tr = tf = 6 ns)SymboltrecParameterMinimum Recovery Time, Reset Inactive to Clock(Figure 2)VCCV2.03.04.56.02.03.04.56.02.03.04.56.02.03.04.56.0Guaranteed Limit–55 to 25°C302070401513704015131000800500400≤85°C40258680451916804519161000800500400≤125°C503012990502420905024201000800500400UnitnstwMinimum Pulse Width, Clock(Figure 1)nstwMinimum Pulse Width, Reset(Figure 2)nstr, tfMaximum Input Rise and Fall Times(Figure 1)nsNOTE:Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book(DL129/D).PIN DESCRIPTIONSINPUTSClock (Pin 10)OUTPUTSQ1 thru Q12 (Pins 9, 7, 6, 5, 3, 2, 4, 13, 12, 14, 15, 1)Negative–edge triggering clock input. A high–to–lowtransition on this input advances the state of the counter.Reset (Pin 11)Active–high outputs. Each Qn output divides the Clockinput frequency by 2N.Active–high reset. A high level applied to this inputasynchronously resets the counter to its zero state, thusforcing all Q outputs low.SWITCHING WAVEFORMStfClock90%50%10%tw1/fMAXtPLHQ190%50%10%tTLHtTHLtPHLtrVCCGNDResettPHLAny Q50%Clocktrectw50%GND50%GNDVCCVCCFigure 1. Figure 2. http://onsemi.com4元器件交易网www.cecb2b.comMC74HC4040ASWITCHING WAVEFORMS (continued)TESTPOINTQnVCC50%GNDtPLHQn+150%*Includes all probe and jig capacitancetPHLDEVICEUNDERTESTOUTPUTCL*Figure 3. Figure 4. Test CircuitQ19Q27Q36Q1014Q1115Q121Clock10CQCQCQCQCQCQCRReset11QCRQCQCQCQCQ4 = Pin 5Q5 = Pin 3Q6 = Pin 2Q7 = Pin 4Q8 = Pin 13Q9 = Pin 12VCC = Pin 16GND = Pin 8Figure 5. Expanded Logic Diagramhttp://onsemi.com5元器件交易网www.cecb2b.comMC74HC4040A1ClockResetQ1Q2Q3Q4Q5Q6Q7Q8Q9Q10Q11Q122481632128256512102420484096Figure 6. Timing DiagramAPPLICATIONS INFORMATIONTime–Base GeneratorA 60Hz sinewave obtained through a 100 K resistorconnected to a 120 Vac power line through a step downtransformer is applied to the input of the MC/74HC14A,Schmitt-trigger inverter. The HC14A squares–up the inputVCC1/6 of HC14A100 K≥20 pFVCCwaveform and feeds the HC4040A. Selecting outputs Q5,Q10, Q11, and Q12 causes a reset every 3600 clocks. TheHC20 decodes the counter outputs, produces a single(narrow) output pulse, and resets the binary counter. Theresulting output frequency is 1.0 pulse/minute.HC4040AClockQ5Q10Q1113121091/2HC20812451/2HC201.0 Pulse/MinuteOutput6110 Vac15 – 30VoltsQ12Figure 7. Time–Base Generatorhttp://onsemi.com6元器件交易网www.cecb2b.comMC74HC4040APACKAGE DIMENSIONSPDIP–16N SUFFIXCASE 8–08ISSUE R–A–169B18NOTES:1.DIMENSIONING AND TOLERANCING PER ANSIY14.5M, 1982.2.CONTROLLING DIMENSION: INCH.3.DIMENSION L TO CENTER OF LEADS WHENFORMED PARALLEL.4.DIMENSION B DOES NOT INCLUDE MOLD FLASH.5.ROUNDED CORNERS OPTIONAL.DIMABCDFGHJKLMSINCHESMILLIMETERSMINMAXMINMAX0.7400.77018.8019.550.2500.2706.356.850.1450.1753.694.440.0150.0210.390.530.0400.701.021.770.100 BSC2. BSC0.050 BSC1.27 BSC0.0080.0150.210.380.1100.1302.803.300.2950.3057.507.740 10 0 10 ____0.0200.0400.511.01FSCL–T–HKGD16 PLSEATINGPLANEJTAMM0.25 (0.010)MSOIC–16D SUFFIXCASE 751B–05ISSUE J–A–NOTES:1.DIMENSIONING AND TOLERANCING PER ANSIY14.5M, 1982.2.CONTROLLING DIMENSION: MILLIMETER.3.DIMENSIONS A AND B DO NOT INCLUDEMOLD PROTRUSION.4.MAXIMUM MOLD PROTRUSION 0.15 (0.006)PER SIDE.5.DIMENSION D DOES NOT INCLUDE DAMBARPROTRUSION. ALLOWABLE DAMBARPROTRUSION SHALL BE 0.127 (0.005) TOTALIN EXCESS OF THE D DIMENSION ATMAXIMUM MATERIAL CONDITION.MILLIMETERSINCHESMINMAXMINMAX9.8010.000.3860.3933.804.000.1500.1571.351.750.00.0680.350.490.0140.0190.401.250.0160.0491.27 BSC0.050 BSC0.190.250.0080.0090.100.250.0040.0090 7 0 7 ____5.806.200.2290.2440.250.500.0100.019169–B–18P8 PL0.25 (0.010)MBSGFKC–T–SEATINGPLANERX 45_MD16 PLMJ0.25 (0.010)TBSASDIMABCDFGJKMPRhttp://onsemi.com7元器件交易网www.cecb2b.com
MC74HC4040A
PACKAGE DIMENSIONS
TSSOP–16DT SUFFIXCASE 948F–01ISSUE O
M16X REFK0.10 (0.004)0.15 (0.006)TUSTUSVSKK11692XL/2J1B–U–LPIN 1IDENT.18SECTION N–NJN0.15 (0.006)TUS0.25 (0.010)MA–V–NFDETAIL ENOTES:1.DIMENSIONING AND TOLERANCING PER ANSIY14.5M, 1982.
2.CONTROLLING DIMENSION: MILLIMETER.
3.DIMENSION A DOES NOT INCLUDE MOLD FLASH.PROTRUSIONS OR GATE BURRS. MOLD FLASH ORGATE BURRS SHALL NOT EXCEED 0.15 (0.006) PERSIDE.
4.DIMENSION B DOES NOT INCLUDE INTERLEADFLASH OR PROTRUSION. INTERLEAD FLASH ORPROTRUSION SHALL NOT EXCEED0.25 (0.010) PER SIDE.
5.DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSIONSHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE KDIMENSION AT MAXIMUM MATERIAL CONDITION.6.TERMINAL NUMBERS ARE SHOWN FORREFERENCE ONLY.
7.DIMENSION A AND B ARE TO BE DETERMINED ATDATUM PLANE –W–.
MILLIMETERSMINMAX4.905.104.304.50–––1.200.050.150.500.750.65 BSC0.180.280.090.200.090.160.190.300.190.256.40 BSC0 8 __INCHES
MINMAX0.1930.2000.1690.177–––0.0470.0020.0060.0200.0300.026 BSC0.0070.0110.0040.0080.0040.0060.0070.0120.0070.0100.252 BSC0 8 __C0.10 (0.004)–T–SEATINGPLANE–W–DGHDETAIL EDIMABCDFGHJJ1KK1LM
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changeswithout further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particularpurpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/orspecifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must bevalidated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applicationsintended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury ordeath may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and holdSCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonableattorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claimalleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
CENTRAL/SOUTH AMERICA:
Spanish Phone:303–308–7143 (Mon–Fri 8:00am to 5:00pm MST)
Email:ONlit–spanish@hibbertco.comASIA/PACIFIC: LDC for ON Semiconductor – Asia Support
Phone:303–675–2121 (Tue–Fri 9:00am to 1:00pm, Time)
Toll Free from & Singapore:001–800–4422–3781
Email: ONlit–asia@hibbertco.com
JAPAN: ON Semiconductor, Japan Customer Focus Center
4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–Phone: 81–3–5740–2745Email: r14525@onsemi.com
ON Semiconductor Website: http://onsemi.comFor additional information, please contact your localSales Representative.http://onsemi.com8MC74HC4040A/D
