Tile-based processor architecture model for high-e

专利名称：Tile-based processor architecture model for

high-efficiency embedded homogeneousmulticore platforms

发明人：Philippe Manet,Bertrand Rousseau申请号：US13576219申请日：20110131公开号：US09275002B2公开日：20160301

专利附图：

摘要：The present invention relates to a processor which comprises processingelements that execute instructions in parallel and are connected together with point-to-

point communication links called data communication links (DCL). The instructions useDCLs to communicate data between them. In order to realize those communications, theyspecify the DCLs from which they take their operands, and the DCLs to which they writetheir results. The DCLs allow the instructions to synchronize their executions and toexplicitly manage the data they manipulate. Communications are explicit and are used torealize the storage of temporary variables, which is decoupled from the storage of long-living variables.

申请人：Philippe Manet,Bertrand Rousseau

地址：Brussels BE,Chastre BE

国籍：BE,BE

代理机构：Young & Thompson

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