1用阻塞方式设计一个2选1的多路选择器 module
mux2_1(ina,inb,sel,out); input ina,inb; input sel; output out; reg out;
always@(sel or ina or inb) case(sel) 1'b1:out=ina; default:out=inb; endcase endmodule
2 设计一个8位全加器module
adder7(ina,inb,ci,sum,co); input[7:0] ina,inb; input ci; output[7:0]sum; output co; reg[7:0]sum; reg[4:0] carry; genvar i;
generate for(i=0;i<4;i=i+1) begin:r_loop always@(ina[i] or inb[i] or carry[i]) begin carry[0]=ci;
sum[i]=ina[i]^inb[i]^carry[i];
carry[i+1]=ina[i]&inb[i]|ina[i ]&carry[i]|inb[i]&carry[i]; end
end
endgenerate
assign co=carry[4]; endmodule
3 同步复位的4位计数器module count4(clk,nrst,out); input clk,nrst;
output[4:0] out; reg[4:0] out;
always@(posedge clk) if(!nrst) out<=4'b0; else
out<=out+4'b1; endmodule
4 用case语句设计一个4 选1的数据选择器 module
mux4_1(en ,in1 ,in2 ,in3 ,in4 ,sel ,out ); input en ; input [7:0] in1 ,in2 ,in3 ,in4 ; input [1:0] sel ; output [7:0] out ; reg [7:0] out ; always @(sel or en or in4 or in1 or in2 or in3 ) begin
if (en == 0) out = {8{1'b0}}; else case (sel ) 0 : out = in1 ;
1 : out = in 2 ;
2 : out = in 3 ;
3 : out = in 4 ;
default : out = {8{1'b0}}; endcase end endmodule
5 设计一个8-3优先编码器 module
encoder83(in,outcode); output[2:0] outcode; input [7:0] in; function[2:0] code; input[7:0] ina; if(ina[0]) code=3'b000;
else if(ina[1]) c ode=3'b001; else if(ina[2]) c ode=3'b010; else if(ina[3]) c ode=3'b011; else if(ina[4]) c ode=3'b100; else if(ina[5]) code=3'b101;
else if(ina[6]) c ode=3'b110; else if(ina[7]) c ode=3'b111; else code=3'bx; endfunction
assign outcode=code(in); endmodule
module bianma83(a,b); input [7:0] a; output [2:0] b; reg [2:0] b; always @ (a) begin casex(a)
8'b00000001:b=3'b000; 8'b0000001x:b=3'b001; 8'b000001xx:b=3'b010; 8'b00001xxx:b=3'b011; 8'b0001xxxx:b=3'b100; 8'b001xxxxx:b=3'b101; 8'b01xxxxxx:b=3'b110; 8'b1xxxxxxx:b=3'b111; default:b=3'bx; endcase end endmodule
6.设计八功能的算术运算单 元(ALU)，其输入信号a和 b均为4位，功能选择信号 select为3位．输出信号out 为8位。算术运算单元alu 所执行的操作与select信号 有关，具体关系见下表。 module alu(a,b,sel,out); input a,b;
input[3:0]sel; output[3:0] out; reg[3:0]out;
always@(sel or a or b ) case(sel) 3'b000:out=a; 3'b001:out=a+b; 3'b010:out=a-b; 3'b011:out=a*b;
3'b100:out=(a>b)?a:b;/*if(a> b)out=a;else out=b;*/ 3'b101:out=(a 3'b110:out=a<<3;
3'b111:out=a>>3; default: out=4'bx; endcase Endmodule
module fiv4(clk,rst_n,o_clk); input clk,rst_n; output o_clk; reg o_clk; reg [1:0]cnt;
always @(posedge clk or negedge rst_n) begin if(!rst_n) cnt<=0; else if(cnt==3) cnt<=0; else
cnt<=cnt+1; end
always @(posedge clk or negedge rst_n) begin
if(!rst_n) o_clk<=0; else if(cnt<2) o_clk<=1; else o_clk<=0; end Endmodule
1 用组合逻辑设计ROM module rom(wr,rd,cs,addr,data);
parameter imgw=256,imgh=256; parameter wid=7; parameter addresswid=17; input wr,rd,cs;
input [addresswid-1:0] addr;
inout [wid:0] data; reg [wid:0]
ram[0:imgw*imgh]; always @(cs or wr or addr) begin if (!cs && !wr) ram[addr]=data; end
assign data = (!cs && !rd) ? ram[addr]: {(wid+1){1'bz}}; endmodule
2 设计一个2-4的译码器 module 2_4 (clk, rst_n, 2_data,4_data); input clk; input rst_n; input [1:0] 2_data; output [3:0] 4_data; always@(posedge clk, negedge rst_n) begin if (!rst_n) begin 2_data<= 0; 4_data<= 0; end else
case (2_data) 00 :
4_data<=4'b0001; 01 :
4_data<=4'b0010; 10:
4_data<=4'b0100; 11 :
4_data<=4'b1000; default :
4_data<=4'b0000; endcase end endmodule
3 使用always语句描述JK 触发器，上升沿触发，带有 同步清零功能。时钟上升沿 功能表如下： module
JK_FF(CLK,J,K,Q,RS,SET); input CLK,J,K,SET,RS; output Q; reg Q;
always @(posedge CLK or negedge RS or negedge SET) begin
if(!RS) Q <= 1'b0; else if(!SET) Q <= 1'b1; else case({J,K}) 2'b00 : Q <= Q; 2'b01 : Q <= 1'b0; 2'b10 : Q <= 1'b1; 2'b11 : Q <= ~Q; default: Q<= 1'bx; endcase end endmodule
4 用verilog代码，分别实 现下图电路结构， module
blocking( sel,clk,ina,inb,inc, qout);
input clk,sel,ina,inb,inc;
output qout; reg qout,w1;
always@(posedge clk) begin w1=ina|inb; if(sel)
qout=w1&inc; else qout=inc; end endmodule module
nonblocking( sel,clk,ina,inb,i nc,qout); input clk,sel,ina,inb,inc; output qout; reg qout,w1;
always@(posedge clk) begin w1<=ina|inb; if(sel)
qout<=w1&inc; else qout<=inc; end endmodule
5 按照下图系统的结构，用verilog代码实现 module
hello(ain,bin,sel,clock,rst_n, outa,outb); input[1:0] ain,bin; input sel; input clock; input rst_n;
output outa,outb; reg[1:0] result; wire eq0,eq1,eq2,eq3; wire nora,norb; reg outa,outb;
always@(ain or bin or sel) begin if(!sel) result<=ain; else
result<=bin; end
always@(result) begin case(result)
2'b00:{eq3,eq2,eq1,eq0}=4'b 0001; 2'b01:{eq3,eq2,eq1,eq0}=4'b 0010;
2'b10:{eq3,eq2,eq1,eq0}=4'b 0100;
2'b11:{eq3,eq2,eq1,eq0}=4'b 1000; default:; endcase end
always@(posedge clock or negedge rst_n) begin if(!rst_n) outa<=0; else
outa<=nora; end
always@(posedge clock or negedge rst_n) begin if(!rst_n) outb<=0; else
outb<=norb; end
assign nora=eq0^eq1; assign norb=eq2^eq3; endmodule
6 设计一个4位脉动进位计 数器 module
ripple_carry_counter(q,clk,rs t);
input clk,rst; output[3:0] q; tff t0(q[0],clk,rst); tff t1(q[1],clk,rst); tff t2 (q[2],clk,rst); tff t3(q[3],clk,rst); endmodule
module tff(q,clk,rst); input clk,rst; output q; wire d;
dff d1(q,d,clk,rst);
not n1(d,q); endmodule
module dff(q,d,clk,rst); input d,clk,rst; output q; reg q;
always@(negedge clk or posedge rst) if(rst) q<=0; else q<=d; endmodule
1将1个200kHz 时钟做2 分频、4 分频、8 分频，要 求分频后的3 个时钟同相， 而且与源时钟近似同相。并 编写测试代码进行验证 module clk_div_phase (rst, clk_200K, clk_100K, clk_50K, clk_25K); input clk_200K; input rst; output clk_100K, clk_50K, clk_25K; wire clk_100K, clk_50K, clk_25K; reg [2:0] cnt; always @ (posedge clk_200K or negedge rst)
if (!rst) cnt <= 3'b000; else
cnt <= cnt + 1;
assign clk_100K = ~cnt [0]; assign clk_50K = ~cnt [1]; assign clk_25K = ~cnt [2]; endmodule 测试模块
`timescale 1ns/1ps module clk_div_phase_tb; reg clk_200K; reg rst;
wire clk_100K, clk_50K, clk_25K; initial begin rst = 0; clk_200K = 0; # 10; rst = 1; # 3000; $stop; end
clk_div_phase
clk_div_phase_inst (.rst(rst), .clk_200K(clk_200K), .clk_100K(clk_100K), .clk_50K(clk_50K), .clk_25K(clk_25K)
); always # (2500) clk_200K = ~clk_200K; endmodule
2 用代码实现四位比较器的设计，并编写测试代码进行验证 module compare (A, B, AeqB, AgtB, AltB); input [3:0] A, B;
output reg AeqB, AgtB, AltB; always @(A, B) begin AeqB = 0; AgtB = 0; AltB = 0; if(A == B) AeqB = 1; else if (A > B) AgtB = 1; else AltB = 1; end
endmodule 3 用结构及建模方法，描述 一个4位全加器， 并编写测试代码进行验证 module
add4(a,b,cin,sum,cout); input a,b,cin; output sum,cout; wire s1,m1,m2,m3; and (m1,a,b), xor (s1,a,b), xor (sum,s1,cin); and (m2,s1,cin); or (cout,m1,m2); endmodule
`include \"full_add1.v\" module
add4_1(sum,cout,a,b,cin); output[3:0] sum; output cout; input[3:0] a,b; input cin; full_add1
f0(a[0],b[0],cin,sum[0],cin1); //级连描述 full_add1
f1(a[1],b[1],cin1,sum[1],cin2 ); full_add1
f2(a[2],b[2],cin2,sum[2],cin3 ); full_add1
f3(a[3],b[3],cin3,sum[3],cout );
endmodule
4设计一个8位补码平方器, 输入是8bit 补码，求其平 方和。并编写测试代码进行 验证
说明由于输入是补码，所以 当最高位是l 时，表示原值 是负数，需要按位取反，加 l 后再平方;当最高位是0 时，表示原值是正数，直接 求平方。
module squl(data_in,square); input [7:0] data_in; //输入是补码
output [15:0] square; wire [7:0] data_bar;
assign data_bar = ~data_in + 1;
assign square=(data_in[7])? (data_bar*data_bar) : (data_in*data_in); endmodule
5 设计一个串并转换电 路，使串行输入数据，并行 4位输出。并编写测试代码 验证 Module
counter_mod_8(clock,reset, Q);
input clock; //posedge effective input reset; output [2:0] Q; reg [2:0] Q; always@(posedge
clock or negedge reset) begin if(~reset) Q <= 3'd0; else Q <= Q + 1; end
endmodule 串转并模块： module
ser_to_par_8bit(ser_in,clk,rst ,out);
input ser_in,clk,rst; output [7:0] out; wire [7:0] out; reg[7:0] par_out; wire[2:0] count; counter_mod_8
f1(.clock(clk),.reset(rst),.Q(c ount));
always@(posedge clk or negedge rst) begin if(~rst)
par_out <= 8'b0000_0000; else begin
par_out <= {par_out[6:0],ser_in}; end end
assign out = (count == 7)? par_out : 8'b0000_0000; endmodule 测试模块
module test_ser_par; reg [7:0] data; wire data_in; reg clock, reset; wire [7:0] out; initial begin clock = 1'b0;
reset = 1'b0; #3 reset = 1'b1; data = 8'b1001_1101; #300 $stop; end always
#5clock = ~clock; always@(posedge clock) data
={data[6:0],data[7]}; assign data_in = data[7] ser_to_par_8bit
a(.ser_in(data_in),.clk(clock) ,.rst(reset),.out(out)); initial $monitor($time,\"reset= %b,d ata= %b,data_in= %b,out= % b\endmodule
6 设计一个并串转换电 路，是并行输入数据，串行 输出，并编写测试代码验证 module
para_to_seria(para_in,clock,r eset,ser_out); input [7:0] para_in; input reset,clock; output ser_out; wire ser_out; reg ser_out_buf; reg [7:0] data; assign
ser_out=reset?ser_out_buf:1' bz;
always@(posedge clock or negedge reset) begin if(~reset) begin ser_out_buf <= 1'b0; data <= para_in; end else begin data <=
{data[6:0],data[7]}; ser_out_buf <= data[7]; end end endmodule 测试模块
module test_para_to_ser; reg [7:0] para_in; reg clock,reset; wire out;
para_to_serial_8bit
f1(.para_in(para_in),.clock(cl ock),.reset(reset),.ser_out(out )); initial
$monitor($time,\"in_8bit = %b,reset= %b,ser_out= %b ,data=%b\1.data); initial begin
clock = 1'b0; reset = 1'b0; #3 reset = 1'b1; #300 $stop; end initial para_in = 8'b1010_0100; always
#5clock = ~clock; endmodule
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