专利名称：Method of and apparatus for testing A-D
converter with a source current
measurement and reduced external testterminals
发明人：Hiroshi Noda申请号：US08/734386申请日：19961017公开号：US05870042A公开日：19990209
摘要：When an upper reference voltage is erroneously reduced below a normal valuein a subranging A-D converter, a resistance block of a ladder resistance having a voltagelower than a proper one is selected and a lower reference voltage is necessarily reducedbelow an analog input voltage, so that all outputs of lower bits go high. Namely, a region(B1) where a current flowing to a comparator becomes constant without depending onthe value of an analog input voltage (Vin) appears. Presence of abnormality can bedetermined by detecting this. Thus, a functional test or a static linearity test of an A-Dconverter cell is made while remarkably reducing the number of external test terminals.
申请人：MITSUBISHI DENKI KABUSHIKI KAISHA
代理机构：Oblon, Spivak, McClelland, Maier & Neustadt, P
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